1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 ethmac: ethernet@ff3f0000 { 141 compatible = "amlogic,meson-axg-dwmac", 142 "snps,dwmac-3.70a", 143 "snps,dwmac"; 144 reg = <0x0 0xff3f0000 0x0 0x10000 145 0x0 0xff634540 0x0 0x8>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "macirq"; 148 clocks = <&clkc CLKID_ETH>, 149 <&clkc CLKID_FCLK_DIV2>, 150 <&clkc CLKID_MPLL2>; 151 clock-names = "stmmaceth", "clkin0", "clkin1"; 152 status = "disabled"; 153 154 mdio0: mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "snps,dwmac-mdio"; 158 }; 159 }; 160 161 apb: bus@ff600000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xff600000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 167 168 hdmi_tx: hdmi-tx@0 { 169 compatible = "amlogic,meson-g12a-dw-hdmi"; 170 reg = <0x0 0x0 0x0 0x10000>; 171 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 172 resets = <&reset RESET_HDMITX_CAPB3>, 173 <&reset RESET_HDMITX_PHY>, 174 <&reset RESET_HDMITX>; 175 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 176 clocks = <&clkc CLKID_HDMI>, 177 <&clkc CLKID_HTX_PCLK>, 178 <&clkc CLKID_VPU_INTR>; 179 clock-names = "isfr", "iahb", "venci"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 185 /* VPU VENC Input */ 186 hdmi_tx_venc_port: port@0 { 187 reg = <0>; 188 189 hdmi_tx_in: endpoint { 190 remote-endpoint = <&hdmi_tx_out>; 191 }; 192 }; 193 194 /* TMDS Output */ 195 hdmi_tx_tmds_port: port@1 { 196 reg = <1>; 197 }; 198 }; 199 200 periphs: bus@34400 { 201 compatible = "simple-bus"; 202 reg = <0x0 0x34400 0x0 0x400>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 206 207 periphs_pinctrl: pinctrl@40 { 208 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges; 212 213 gpio: bank@40 { 214 reg = <0x0 0x40 0x0 0x4c>, 215 <0x0 0xe8 0x0 0x18>, 216 <0x0 0x120 0x0 0x18>, 217 <0x0 0x2c0 0x0 0x40>, 218 <0x0 0x340 0x0 0x1c>; 219 reg-names = "gpio", 220 "pull", 221 "pull-enable", 222 "mux", 223 "ds"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&periphs_pinctrl 0 0 86>; 227 }; 228 229 cec_ao_a_h_pins: cec_ao_a_h { 230 mux { 231 groups = "cec_ao_a_h"; 232 function = "cec_ao_a_h"; 233 bias-disable; 234 }; 235 }; 236 237 cec_ao_b_h_pins: cec_ao_b_h { 238 mux { 239 groups = "cec_ao_b_h"; 240 function = "cec_ao_b_h"; 241 bias-disable; 242 }; 243 }; 244 245 emmc_pins: emmc { 246 mux-0 { 247 groups = "emmc_nand_d0", 248 "emmc_nand_d1", 249 "emmc_nand_d2", 250 "emmc_nand_d3", 251 "emmc_nand_d4", 252 "emmc_nand_d5", 253 "emmc_nand_d6", 254 "emmc_nand_d7", 255 "emmc_cmd"; 256 function = "emmc"; 257 bias-pull-up; 258 drive-strength-microamp = <4000>; 259 }; 260 261 mux-1 { 262 groups = "emmc_clk"; 263 function = "emmc"; 264 bias-disable; 265 drive-strength-microamp = <4000>; 266 }; 267 }; 268 269 emmc_ds_pins: emmc-ds { 270 mux { 271 groups = "emmc_nand_ds"; 272 function = "emmc"; 273 bias-pull-down; 274 drive-strength-microamp = <4000>; 275 }; 276 }; 277 278 emmc_clk_gate_pins: emmc_clk_gate { 279 mux { 280 groups = "BOOT_8"; 281 function = "gpio_periphs"; 282 bias-pull-down; 283 drive-strength-microamp = <4000>; 284 }; 285 }; 286 287 hdmitx_ddc_pins: hdmitx_ddc { 288 mux { 289 groups = "hdmitx_sda", 290 "hdmitx_sck"; 291 function = "hdmitx"; 292 bias-disable; 293 }; 294 }; 295 296 hdmitx_hpd_pins: hdmitx_hpd { 297 mux { 298 groups = "hdmitx_hpd_in"; 299 function = "hdmitx"; 300 bias-disable; 301 }; 302 }; 303 304 305 i2c0_sda_c_pins: i2c0-sda-c { 306 mux { 307 groups = "i2c0_sda_c"; 308 function = "i2c0"; 309 bias-disable; 310 drive-strength-microamp = <3000>; 311 312 }; 313 }; 314 315 i2c0_sck_c_pins: i2c0-sck-c { 316 mux { 317 groups = "i2c0_sck_c"; 318 function = "i2c0"; 319 bias-disable; 320 drive-strength-microamp = <3000>; 321 }; 322 }; 323 324 i2c0_sda_z0_pins: i2c0-sda-z0 { 325 mux { 326 groups = "i2c0_sda_z0"; 327 function = "i2c0"; 328 bias-disable; 329 drive-strength-microamp = <3000>; 330 }; 331 }; 332 333 i2c0_sck_z1_pins: i2c0-sck-z1 { 334 mux { 335 groups = "i2c0_sck_z1"; 336 function = "i2c0"; 337 bias-disable; 338 drive-strength-microamp = <3000>; 339 }; 340 }; 341 342 i2c0_sda_z7_pins: i2c0-sda-z7 { 343 mux { 344 groups = "i2c0_sda_z7"; 345 function = "i2c0"; 346 bias-disable; 347 drive-strength-microamp = <3000>; 348 }; 349 }; 350 351 i2c0_sda_z8_pins: i2c0-sda-z8 { 352 mux { 353 groups = "i2c0_sda_z8"; 354 function = "i2c0"; 355 bias-disable; 356 drive-strength-microamp = <3000>; 357 }; 358 }; 359 360 i2c1_sda_x_pins: i2c1-sda-x { 361 mux { 362 groups = "i2c1_sda_x"; 363 function = "i2c1"; 364 bias-disable; 365 drive-strength-microamp = <3000>; 366 }; 367 }; 368 369 i2c1_sck_x_pins: i2c1-sck-x { 370 mux { 371 groups = "i2c1_sck_x"; 372 function = "i2c1"; 373 bias-disable; 374 drive-strength-microamp = <3000>; 375 }; 376 }; 377 378 i2c1_sda_h2_pins: i2c1-sda-h2 { 379 mux { 380 groups = "i2c1_sda_h2"; 381 function = "i2c1"; 382 bias-disable; 383 drive-strength-microamp = <3000>; 384 }; 385 }; 386 387 i2c1_sck_h3_pins: i2c1-sck-h3 { 388 mux { 389 groups = "i2c1_sck_h3"; 390 function = "i2c1"; 391 bias-disable; 392 drive-strength-microamp = <3000>; 393 }; 394 }; 395 396 i2c1_sda_h6_pins: i2c1-sda-h6 { 397 mux { 398 groups = "i2c1_sda_h6"; 399 function = "i2c1"; 400 bias-disable; 401 drive-strength-microamp = <3000>; 402 }; 403 }; 404 405 i2c1_sck_h7_pins: i2c1-sck-h7 { 406 mux { 407 groups = "i2c1_sck_h7"; 408 function = "i2c1"; 409 bias-disable; 410 drive-strength-microamp = <3000>; 411 }; 412 }; 413 414 i2c2_sda_x_pins: i2c2-sda-x { 415 mux { 416 groups = "i2c2_sda_x"; 417 function = "i2c2"; 418 bias-disable; 419 drive-strength-microamp = <3000>; 420 }; 421 }; 422 423 i2c2_sck_x_pins: i2c2-sck-x { 424 mux { 425 groups = "i2c2_sck_x"; 426 function = "i2c2"; 427 bias-disable; 428 drive-strength-microamp = <3000>; 429 }; 430 }; 431 432 i2c2_sda_z_pins: i2c2-sda-z { 433 mux { 434 groups = "i2c2_sda_z"; 435 function = "i2c2"; 436 bias-disable; 437 drive-strength-microamp = <3000>; 438 }; 439 }; 440 441 i2c2_sck_z_pins: i2c2-sck-z { 442 mux { 443 groups = "i2c2_sck_z"; 444 function = "i2c2"; 445 bias-disable; 446 drive-strength-microamp = <3000>; 447 }; 448 }; 449 450 i2c3_sda_h_pins: i2c3-sda-h { 451 mux { 452 groups = "i2c3_sda_h"; 453 function = "i2c3"; 454 bias-disable; 455 drive-strength-microamp = <3000>; 456 }; 457 }; 458 459 i2c3_sck_h_pins: i2c3-sck-h { 460 mux { 461 groups = "i2c3_sck_h"; 462 function = "i2c3"; 463 bias-disable; 464 drive-strength-microamp = <3000>; 465 }; 466 }; 467 468 i2c3_sda_a_pins: i2c3-sda-a { 469 mux { 470 groups = "i2c3_sda_a"; 471 function = "i2c3"; 472 bias-disable; 473 drive-strength-microamp = <3000>; 474 }; 475 }; 476 477 i2c3_sck_a_pins: i2c3-sck-a { 478 mux { 479 groups = "i2c3_sck_a"; 480 function = "i2c3"; 481 bias-disable; 482 drive-strength-microamp = <3000>; 483 }; 484 }; 485 486 mclk0_a_pins: mclk0-a { 487 mux { 488 groups = "mclk0_a"; 489 function = "mclk0"; 490 bias-disable; 491 drive-strength-microamp = <3000>; 492 }; 493 }; 494 495 mclk1_a_pins: mclk1-a { 496 mux { 497 groups = "mclk1_a"; 498 function = "mclk1"; 499 bias-disable; 500 drive-strength-microamp = <3000>; 501 }; 502 }; 503 504 mclk1_x_pins: mclk1-x { 505 mux { 506 groups = "mclk1_x"; 507 function = "mclk1"; 508 bias-disable; 509 drive-strength-microamp = <3000>; 510 }; 511 }; 512 513 mclk1_z_pins: mclk1-z { 514 mux { 515 groups = "mclk1_z"; 516 function = "mclk1"; 517 bias-disable; 518 drive-strength-microamp = <3000>; 519 }; 520 }; 521 522 pdm_din0_a_pins: pdm-din0-a { 523 mux { 524 groups = "pdm_din0_a"; 525 function = "pdm"; 526 bias-disable; 527 }; 528 }; 529 530 pdm_din0_c_pins: pdm-din0-c { 531 mux { 532 groups = "pdm_din0_c"; 533 function = "pdm"; 534 bias-disable; 535 }; 536 }; 537 538 pdm_din0_x_pins: pdm-din0-x { 539 mux { 540 groups = "pdm_din0_x"; 541 function = "pdm"; 542 bias-disable; 543 }; 544 }; 545 546 pdm_din0_z_pins: pdm-din0-z { 547 mux { 548 groups = "pdm_din0_z"; 549 function = "pdm"; 550 bias-disable; 551 }; 552 }; 553 554 pdm_din1_a_pins: pdm-din1-a { 555 mux { 556 groups = "pdm_din1_a"; 557 function = "pdm"; 558 bias-disable; 559 }; 560 }; 561 562 pdm_din1_c_pins: pdm-din1-c { 563 mux { 564 groups = "pdm_din1_c"; 565 function = "pdm"; 566 bias-disable; 567 }; 568 }; 569 570 pdm_din1_x_pins: pdm-din1-x { 571 mux { 572 groups = "pdm_din1_x"; 573 function = "pdm"; 574 bias-disable; 575 }; 576 }; 577 578 pdm_din1_z_pins: pdm-din1-z { 579 mux { 580 groups = "pdm_din1_z"; 581 function = "pdm"; 582 bias-disable; 583 }; 584 }; 585 586 pdm_din2_a_pins: pdm-din2-a { 587 mux { 588 groups = "pdm_din2_a"; 589 function = "pdm"; 590 bias-disable; 591 }; 592 }; 593 594 pdm_din2_c_pins: pdm-din2-c { 595 mux { 596 groups = "pdm_din2_c"; 597 function = "pdm"; 598 bias-disable; 599 }; 600 }; 601 602 pdm_din2_x_pins: pdm-din2-x { 603 mux { 604 groups = "pdm_din2_x"; 605 function = "pdm"; 606 bias-disable; 607 }; 608 }; 609 610 pdm_din2_z_pins: pdm-din2-z { 611 mux { 612 groups = "pdm_din2_z"; 613 function = "pdm"; 614 bias-disable; 615 }; 616 }; 617 618 pdm_din3_a_pins: pdm-din3-a { 619 mux { 620 groups = "pdm_din3_a"; 621 function = "pdm"; 622 bias-disable; 623 }; 624 }; 625 626 pdm_din3_c_pins: pdm-din3-c { 627 mux { 628 groups = "pdm_din3_c"; 629 function = "pdm"; 630 bias-disable; 631 }; 632 }; 633 634 pdm_din3_x_pins: pdm-din3-x { 635 mux { 636 groups = "pdm_din3_x"; 637 function = "pdm"; 638 bias-disable; 639 }; 640 }; 641 642 pdm_din3_z_pins: pdm-din3-z { 643 mux { 644 groups = "pdm_din3_z"; 645 function = "pdm"; 646 bias-disable; 647 }; 648 }; 649 650 pdm_dclk_a_pins: pdm-dclk-a { 651 mux { 652 groups = "pdm_dclk_a"; 653 function = "pdm"; 654 bias-disable; 655 drive-strength-microamp = <500>; 656 }; 657 }; 658 659 pdm_dclk_c_pins: pdm-dclk-c { 660 mux { 661 groups = "pdm_dclk_c"; 662 function = "pdm"; 663 bias-disable; 664 drive-strength-microamp = <500>; 665 }; 666 }; 667 668 pdm_dclk_x_pins: pdm-dclk-x { 669 mux { 670 groups = "pdm_dclk_x"; 671 function = "pdm"; 672 bias-disable; 673 drive-strength-microamp = <500>; 674 }; 675 }; 676 677 pdm_dclk_z_pins: pdm-dclk-z { 678 mux { 679 groups = "pdm_dclk_z"; 680 function = "pdm"; 681 bias-disable; 682 drive-strength-microamp = <500>; 683 }; 684 }; 685 686 pwm_a_pins: pwm-a { 687 mux { 688 groups = "pwm_a"; 689 function = "pwm_a"; 690 bias-disable; 691 }; 692 }; 693 694 pwm_b_x7_pins: pwm-b-x7 { 695 mux { 696 groups = "pwm_b_x7"; 697 function = "pwm_b"; 698 bias-disable; 699 }; 700 }; 701 702 pwm_b_x19_pins: pwm-b-x19 { 703 mux { 704 groups = "pwm_b_x19"; 705 function = "pwm_b"; 706 bias-disable; 707 }; 708 }; 709 710 pwm_c_c_pins: pwm-c-c { 711 mux { 712 groups = "pwm_c_c"; 713 function = "pwm_c"; 714 bias-disable; 715 }; 716 }; 717 718 pwm_c_x5_pins: pwm-c-x5 { 719 mux { 720 groups = "pwm_c_x5"; 721 function = "pwm_c"; 722 bias-disable; 723 }; 724 }; 725 726 pwm_c_x8_pins: pwm-c-x8 { 727 mux { 728 groups = "pwm_c_x8"; 729 function = "pwm_c"; 730 bias-disable; 731 }; 732 }; 733 734 pwm_d_x3_pins: pwm-d-x3 { 735 mux { 736 groups = "pwm_d_x3"; 737 function = "pwm_d"; 738 bias-disable; 739 }; 740 }; 741 742 pwm_d_x6_pins: pwm-d-x6 { 743 mux { 744 groups = "pwm_d_x6"; 745 function = "pwm_d"; 746 bias-disable; 747 }; 748 }; 749 750 pwm_e_pins: pwm-e { 751 mux { 752 groups = "pwm_e"; 753 function = "pwm_e"; 754 bias-disable; 755 }; 756 }; 757 758 pwm_f_x_pins: pwm-f-x { 759 mux { 760 groups = "pwm_f_x"; 761 function = "pwm_f"; 762 bias-disable; 763 }; 764 }; 765 766 pwm_f_h_pins: pwm-f-h { 767 mux { 768 groups = "pwm_f_h"; 769 function = "pwm_f"; 770 bias-disable; 771 }; 772 }; 773 774 sdcard_c_pins: sdcard_c { 775 mux-0 { 776 groups = "sdcard_d0_c", 777 "sdcard_d1_c", 778 "sdcard_d2_c", 779 "sdcard_d3_c", 780 "sdcard_cmd_c"; 781 function = "sdcard"; 782 bias-pull-up; 783 drive-strength-microamp = <4000>; 784 }; 785 786 mux-1 { 787 groups = "sdcard_clk_c"; 788 function = "sdcard"; 789 bias-disable; 790 drive-strength-microamp = <4000>; 791 }; 792 }; 793 794 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 795 mux { 796 groups = "GPIOC_4"; 797 function = "gpio_periphs"; 798 bias-pull-down; 799 drive-strength-microamp = <4000>; 800 }; 801 }; 802 803 sdcard_z_pins: sdcard_z { 804 mux-0 { 805 groups = "sdcard_d0_z", 806 "sdcard_d1_z", 807 "sdcard_d2_z", 808 "sdcard_d3_z", 809 "sdcard_cmd_z"; 810 function = "sdcard"; 811 bias-pull-up; 812 drive-strength-microamp = <4000>; 813 }; 814 815 mux-1 { 816 groups = "sdcard_clk_z"; 817 function = "sdcard"; 818 bias-disable; 819 drive-strength-microamp = <4000>; 820 }; 821 }; 822 823 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 824 mux { 825 groups = "GPIOZ_6"; 826 function = "gpio_periphs"; 827 bias-pull-down; 828 drive-strength-microamp = <4000>; 829 }; 830 }; 831 832 spdif_in_a10_pins: spdif-in-a10 { 833 mux { 834 groups = "spdif_in_a10"; 835 function = "spdif_in"; 836 bias-disable; 837 }; 838 }; 839 840 spdif_in_a12_pins: spdif-in-a12 { 841 mux { 842 groups = "spdif_in_a12"; 843 function = "spdif_in"; 844 bias-disable; 845 }; 846 }; 847 848 spdif_in_h_pins: spdif-in-h { 849 mux { 850 groups = "spdif_in_h"; 851 function = "spdif_in"; 852 bias-disable; 853 }; 854 }; 855 856 spdif_out_h_pins: spdif-out-h { 857 mux { 858 groups = "spdif_out_h"; 859 function = "spdif_out"; 860 drive-strength-microamp = <500>; 861 bias-disable; 862 }; 863 }; 864 865 spdif_out_a11_pins: spdif-out-a11 { 866 mux { 867 groups = "spdif_out_a11"; 868 function = "spdif_out"; 869 drive-strength-microamp = <500>; 870 bias-disable; 871 }; 872 }; 873 874 spdif_out_a13_pins: spdif-out-a13 { 875 mux { 876 groups = "spdif_out_a13"; 877 function = "spdif_out"; 878 drive-strength-microamp = <500>; 879 bias-disable; 880 }; 881 }; 882 883 tdm_a_din0_pins: tdm-a-din0 { 884 mux { 885 groups = "tdm_a_din0"; 886 function = "tdm_a"; 887 bias-disable; 888 }; 889 }; 890 891 892 tdm_a_din1_pins: tdm-a-din1 { 893 mux { 894 groups = "tdm_a_din1"; 895 function = "tdm_a"; 896 bias-disable; 897 }; 898 }; 899 900 tdm_a_dout0_pins: tdm-a-dout0 { 901 mux { 902 groups = "tdm_a_dout0"; 903 function = "tdm_a"; 904 bias-disable; 905 drive-strength-microamp = <3000>; 906 }; 907 }; 908 909 tdm_a_dout1_pins: tdm-a-dout1 { 910 mux { 911 groups = "tdm_a_dout1"; 912 function = "tdm_a"; 913 bias-disable; 914 drive-strength-microamp = <3000>; 915 }; 916 }; 917 918 tdm_a_fs_pins: tdm-a-fs { 919 mux { 920 groups = "tdm_a_fs"; 921 function = "tdm_a"; 922 bias-disable; 923 drive-strength-microamp = <3000>; 924 }; 925 }; 926 927 tdm_a_sclk_pins: tdm-a-sclk { 928 mux { 929 groups = "tdm_a_sclk"; 930 function = "tdm_a"; 931 bias-disable; 932 drive-strength-microamp = <3000>; 933 }; 934 }; 935 936 tdm_a_slv_fs_pins: tdm-a-slv-fs { 937 mux { 938 groups = "tdm_a_slv_fs"; 939 function = "tdm_a"; 940 bias-disable; 941 }; 942 }; 943 944 945 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 946 mux { 947 groups = "tdm_a_slv_sclk"; 948 function = "tdm_a"; 949 bias-disable; 950 }; 951 }; 952 953 tdm_b_din0_pins: tdm-b-din0 { 954 mux { 955 groups = "tdm_b_din0"; 956 function = "tdm_b"; 957 bias-disable; 958 }; 959 }; 960 961 tdm_b_din1_pins: tdm-b-din1 { 962 mux { 963 groups = "tdm_b_din1"; 964 function = "tdm_b"; 965 bias-disable; 966 }; 967 }; 968 969 tdm_b_din2_pins: tdm-b-din2 { 970 mux { 971 groups = "tdm_b_din2"; 972 function = "tdm_b"; 973 bias-disable; 974 }; 975 }; 976 977 tdm_b_din3_a_pins: tdm-b-din3-a { 978 mux { 979 groups = "tdm_b_din3_a"; 980 function = "tdm_b"; 981 bias-disable; 982 }; 983 }; 984 985 tdm_b_din3_h_pins: tdm-b-din3-h { 986 mux { 987 groups = "tdm_b_din3_h"; 988 function = "tdm_b"; 989 bias-disable; 990 }; 991 }; 992 993 tdm_b_dout0_pins: tdm-b-dout0 { 994 mux { 995 groups = "tdm_b_dout0"; 996 function = "tdm_b"; 997 bias-disable; 998 drive-strength-microamp = <3000>; 999 }; 1000 }; 1001 1002 tdm_b_dout1_pins: tdm-b-dout1 { 1003 mux { 1004 groups = "tdm_b_dout1"; 1005 function = "tdm_b"; 1006 bias-disable; 1007 drive-strength-microamp = <3000>; 1008 }; 1009 }; 1010 1011 tdm_b_dout2_pins: tdm-b-dout2 { 1012 mux { 1013 groups = "tdm_b_dout2"; 1014 function = "tdm_b"; 1015 bias-disable; 1016 drive-strength-microamp = <3000>; 1017 }; 1018 }; 1019 1020 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1021 mux { 1022 groups = "tdm_b_dout3_a"; 1023 function = "tdm_b"; 1024 bias-disable; 1025 drive-strength-microamp = <3000>; 1026 }; 1027 }; 1028 1029 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1030 mux { 1031 groups = "tdm_b_dout3_h"; 1032 function = "tdm_b"; 1033 bias-disable; 1034 drive-strength-microamp = <3000>; 1035 }; 1036 }; 1037 1038 tdm_b_fs_pins: tdm-b-fs { 1039 mux { 1040 groups = "tdm_b_fs"; 1041 function = "tdm_b"; 1042 bias-disable; 1043 drive-strength-microamp = <3000>; 1044 }; 1045 }; 1046 1047 tdm_b_sclk_pins: tdm-b-sclk { 1048 mux { 1049 groups = "tdm_b_sclk"; 1050 function = "tdm_b"; 1051 bias-disable; 1052 drive-strength-microamp = <3000>; 1053 }; 1054 }; 1055 1056 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1057 mux { 1058 groups = "tdm_b_slv_fs"; 1059 function = "tdm_b"; 1060 bias-disable; 1061 }; 1062 }; 1063 1064 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1065 mux { 1066 groups = "tdm_b_slv_sclk"; 1067 function = "tdm_b"; 1068 bias-disable; 1069 }; 1070 }; 1071 1072 tdm_c_din0_a_pins: tdm-c-din0-a { 1073 mux { 1074 groups = "tdm_c_din0_a"; 1075 function = "tdm_c"; 1076 bias-disable; 1077 }; 1078 }; 1079 1080 tdm_c_din0_z_pins: tdm-c-din0-z { 1081 mux { 1082 groups = "tdm_c_din0_z"; 1083 function = "tdm_c"; 1084 bias-disable; 1085 }; 1086 }; 1087 1088 tdm_c_din1_a_pins: tdm-c-din1-a { 1089 mux { 1090 groups = "tdm_c_din1_a"; 1091 function = "tdm_c"; 1092 bias-disable; 1093 }; 1094 }; 1095 1096 tdm_c_din1_z_pins: tdm-c-din1-z { 1097 mux { 1098 groups = "tdm_c_din1_z"; 1099 function = "tdm_c"; 1100 bias-disable; 1101 }; 1102 }; 1103 1104 tdm_c_din2_a_pins: tdm-c-din2-a { 1105 mux { 1106 groups = "tdm_c_din2_a"; 1107 function = "tdm_c"; 1108 bias-disable; 1109 }; 1110 }; 1111 1112 tdm_c_din2_z_pins: tdm-c-din2-z { 1113 mux { 1114 groups = "tdm_c_din2_z"; 1115 function = "tdm_c"; 1116 bias-disable; 1117 }; 1118 }; 1119 1120 tdm_c_din3_a_pins: tdm-c-din3-a { 1121 mux { 1122 groups = "tdm_c_din3_a"; 1123 function = "tdm_c"; 1124 bias-disable; 1125 }; 1126 }; 1127 1128 tdm_c_din3_z_pins: tdm-c-din3-z { 1129 mux { 1130 groups = "tdm_c_din3_z"; 1131 function = "tdm_c"; 1132 bias-disable; 1133 }; 1134 }; 1135 1136 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1137 mux { 1138 groups = "tdm_c_dout0_a"; 1139 function = "tdm_c"; 1140 bias-disable; 1141 drive-strength-microamp = <3000>; 1142 }; 1143 }; 1144 1145 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1146 mux { 1147 groups = "tdm_c_dout0_z"; 1148 function = "tdm_c"; 1149 bias-disable; 1150 drive-strength-microamp = <3000>; 1151 }; 1152 }; 1153 1154 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1155 mux { 1156 groups = "tdm_c_dout1_a"; 1157 function = "tdm_c"; 1158 bias-disable; 1159 drive-strength-microamp = <3000>; 1160 }; 1161 }; 1162 1163 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1164 mux { 1165 groups = "tdm_c_dout1_z"; 1166 function = "tdm_c"; 1167 bias-disable; 1168 drive-strength-microamp = <3000>; 1169 }; 1170 }; 1171 1172 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1173 mux { 1174 groups = "tdm_c_dout2_a"; 1175 function = "tdm_c"; 1176 bias-disable; 1177 drive-strength-microamp = <3000>; 1178 }; 1179 }; 1180 1181 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1182 mux { 1183 groups = "tdm_c_dout2_z"; 1184 function = "tdm_c"; 1185 bias-disable; 1186 drive-strength-microamp = <3000>; 1187 }; 1188 }; 1189 1190 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1191 mux { 1192 groups = "tdm_c_dout3_a"; 1193 function = "tdm_c"; 1194 bias-disable; 1195 drive-strength-microamp = <3000>; 1196 }; 1197 }; 1198 1199 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1200 mux { 1201 groups = "tdm_c_dout3_z"; 1202 function = "tdm_c"; 1203 bias-disable; 1204 drive-strength-microamp = <3000>; 1205 }; 1206 }; 1207 1208 tdm_c_fs_a_pins: tdm-c-fs-a { 1209 mux { 1210 groups = "tdm_c_fs_a"; 1211 function = "tdm_c"; 1212 bias-disable; 1213 drive-strength-microamp = <3000>; 1214 }; 1215 }; 1216 1217 tdm_c_fs_z_pins: tdm-c-fs-z { 1218 mux { 1219 groups = "tdm_c_fs_z"; 1220 function = "tdm_c"; 1221 bias-disable; 1222 drive-strength-microamp = <3000>; 1223 }; 1224 }; 1225 1226 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1227 mux { 1228 groups = "tdm_c_sclk_a"; 1229 function = "tdm_c"; 1230 bias-disable; 1231 drive-strength-microamp = <3000>; 1232 }; 1233 }; 1234 1235 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1236 mux { 1237 groups = "tdm_c_sclk_z"; 1238 function = "tdm_c"; 1239 bias-disable; 1240 drive-strength-microamp = <3000>; 1241 }; 1242 }; 1243 1244 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1245 mux { 1246 groups = "tdm_c_slv_fs_a"; 1247 function = "tdm_c"; 1248 bias-disable; 1249 }; 1250 }; 1251 1252 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1253 mux { 1254 groups = "tdm_c_slv_fs_z"; 1255 function = "tdm_c"; 1256 bias-disable; 1257 }; 1258 }; 1259 1260 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1261 mux { 1262 groups = "tdm_c_slv_sclk_a"; 1263 function = "tdm_c"; 1264 bias-disable; 1265 }; 1266 }; 1267 1268 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1269 mux { 1270 groups = "tdm_c_slv_sclk_z"; 1271 function = "tdm_c"; 1272 bias-disable; 1273 }; 1274 }; 1275 1276 uart_a_pins: uart-a { 1277 mux { 1278 groups = "uart_a_tx", 1279 "uart_a_rx"; 1280 function = "uart_a"; 1281 bias-disable; 1282 }; 1283 }; 1284 1285 uart_a_cts_rts_pins: uart-a-cts-rts { 1286 mux { 1287 groups = "uart_a_cts", 1288 "uart_a_rts"; 1289 function = "uart_a"; 1290 bias-disable; 1291 }; 1292 }; 1293 1294 uart_b_pins: uart-b { 1295 mux { 1296 groups = "uart_b_tx", 1297 "uart_b_rx"; 1298 function = "uart_b"; 1299 bias-disable; 1300 }; 1301 }; 1302 1303 uart_c_pins: uart-c { 1304 mux { 1305 groups = "uart_c_tx", 1306 "uart_c_rx"; 1307 function = "uart_c"; 1308 bias-disable; 1309 }; 1310 }; 1311 1312 uart_c_cts_rts_pins: uart-c-cts-rts { 1313 mux { 1314 groups = "uart_c_cts", 1315 "uart_c_rts"; 1316 function = "uart_c"; 1317 bias-disable; 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 usb2_phy0: phy@36000 { 1324 compatible = "amlogic,g12a-usb2-phy"; 1325 reg = <0x0 0x36000 0x0 0x2000>; 1326 clocks = <&xtal>; 1327 clock-names = "xtal"; 1328 resets = <&reset RESET_USB_PHY20>; 1329 reset-names = "phy"; 1330 #phy-cells = <0>; 1331 }; 1332 1333 dmc: bus@38000 { 1334 compatible = "simple-bus"; 1335 reg = <0x0 0x38000 0x0 0x400>; 1336 #address-cells = <2>; 1337 #size-cells = <2>; 1338 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1339 1340 canvas: video-lut@48 { 1341 compatible = "amlogic,canvas"; 1342 reg = <0x0 0x48 0x0 0x14>; 1343 }; 1344 }; 1345 1346 usb2_phy1: phy@3a000 { 1347 compatible = "amlogic,g12a-usb2-phy"; 1348 reg = <0x0 0x3a000 0x0 0x2000>; 1349 clocks = <&xtal>; 1350 clock-names = "xtal"; 1351 resets = <&reset RESET_USB_PHY21>; 1352 reset-names = "phy"; 1353 #phy-cells = <0>; 1354 }; 1355 1356 hiu: bus@3c000 { 1357 compatible = "simple-bus"; 1358 reg = <0x0 0x3c000 0x0 0x1400>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1362 1363 hhi: system-controller@0 { 1364 compatible = "amlogic,meson-gx-hhi-sysctrl", 1365 "simple-mfd", "syscon"; 1366 reg = <0 0 0 0x400>; 1367 1368 clkc: clock-controller { 1369 compatible = "amlogic,g12a-clkc"; 1370 #clock-cells = <1>; 1371 clocks = <&xtal>; 1372 clock-names = "xtal"; 1373 }; 1374 }; 1375 }; 1376 1377 pdm: audio-controller@40000 { 1378 compatible = "amlogic,g12a-pdm", 1379 "amlogic,axg-pdm"; 1380 reg = <0x0 0x40000 0x0 0x34>; 1381 #sound-dai-cells = <0>; 1382 sound-name-prefix = "PDM"; 1383 clocks = <&clkc_audio AUD_CLKID_PDM>, 1384 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1385 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1386 clock-names = "pclk", "dclk", "sysclk"; 1387 status = "disabled"; 1388 }; 1389 1390 audio: bus@42000 { 1391 compatible = "simple-bus"; 1392 reg = <0x0 0x42000 0x0 0x2000>; 1393 #address-cells = <2>; 1394 #size-cells = <2>; 1395 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1396 1397 clkc_audio: clock-controller@0 { 1398 status = "disabled"; 1399 compatible = "amlogic,g12a-audio-clkc"; 1400 reg = <0x0 0x0 0x0 0xb4>; 1401 #clock-cells = <1>; 1402 1403 clocks = <&clkc CLKID_AUDIO>, 1404 <&clkc CLKID_MPLL0>, 1405 <&clkc CLKID_MPLL1>, 1406 <&clkc CLKID_MPLL2>, 1407 <&clkc CLKID_MPLL3>, 1408 <&clkc CLKID_HIFI_PLL>, 1409 <&clkc CLKID_FCLK_DIV3>, 1410 <&clkc CLKID_FCLK_DIV4>, 1411 <&clkc CLKID_GP0_PLL>; 1412 clock-names = "pclk", 1413 "mst_in0", 1414 "mst_in1", 1415 "mst_in2", 1416 "mst_in3", 1417 "mst_in4", 1418 "mst_in5", 1419 "mst_in6", 1420 "mst_in7"; 1421 1422 resets = <&reset RESET_AUDIO>; 1423 }; 1424 1425 toddr_a: audio-controller@100 { 1426 compatible = "amlogic,g12a-toddr", 1427 "amlogic,axg-toddr"; 1428 reg = <0x0 0x100 0x0 0x1c>; 1429 #sound-dai-cells = <0>; 1430 sound-name-prefix = "TODDR_A"; 1431 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1432 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1433 resets = <&arb AXG_ARB_TODDR_A>; 1434 status = "disabled"; 1435 }; 1436 1437 toddr_b: audio-controller@140 { 1438 compatible = "amlogic,g12a-toddr", 1439 "amlogic,axg-toddr"; 1440 reg = <0x0 0x140 0x0 0x1c>; 1441 #sound-dai-cells = <0>; 1442 sound-name-prefix = "TODDR_B"; 1443 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1444 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1445 resets = <&arb AXG_ARB_TODDR_B>; 1446 status = "disabled"; 1447 }; 1448 1449 toddr_c: audio-controller@180 { 1450 compatible = "amlogic,g12a-toddr", 1451 "amlogic,axg-toddr"; 1452 reg = <0x0 0x180 0x0 0x1c>; 1453 #sound-dai-cells = <0>; 1454 sound-name-prefix = "TODDR_C"; 1455 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1456 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1457 resets = <&arb AXG_ARB_TODDR_C>; 1458 status = "disabled"; 1459 }; 1460 1461 frddr_a: audio-controller@1c0 { 1462 compatible = "amlogic,g12a-frddr", 1463 "amlogic,axg-frddr"; 1464 reg = <0x0 0x1c0 0x0 0x1c>; 1465 #sound-dai-cells = <0>; 1466 sound-name-prefix = "FRDDR_A"; 1467 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1468 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1469 resets = <&arb AXG_ARB_FRDDR_A>; 1470 status = "disabled"; 1471 }; 1472 1473 frddr_b: audio-controller@200 { 1474 compatible = "amlogic,g12a-frddr", 1475 "amlogic,axg-frddr"; 1476 reg = <0x0 0x200 0x0 0x1c>; 1477 #sound-dai-cells = <0>; 1478 sound-name-prefix = "FRDDR_B"; 1479 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1480 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1481 resets = <&arb AXG_ARB_FRDDR_B>; 1482 status = "disabled"; 1483 }; 1484 1485 frddr_c: audio-controller@240 { 1486 compatible = "amlogic,g12a-frddr", 1487 "amlogic,axg-frddr"; 1488 reg = <0x0 0x240 0x0 0x1c>; 1489 #sound-dai-cells = <0>; 1490 sound-name-prefix = "FRDDR_C"; 1491 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1492 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1493 resets = <&arb AXG_ARB_FRDDR_C>; 1494 status = "disabled"; 1495 }; 1496 1497 arb: reset-controller@280 { 1498 status = "disabled"; 1499 compatible = "amlogic,meson-axg-audio-arb"; 1500 reg = <0x0 0x280 0x0 0x4>; 1501 #reset-cells = <1>; 1502 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1503 }; 1504 1505 tdmin_a: audio-controller@300 { 1506 compatible = "amlogic,g12a-tdmin", 1507 "amlogic,axg-tdmin"; 1508 reg = <0x0 0x300 0x0 0x40>; 1509 sound-name-prefix = "TDMIN_A"; 1510 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1511 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1512 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1513 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1514 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1515 clock-names = "pclk", "sclk", "sclk_sel", 1516 "lrclk", "lrclk_sel"; 1517 status = "disabled"; 1518 }; 1519 1520 tdmin_b: audio-controller@340 { 1521 compatible = "amlogic,g12a-tdmin", 1522 "amlogic,axg-tdmin"; 1523 reg = <0x0 0x340 0x0 0x40>; 1524 sound-name-prefix = "TDMIN_B"; 1525 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1526 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1527 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1528 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1529 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1530 clock-names = "pclk", "sclk", "sclk_sel", 1531 "lrclk", "lrclk_sel"; 1532 status = "disabled"; 1533 }; 1534 1535 tdmin_c: audio-controller@380 { 1536 compatible = "amlogic,g12a-tdmin", 1537 "amlogic,axg-tdmin"; 1538 reg = <0x0 0x380 0x0 0x40>; 1539 sound-name-prefix = "TDMIN_C"; 1540 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1541 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1542 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1543 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1544 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1545 clock-names = "pclk", "sclk", "sclk_sel", 1546 "lrclk", "lrclk_sel"; 1547 status = "disabled"; 1548 }; 1549 1550 tdmin_lb: audio-controller@3c0 { 1551 compatible = "amlogic,g12a-tdmin", 1552 "amlogic,axg-tdmin"; 1553 reg = <0x0 0x3c0 0x0 0x40>; 1554 sound-name-prefix = "TDMIN_LB"; 1555 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1556 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1557 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1558 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1559 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1560 clock-names = "pclk", "sclk", "sclk_sel", 1561 "lrclk", "lrclk_sel"; 1562 status = "disabled"; 1563 }; 1564 1565 spdifin: audio-controller@400 { 1566 compatible = "amlogic,g12a-spdifin", 1567 "amlogic,axg-spdifin"; 1568 reg = <0x0 0x400 0x0 0x30>; 1569 #sound-dai-cells = <0>; 1570 sound-name-prefix = "SPDIFIN"; 1571 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1572 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1573 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1574 clock-names = "pclk", "refclk"; 1575 status = "disabled"; 1576 }; 1577 1578 spdifout: audio-controller@480 { 1579 compatible = "amlogic,g12a-spdifout", 1580 "amlogic,axg-spdifout"; 1581 reg = <0x0 0x480 0x0 0x50>; 1582 #sound-dai-cells = <0>; 1583 sound-name-prefix = "SPDIFOUT"; 1584 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1585 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1586 clock-names = "pclk", "mclk"; 1587 status = "disabled"; 1588 }; 1589 1590 tdmout_a: audio-controller@500 { 1591 compatible = "amlogic,g12a-tdmout"; 1592 reg = <0x0 0x500 0x0 0x40>; 1593 sound-name-prefix = "TDMOUT_A"; 1594 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1595 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1596 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1597 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1598 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1599 clock-names = "pclk", "sclk", "sclk_sel", 1600 "lrclk", "lrclk_sel"; 1601 status = "disabled"; 1602 }; 1603 1604 tdmout_b: audio-controller@540 { 1605 compatible = "amlogic,g12a-tdmout"; 1606 reg = <0x0 0x540 0x0 0x40>; 1607 sound-name-prefix = "TDMOUT_B"; 1608 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1609 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1610 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1611 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1612 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1613 clock-names = "pclk", "sclk", "sclk_sel", 1614 "lrclk", "lrclk_sel"; 1615 status = "disabled"; 1616 }; 1617 1618 tdmout_c: audio-controller@580 { 1619 compatible = "amlogic,g12a-tdmout"; 1620 reg = <0x0 0x580 0x0 0x40>; 1621 sound-name-prefix = "TDMOUT_C"; 1622 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1623 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1624 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1625 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1626 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1627 clock-names = "pclk", "sclk", "sclk_sel", 1628 "lrclk", "lrclk_sel"; 1629 status = "disabled"; 1630 }; 1631 1632 spdifout_b: audio-controller@680 { 1633 compatible = "amlogic,g12a-spdifout", 1634 "amlogic,axg-spdifout"; 1635 reg = <0x0 0x680 0x0 0x50>; 1636 #sound-dai-cells = <0>; 1637 sound-name-prefix = "SPDIFOUT_B"; 1638 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1639 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1640 clock-names = "pclk", "mclk"; 1641 status = "disabled"; 1642 }; 1643 1644 tohdmitx: audio-controller@744 { 1645 compatible = "amlogic,g12a-tohdmitx"; 1646 reg = <0x0 0x744 0x0 0x4>; 1647 #sound-dai-cells = <1>; 1648 sound-name-prefix = "TOHDMITX"; 1649 status = "disabled"; 1650 }; 1651 }; 1652 1653 usb3_pcie_phy: phy@46000 { 1654 compatible = "amlogic,g12a-usb3-pcie-phy"; 1655 reg = <0x0 0x46000 0x0 0x2000>; 1656 clocks = <&clkc CLKID_PCIE_PLL>; 1657 clock-names = "ref_clk"; 1658 resets = <&reset RESET_PCIE_PHY>; 1659 reset-names = "phy"; 1660 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1661 assigned-clock-rates = <100000000>; 1662 #phy-cells = <1>; 1663 }; 1664 }; 1665 1666 aobus: bus@ff800000 { 1667 compatible = "simple-bus"; 1668 reg = <0x0 0xff800000 0x0 0x100000>; 1669 #address-cells = <2>; 1670 #size-cells = <2>; 1671 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1672 1673 rti: sys-ctrl@0 { 1674 compatible = "amlogic,meson-gx-ao-sysctrl", 1675 "simple-mfd", "syscon"; 1676 reg = <0x0 0x0 0x0 0x100>; 1677 #address-cells = <2>; 1678 #size-cells = <2>; 1679 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1680 1681 clkc_AO: clock-controller { 1682 compatible = "amlogic,meson-g12a-aoclkc"; 1683 #clock-cells = <1>; 1684 #reset-cells = <1>; 1685 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1686 clock-names = "xtal", "mpeg-clk"; 1687 }; 1688 1689 pwrc_vpu: power-controller-vpu { 1690 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1691 #power-domain-cells = <0>; 1692 amlogic,hhi-sysctrl = <&hhi>; 1693 resets = <&reset RESET_VIU>, 1694 <&reset RESET_VENC>, 1695 <&reset RESET_VCBUS>, 1696 <&reset RESET_BT656>, 1697 <&reset RESET_RDMA>, 1698 <&reset RESET_VENCI>, 1699 <&reset RESET_VENCP>, 1700 <&reset RESET_VDAC>, 1701 <&reset RESET_VDI6>, 1702 <&reset RESET_VENCL>, 1703 <&reset RESET_VID_LOCK>; 1704 clocks = <&clkc CLKID_VPU>, 1705 <&clkc CLKID_VAPB>; 1706 clock-names = "vpu", "vapb"; 1707 /* 1708 * VPU clocking is provided by two identical clock paths 1709 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1710 * free mux to safely change frequency while running. 1711 * Same for VAPB but with a final gate after the glitch free mux. 1712 */ 1713 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1714 <&clkc CLKID_VPU_0>, 1715 <&clkc CLKID_VPU>, /* Glitch free mux */ 1716 <&clkc CLKID_VAPB_0_SEL>, 1717 <&clkc CLKID_VAPB_0>, 1718 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1719 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1720 <0>, /* Do Nothing */ 1721 <&clkc CLKID_VPU_0>, 1722 <&clkc CLKID_FCLK_DIV4>, 1723 <0>, /* Do Nothing */ 1724 <&clkc CLKID_VAPB_0>; 1725 assigned-clock-rates = <0>, /* Do Nothing */ 1726 <666666666>, 1727 <0>, /* Do Nothing */ 1728 <0>, /* Do Nothing */ 1729 <250000000>, 1730 <0>; /* Do Nothing */ 1731 }; 1732 1733 ao_pinctrl: pinctrl@14 { 1734 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1735 #address-cells = <2>; 1736 #size-cells = <2>; 1737 ranges; 1738 1739 gpio_ao: bank@14 { 1740 reg = <0x0 0x14 0x0 0x8>, 1741 <0x0 0x1c 0x0 0x8>, 1742 <0x0 0x24 0x0 0x14>; 1743 reg-names = "mux", 1744 "ds", 1745 "gpio"; 1746 gpio-controller; 1747 #gpio-cells = <2>; 1748 gpio-ranges = <&ao_pinctrl 0 0 15>; 1749 }; 1750 1751 i2c_ao_sck_pins: i2c_ao_sck_pins { 1752 mux { 1753 groups = "i2c_ao_sck"; 1754 function = "i2c_ao"; 1755 bias-disable; 1756 drive-strength-microamp = <3000>; 1757 }; 1758 }; 1759 1760 i2c_ao_sda_pins: i2c_ao_sda { 1761 mux { 1762 groups = "i2c_ao_sda"; 1763 function = "i2c_ao"; 1764 bias-disable; 1765 drive-strength-microamp = <3000>; 1766 }; 1767 }; 1768 1769 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1770 mux { 1771 groups = "i2c_ao_sck_e"; 1772 function = "i2c_ao"; 1773 bias-disable; 1774 drive-strength-microamp = <3000>; 1775 }; 1776 }; 1777 1778 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1779 mux { 1780 groups = "i2c_ao_sda_e"; 1781 function = "i2c_ao"; 1782 bias-disable; 1783 drive-strength-microamp = <3000>; 1784 }; 1785 }; 1786 1787 mclk0_ao_pins: mclk0-ao { 1788 mux { 1789 groups = "mclk0_ao"; 1790 function = "mclk0_ao"; 1791 bias-disable; 1792 drive-strength-microamp = <3000>; 1793 }; 1794 }; 1795 1796 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1797 mux { 1798 groups = "tdm_ao_b_din0"; 1799 function = "tdm_ao_b"; 1800 bias-disable; 1801 }; 1802 }; 1803 1804 spdif_ao_out_pins: spdif-ao-out { 1805 mux { 1806 groups = "spdif_ao_out"; 1807 function = "spdif_ao_out"; 1808 drive-strength-microamp = <500>; 1809 bias-disable; 1810 }; 1811 }; 1812 1813 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1814 mux { 1815 groups = "tdm_ao_b_din1"; 1816 function = "tdm_ao_b"; 1817 bias-disable; 1818 }; 1819 }; 1820 1821 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1822 mux { 1823 groups = "tdm_ao_b_din2"; 1824 function = "tdm_ao_b"; 1825 bias-disable; 1826 }; 1827 }; 1828 1829 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1830 mux { 1831 groups = "tdm_ao_b_dout0"; 1832 function = "tdm_ao_b"; 1833 bias-disable; 1834 drive-strength-microamp = <3000>; 1835 }; 1836 }; 1837 1838 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1839 mux { 1840 groups = "tdm_ao_b_dout1"; 1841 function = "tdm_ao_b"; 1842 bias-disable; 1843 drive-strength-microamp = <3000>; 1844 }; 1845 }; 1846 1847 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1848 mux { 1849 groups = "tdm_ao_b_dout2"; 1850 function = "tdm_ao_b"; 1851 bias-disable; 1852 drive-strength-microamp = <3000>; 1853 }; 1854 }; 1855 1856 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1857 mux { 1858 groups = "tdm_ao_b_fs"; 1859 function = "tdm_ao_b"; 1860 bias-disable; 1861 drive-strength-microamp = <3000>; 1862 }; 1863 }; 1864 1865 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1866 mux { 1867 groups = "tdm_ao_b_sclk"; 1868 function = "tdm_ao_b"; 1869 bias-disable; 1870 drive-strength-microamp = <3000>; 1871 }; 1872 }; 1873 1874 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1875 mux { 1876 groups = "tdm_ao_b_slv_fs"; 1877 function = "tdm_ao_b"; 1878 bias-disable; 1879 }; 1880 }; 1881 1882 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1883 mux { 1884 groups = "tdm_ao_b_slv_sclk"; 1885 function = "tdm_ao_b"; 1886 bias-disable; 1887 }; 1888 }; 1889 1890 uart_ao_a_pins: uart-a-ao { 1891 mux { 1892 groups = "uart_ao_a_tx", 1893 "uart_ao_a_rx"; 1894 function = "uart_ao_a"; 1895 bias-disable; 1896 }; 1897 }; 1898 1899 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1900 mux { 1901 groups = "uart_ao_a_cts", 1902 "uart_ao_a_rts"; 1903 function = "uart_ao_a"; 1904 bias-disable; 1905 }; 1906 }; 1907 1908 pwm_ao_a_pins: pwm-ao-a { 1909 mux { 1910 groups = "pwm_ao_a"; 1911 function = "pwm_ao_a"; 1912 bias-disable; 1913 }; 1914 }; 1915 1916 pwm_ao_b_pins: pwm-ao-b { 1917 mux { 1918 groups = "pwm_ao_b"; 1919 function = "pwm_ao_b"; 1920 bias-disable; 1921 }; 1922 }; 1923 1924 pwm_ao_c_4_pins: pwm-ao-c-4 { 1925 mux { 1926 groups = "pwm_ao_c_4"; 1927 function = "pwm_ao_c"; 1928 bias-disable; 1929 }; 1930 }; 1931 1932 pwm_ao_c_6_pins: pwm-ao-c-6 { 1933 mux { 1934 groups = "pwm_ao_c_6"; 1935 function = "pwm_ao_c"; 1936 bias-disable; 1937 }; 1938 }; 1939 1940 pwm_ao_d_5_pins: pwm-ao-d-5 { 1941 mux { 1942 groups = "pwm_ao_d_5"; 1943 function = "pwm_ao_d"; 1944 bias-disable; 1945 }; 1946 }; 1947 1948 pwm_ao_d_10_pins: pwm-ao-d-10 { 1949 mux { 1950 groups = "pwm_ao_d_10"; 1951 function = "pwm_ao_d"; 1952 bias-disable; 1953 }; 1954 }; 1955 1956 pwm_ao_d_e_pins: pwm-ao-d-e { 1957 mux { 1958 groups = "pwm_ao_d_e"; 1959 function = "pwm_ao_d"; 1960 }; 1961 }; 1962 1963 remote_input_ao_pins: remote-input-ao { 1964 mux { 1965 groups = "remote_ao_input"; 1966 function = "remote_ao_input"; 1967 bias-disable; 1968 }; 1969 }; 1970 }; 1971 }; 1972 1973 cec_AO: cec@100 { 1974 compatible = "amlogic,meson-gx-ao-cec"; 1975 reg = <0x0 0x00100 0x0 0x14>; 1976 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1977 clocks = <&clkc_AO CLKID_AO_CEC>; 1978 clock-names = "core"; 1979 status = "disabled"; 1980 }; 1981 1982 sec_AO: ao-secure@140 { 1983 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1984 reg = <0x0 0x140 0x0 0x140>; 1985 amlogic,has-chip-id; 1986 }; 1987 1988 cecb_AO: cec@280 { 1989 compatible = "amlogic,meson-g12a-ao-cec"; 1990 reg = <0x0 0x00280 0x0 0x1c>; 1991 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1992 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1993 clock-names = "oscin"; 1994 status = "disabled"; 1995 }; 1996 1997 pwm_AO_cd: pwm@2000 { 1998 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1999 reg = <0x0 0x2000 0x0 0x20>; 2000 #pwm-cells = <3>; 2001 status = "disabled"; 2002 }; 2003 2004 uart_AO: serial@3000 { 2005 compatible = "amlogic,meson-gx-uart", 2006 "amlogic,meson-ao-uart"; 2007 reg = <0x0 0x3000 0x0 0x18>; 2008 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2009 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2010 clock-names = "xtal", "pclk", "baud"; 2011 status = "disabled"; 2012 }; 2013 2014 uart_AO_B: serial@4000 { 2015 compatible = "amlogic,meson-gx-uart", 2016 "amlogic,meson-ao-uart"; 2017 reg = <0x0 0x4000 0x0 0x18>; 2018 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2019 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2020 clock-names = "xtal", "pclk", "baud"; 2021 status = "disabled"; 2022 }; 2023 2024 i2c_AO: i2c@5000 { 2025 compatible = "amlogic,meson-axg-i2c"; 2026 status = "disabled"; 2027 reg = <0x0 0x05000 0x0 0x20>; 2028 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 clocks = <&clkc CLKID_I2C>; 2032 }; 2033 2034 pwm_AO_ab: pwm@7000 { 2035 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2036 reg = <0x0 0x7000 0x0 0x20>; 2037 #pwm-cells = <3>; 2038 status = "disabled"; 2039 }; 2040 2041 ir: ir@8000 { 2042 compatible = "amlogic,meson-gxbb-ir"; 2043 reg = <0x0 0x8000 0x0 0x20>; 2044 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2045 status = "disabled"; 2046 }; 2047 2048 saradc: adc@9000 { 2049 compatible = "amlogic,meson-g12a-saradc", 2050 "amlogic,meson-saradc"; 2051 reg = <0x0 0x9000 0x0 0x48>; 2052 #io-channel-cells = <1>; 2053 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2054 clocks = <&xtal>, 2055 <&clkc_AO CLKID_AO_SAR_ADC>, 2056 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2057 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2058 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2059 status = "disabled"; 2060 }; 2061 }; 2062 2063 vpu: vpu@ff900000 { 2064 compatible = "amlogic,meson-g12a-vpu"; 2065 reg = <0x0 0xff900000 0x0 0x100000>, 2066 <0x0 0xff63c000 0x0 0x1000>; 2067 reg-names = "vpu", "hhi"; 2068 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2069 #address-cells = <1>; 2070 #size-cells = <0>; 2071 amlogic,canvas = <&canvas>; 2072 power-domains = <&pwrc_vpu>; 2073 2074 /* CVBS VDAC output port */ 2075 cvbs_vdac_port: port@0 { 2076 reg = <0>; 2077 }; 2078 2079 /* HDMI-TX output port */ 2080 hdmi_tx_port: port@1 { 2081 reg = <1>; 2082 2083 hdmi_tx_out: endpoint { 2084 remote-endpoint = <&hdmi_tx_in>; 2085 }; 2086 }; 2087 }; 2088 2089 gic: interrupt-controller@ffc01000 { 2090 compatible = "arm,gic-400"; 2091 reg = <0x0 0xffc01000 0 0x1000>, 2092 <0x0 0xffc02000 0 0x2000>, 2093 <0x0 0xffc04000 0 0x2000>, 2094 <0x0 0xffc06000 0 0x2000>; 2095 interrupt-controller; 2096 interrupts = <GIC_PPI 9 2097 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2098 #interrupt-cells = <3>; 2099 #address-cells = <0>; 2100 }; 2101 2102 cbus: bus@ffd00000 { 2103 compatible = "simple-bus"; 2104 reg = <0x0 0xffd00000 0x0 0x100000>; 2105 #address-cells = <2>; 2106 #size-cells = <2>; 2107 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2108 2109 reset: reset-controller@1004 { 2110 compatible = "amlogic,meson-g12a-reset", 2111 "amlogic,meson-axg-reset"; 2112 reg = <0x0 0x1004 0x0 0x9c>; 2113 #reset-cells = <1>; 2114 }; 2115 2116 pwm_ef: pwm@19000 { 2117 compatible = "amlogic,meson-g12a-ee-pwm"; 2118 reg = <0x0 0x19000 0x0 0x20>; 2119 #pwm-cells = <3>; 2120 status = "disabled"; 2121 }; 2122 2123 pwm_cd: pwm@1a000 { 2124 compatible = "amlogic,meson-g12a-ee-pwm"; 2125 reg = <0x0 0x1a000 0x0 0x20>; 2126 #pwm-cells = <3>; 2127 status = "disabled"; 2128 }; 2129 2130 pwm_ab: pwm@1b000 { 2131 compatible = "amlogic,meson-g12a-ee-pwm"; 2132 reg = <0x0 0x1b000 0x0 0x20>; 2133 #pwm-cells = <3>; 2134 status = "disabled"; 2135 }; 2136 2137 i2c3: i2c@1c000 { 2138 compatible = "amlogic,meson-axg-i2c"; 2139 status = "disabled"; 2140 reg = <0x0 0x1c000 0x0 0x20>; 2141 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2142 #address-cells = <1>; 2143 #size-cells = <0>; 2144 clocks = <&clkc CLKID_I2C>; 2145 }; 2146 2147 i2c2: i2c@1d000 { 2148 compatible = "amlogic,meson-axg-i2c"; 2149 status = "disabled"; 2150 reg = <0x0 0x1d000 0x0 0x20>; 2151 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 clocks = <&clkc CLKID_I2C>; 2155 }; 2156 2157 i2c1: i2c@1e000 { 2158 compatible = "amlogic,meson-axg-i2c"; 2159 status = "disabled"; 2160 reg = <0x0 0x1e000 0x0 0x20>; 2161 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2162 #address-cells = <1>; 2163 #size-cells = <0>; 2164 clocks = <&clkc CLKID_I2C>; 2165 }; 2166 2167 i2c0: i2c@1f000 { 2168 compatible = "amlogic,meson-axg-i2c"; 2169 status = "disabled"; 2170 reg = <0x0 0x1f000 0x0 0x20>; 2171 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 clocks = <&clkc CLKID_I2C>; 2175 }; 2176 2177 clk_msr: clock-measure@18000 { 2178 compatible = "amlogic,meson-g12a-clk-measure"; 2179 reg = <0x0 0x18000 0x0 0x10>; 2180 }; 2181 2182 uart_C: serial@22000 { 2183 compatible = "amlogic,meson-gx-uart"; 2184 reg = <0x0 0x22000 0x0 0x18>; 2185 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2186 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2187 clock-names = "xtal", "pclk", "baud"; 2188 status = "disabled"; 2189 }; 2190 2191 uart_B: serial@23000 { 2192 compatible = "amlogic,meson-gx-uart"; 2193 reg = <0x0 0x23000 0x0 0x18>; 2194 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2195 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2196 clock-names = "xtal", "pclk", "baud"; 2197 status = "disabled"; 2198 }; 2199 2200 uart_A: serial@24000 { 2201 compatible = "amlogic,meson-gx-uart"; 2202 reg = <0x0 0x24000 0x0 0x18>; 2203 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2204 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2205 clock-names = "xtal", "pclk", "baud"; 2206 status = "disabled"; 2207 }; 2208 }; 2209 2210 sd_emmc_b: sd@ffe05000 { 2211 compatible = "amlogic,meson-axg-mmc"; 2212 reg = <0x0 0xffe05000 0x0 0x800>; 2213 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2214 status = "disabled"; 2215 clocks = <&clkc CLKID_SD_EMMC_B>, 2216 <&clkc CLKID_SD_EMMC_B_CLK0>, 2217 <&clkc CLKID_FCLK_DIV2>; 2218 clock-names = "core", "clkin0", "clkin1"; 2219 resets = <&reset RESET_SD_EMMC_B>; 2220 }; 2221 2222 sd_emmc_c: mmc@ffe07000 { 2223 compatible = "amlogic,meson-axg-mmc"; 2224 reg = <0x0 0xffe07000 0x0 0x800>; 2225 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2226 status = "disabled"; 2227 clocks = <&clkc CLKID_SD_EMMC_C>, 2228 <&clkc CLKID_SD_EMMC_C_CLK0>, 2229 <&clkc CLKID_FCLK_DIV2>; 2230 clock-names = "core", "clkin0", "clkin1"; 2231 resets = <&reset RESET_SD_EMMC_C>; 2232 }; 2233 2234 usb: usb@ffe09000 { 2235 status = "disabled"; 2236 compatible = "amlogic,meson-g12a-usb-ctrl"; 2237 reg = <0x0 0xffe09000 0x0 0xa0>; 2238 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2239 #address-cells = <2>; 2240 #size-cells = <2>; 2241 ranges; 2242 2243 clocks = <&clkc CLKID_USB>; 2244 resets = <&reset RESET_USB>; 2245 2246 dr_mode = "otg"; 2247 2248 phys = <&usb2_phy0>, <&usb2_phy1>, 2249 <&usb3_pcie_phy PHY_TYPE_USB3>; 2250 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2251 2252 dwc2: usb@ff400000 { 2253 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2254 reg = <0x0 0xff400000 0x0 0x40000>; 2255 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2256 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2257 clock-names = "ddr"; 2258 phys = <&usb2_phy1>; 2259 dr_mode = "peripheral"; 2260 g-rx-fifo-size = <192>; 2261 g-np-tx-fifo-size = <128>; 2262 g-tx-fifo-size = <128 128 16 16 16>; 2263 }; 2264 2265 dwc3: usb@ff500000 { 2266 compatible = "snps,dwc3"; 2267 reg = <0x0 0xff500000 0x0 0x100000>; 2268 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2269 dr_mode = "host"; 2270 snps,dis_u2_susphy_quirk; 2271 snps,quirk-frame-length-adjustment; 2272 }; 2273 }; 2274 2275 mali: gpu@ffe40000 { 2276 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2277 reg = <0x0 0xffe40000 0x0 0x40000>; 2278 interrupt-parent = <&gic>; 2279 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2282 interrupt-names = "gpu", "mmu", "job"; 2283 clocks = <&clkc CLKID_MALI>; 2284 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2285 2286 /* 2287 * Mali clocking is provided by two identical clock paths 2288 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2289 * free mux to safely change frequency while running. 2290 */ 2291 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2292 <&clkc CLKID_MALI_0>, 2293 <&clkc CLKID_MALI>; /* Glitch free mux */ 2294 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2295 <0>, /* Do Nothing */ 2296 <&clkc CLKID_MALI_0>; 2297 assigned-clock-rates = <0>, /* Do Nothing */ 2298 <800000000>, 2299 <0>; /* Do Nothing */ 2300 }; 2301 }; 2302 2303 timer { 2304 compatible = "arm,armv8-timer"; 2305 interrupts = <GIC_PPI 13 2306 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2307 <GIC_PPI 14 2308 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2309 <GIC_PPI 11 2310 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2311 <GIC_PPI 10 2312 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2313 }; 2314 2315 xtal: xtal-clk { 2316 compatible = "fixed-clock"; 2317 clock-frequency = <24000000>; 2318 clock-output-names = "xtal"; 2319 #clock-cells = <0>; 2320 }; 2321 2322}; 2323