1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 apb: bus@ff600000 { 141 compatible = "simple-bus"; 142 reg = <0x0 0xff600000 0x0 0x200000>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 146 147 hdmi_tx: hdmi-tx@0 { 148 compatible = "amlogic,meson-g12a-dw-hdmi"; 149 reg = <0x0 0x0 0x0 0x10000>; 150 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 151 resets = <&reset RESET_HDMITX_CAPB3>, 152 <&reset RESET_HDMITX_PHY>, 153 <&reset RESET_HDMITX>; 154 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 155 clocks = <&clkc CLKID_HDMI>, 156 <&clkc CLKID_HTX_PCLK>, 157 <&clkc CLKID_VPU_INTR>; 158 clock-names = "isfr", "iahb", "venci"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 #sound-dai-cells = <0>; 162 status = "disabled"; 163 164 /* VPU VENC Input */ 165 hdmi_tx_venc_port: port@0 { 166 reg = <0>; 167 168 hdmi_tx_in: endpoint { 169 remote-endpoint = <&hdmi_tx_out>; 170 }; 171 }; 172 173 /* TMDS Output */ 174 hdmi_tx_tmds_port: port@1 { 175 reg = <1>; 176 }; 177 }; 178 179 periphs: bus@34400 { 180 compatible = "simple-bus"; 181 reg = <0x0 0x34400 0x0 0x400>; 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 185 186 periphs_pinctrl: pinctrl@40 { 187 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 gpio: bank@40 { 193 reg = <0x0 0x40 0x0 0x4c>, 194 <0x0 0xe8 0x0 0x18>, 195 <0x0 0x120 0x0 0x18>, 196 <0x0 0x2c0 0x0 0x40>, 197 <0x0 0x340 0x0 0x1c>; 198 reg-names = "gpio", 199 "pull", 200 "pull-enable", 201 "mux", 202 "ds"; 203 gpio-controller; 204 #gpio-cells = <2>; 205 gpio-ranges = <&periphs_pinctrl 0 0 86>; 206 }; 207 208 cec_ao_a_h_pins: cec_ao_a_h { 209 mux { 210 groups = "cec_ao_a_h"; 211 function = "cec_ao_a_h"; 212 bias-disable; 213 }; 214 }; 215 216 cec_ao_b_h_pins: cec_ao_b_h { 217 mux { 218 groups = "cec_ao_b_h"; 219 function = "cec_ao_b_h"; 220 bias-disable; 221 }; 222 }; 223 224 emmc_pins: emmc { 225 mux-0 { 226 groups = "emmc_nand_d0", 227 "emmc_nand_d1", 228 "emmc_nand_d2", 229 "emmc_nand_d3", 230 "emmc_nand_d4", 231 "emmc_nand_d5", 232 "emmc_nand_d6", 233 "emmc_nand_d7", 234 "emmc_cmd"; 235 function = "emmc"; 236 bias-pull-up; 237 drive-strength-microamp = <4000>; 238 }; 239 240 mux-1 { 241 groups = "emmc_clk"; 242 function = "emmc"; 243 bias-disable; 244 drive-strength-microamp = <4000>; 245 }; 246 }; 247 248 emmc_ds_pins: emmc-ds { 249 mux { 250 groups = "emmc_nand_ds"; 251 function = "emmc"; 252 bias-pull-down; 253 drive-strength-microamp = <4000>; 254 }; 255 }; 256 257 emmc_clk_gate_pins: emmc_clk_gate { 258 mux { 259 groups = "BOOT_8"; 260 function = "gpio_periphs"; 261 bias-pull-down; 262 drive-strength-microamp = <4000>; 263 }; 264 }; 265 266 hdmitx_ddc_pins: hdmitx_ddc { 267 mux { 268 groups = "hdmitx_sda", 269 "hdmitx_sck"; 270 function = "hdmitx"; 271 bias-disable; 272 }; 273 }; 274 275 hdmitx_hpd_pins: hdmitx_hpd { 276 mux { 277 groups = "hdmitx_hpd_in"; 278 function = "hdmitx"; 279 bias-disable; 280 }; 281 }; 282 283 284 i2c0_sda_c_pins: i2c0-sda-c { 285 mux { 286 groups = "i2c0_sda_c"; 287 function = "i2c0"; 288 bias-disable; 289 drive-strength-microamp = <3000>; 290 291 }; 292 }; 293 294 i2c0_sck_c_pins: i2c0-sck-c { 295 mux { 296 groups = "i2c0_sck_c"; 297 function = "i2c0"; 298 bias-disable; 299 drive-strength-microamp = <3000>; 300 }; 301 }; 302 303 i2c0_sda_z0_pins: i2c0-sda-z0 { 304 mux { 305 groups = "i2c0_sda_z0"; 306 function = "i2c0"; 307 bias-disable; 308 drive-strength-microamp = <3000>; 309 }; 310 }; 311 312 i2c0_sck_z1_pins: i2c0-sck-z1 { 313 mux { 314 groups = "i2c0_sck_z1"; 315 function = "i2c0"; 316 bias-disable; 317 drive-strength-microamp = <3000>; 318 }; 319 }; 320 321 i2c0_sda_z7_pins: i2c0-sda-z7 { 322 mux { 323 groups = "i2c0_sda_z7"; 324 function = "i2c0"; 325 bias-disable; 326 drive-strength-microamp = <3000>; 327 }; 328 }; 329 330 i2c0_sda_z8_pins: i2c0-sda-z8 { 331 mux { 332 groups = "i2c0_sda_z8"; 333 function = "i2c0"; 334 bias-disable; 335 drive-strength-microamp = <3000>; 336 }; 337 }; 338 339 i2c1_sda_x_pins: i2c1-sda-x { 340 mux { 341 groups = "i2c1_sda_x"; 342 function = "i2c1"; 343 bias-disable; 344 drive-strength-microamp = <3000>; 345 }; 346 }; 347 348 i2c1_sck_x_pins: i2c1-sck-x { 349 mux { 350 groups = "i2c1_sck_x"; 351 function = "i2c1"; 352 bias-disable; 353 drive-strength-microamp = <3000>; 354 }; 355 }; 356 357 i2c1_sda_h2_pins: i2c1-sda-h2 { 358 mux { 359 groups = "i2c1_sda_h2"; 360 function = "i2c1"; 361 bias-disable; 362 drive-strength-microamp = <3000>; 363 }; 364 }; 365 366 i2c1_sck_h3_pins: i2c1-sck-h3 { 367 mux { 368 groups = "i2c1_sck_h3"; 369 function = "i2c1"; 370 bias-disable; 371 drive-strength-microamp = <3000>; 372 }; 373 }; 374 375 i2c1_sda_h6_pins: i2c1-sda-h6 { 376 mux { 377 groups = "i2c1_sda_h6"; 378 function = "i2c1"; 379 bias-disable; 380 drive-strength-microamp = <3000>; 381 }; 382 }; 383 384 i2c1_sck_h7_pins: i2c1-sck-h7 { 385 mux { 386 groups = "i2c1_sck_h7"; 387 function = "i2c1"; 388 bias-disable; 389 drive-strength-microamp = <3000>; 390 }; 391 }; 392 393 i2c2_sda_x_pins: i2c2-sda-x { 394 mux { 395 groups = "i2c2_sda_x"; 396 function = "i2c2"; 397 bias-disable; 398 drive-strength-microamp = <3000>; 399 }; 400 }; 401 402 i2c2_sck_x_pins: i2c2-sck-x { 403 mux { 404 groups = "i2c2_sck_x"; 405 function = "i2c2"; 406 bias-disable; 407 drive-strength-microamp = <3000>; 408 }; 409 }; 410 411 i2c2_sda_z_pins: i2c2-sda-z { 412 mux { 413 groups = "i2c2_sda_z"; 414 function = "i2c2"; 415 bias-disable; 416 drive-strength-microamp = <3000>; 417 }; 418 }; 419 420 i2c2_sck_z_pins: i2c2-sck-z { 421 mux { 422 groups = "i2c2_sck_z"; 423 function = "i2c2"; 424 bias-disable; 425 drive-strength-microamp = <3000>; 426 }; 427 }; 428 429 i2c3_sda_h_pins: i2c3-sda-h { 430 mux { 431 groups = "i2c3_sda_h"; 432 function = "i2c3"; 433 bias-disable; 434 drive-strength-microamp = <3000>; 435 }; 436 }; 437 438 i2c3_sck_h_pins: i2c3-sck-h { 439 mux { 440 groups = "i2c3_sck_h"; 441 function = "i2c3"; 442 bias-disable; 443 drive-strength-microamp = <3000>; 444 }; 445 }; 446 447 i2c3_sda_a_pins: i2c3-sda-a { 448 mux { 449 groups = "i2c3_sda_a"; 450 function = "i2c3"; 451 bias-disable; 452 drive-strength-microamp = <3000>; 453 }; 454 }; 455 456 i2c3_sck_a_pins: i2c3-sck-a { 457 mux { 458 groups = "i2c3_sck_a"; 459 function = "i2c3"; 460 bias-disable; 461 drive-strength-microamp = <3000>; 462 }; 463 }; 464 465 mclk0_a_pins: mclk0-a { 466 mux { 467 groups = "mclk0_a"; 468 function = "mclk0"; 469 bias-disable; 470 drive-strength-microamp = <3000>; 471 }; 472 }; 473 474 mclk1_a_pins: mclk1-a { 475 mux { 476 groups = "mclk1_a"; 477 function = "mclk1"; 478 bias-disable; 479 drive-strength-microamp = <3000>; 480 }; 481 }; 482 483 mclk1_x_pins: mclk1-x { 484 mux { 485 groups = "mclk1_x"; 486 function = "mclk1"; 487 bias-disable; 488 drive-strength-microamp = <3000>; 489 }; 490 }; 491 492 mclk1_z_pins: mclk1-z { 493 mux { 494 groups = "mclk1_z"; 495 function = "mclk1"; 496 bias-disable; 497 drive-strength-microamp = <3000>; 498 }; 499 }; 500 501 pdm_din0_a_pins: pdm-din0-a { 502 mux { 503 groups = "pdm_din0_a"; 504 function = "pdm"; 505 bias-disable; 506 }; 507 }; 508 509 pdm_din0_c_pins: pdm-din0-c { 510 mux { 511 groups = "pdm_din0_c"; 512 function = "pdm"; 513 bias-disable; 514 }; 515 }; 516 517 pdm_din0_x_pins: pdm-din0-x { 518 mux { 519 groups = "pdm_din0_x"; 520 function = "pdm"; 521 bias-disable; 522 }; 523 }; 524 525 pdm_din0_z_pins: pdm-din0-z { 526 mux { 527 groups = "pdm_din0_z"; 528 function = "pdm"; 529 bias-disable; 530 }; 531 }; 532 533 pdm_din1_a_pins: pdm-din1-a { 534 mux { 535 groups = "pdm_din1_a"; 536 function = "pdm"; 537 bias-disable; 538 }; 539 }; 540 541 pdm_din1_c_pins: pdm-din1-c { 542 mux { 543 groups = "pdm_din1_c"; 544 function = "pdm"; 545 bias-disable; 546 }; 547 }; 548 549 pdm_din1_x_pins: pdm-din1-x { 550 mux { 551 groups = "pdm_din1_x"; 552 function = "pdm"; 553 bias-disable; 554 }; 555 }; 556 557 pdm_din1_z_pins: pdm-din1-z { 558 mux { 559 groups = "pdm_din1_z"; 560 function = "pdm"; 561 bias-disable; 562 }; 563 }; 564 565 pdm_din2_a_pins: pdm-din2-a { 566 mux { 567 groups = "pdm_din2_a"; 568 function = "pdm"; 569 bias-disable; 570 }; 571 }; 572 573 pdm_din2_c_pins: pdm-din2-c { 574 mux { 575 groups = "pdm_din2_c"; 576 function = "pdm"; 577 bias-disable; 578 }; 579 }; 580 581 pdm_din2_x_pins: pdm-din2-x { 582 mux { 583 groups = "pdm_din2_x"; 584 function = "pdm"; 585 bias-disable; 586 }; 587 }; 588 589 pdm_din2_z_pins: pdm-din2-z { 590 mux { 591 groups = "pdm_din2_z"; 592 function = "pdm"; 593 bias-disable; 594 }; 595 }; 596 597 pdm_din3_a_pins: pdm-din3-a { 598 mux { 599 groups = "pdm_din3_a"; 600 function = "pdm"; 601 bias-disable; 602 }; 603 }; 604 605 pdm_din3_c_pins: pdm-din3-c { 606 mux { 607 groups = "pdm_din3_c"; 608 function = "pdm"; 609 bias-disable; 610 }; 611 }; 612 613 pdm_din3_x_pins: pdm-din3-x { 614 mux { 615 groups = "pdm_din3_x"; 616 function = "pdm"; 617 bias-disable; 618 }; 619 }; 620 621 pdm_din3_z_pins: pdm-din3-z { 622 mux { 623 groups = "pdm_din3_z"; 624 function = "pdm"; 625 bias-disable; 626 }; 627 }; 628 629 pdm_dclk_a_pins: pdm-dclk-a { 630 mux { 631 groups = "pdm_dclk_a"; 632 function = "pdm"; 633 bias-disable; 634 drive-strength-microamp = <500>; 635 }; 636 }; 637 638 pdm_dclk_c_pins: pdm-dclk-c { 639 mux { 640 groups = "pdm_dclk_c"; 641 function = "pdm"; 642 bias-disable; 643 drive-strength-microamp = <500>; 644 }; 645 }; 646 647 pdm_dclk_x_pins: pdm-dclk-x { 648 mux { 649 groups = "pdm_dclk_x"; 650 function = "pdm"; 651 bias-disable; 652 drive-strength-microamp = <500>; 653 }; 654 }; 655 656 pdm_dclk_z_pins: pdm-dclk-z { 657 mux { 658 groups = "pdm_dclk_z"; 659 function = "pdm"; 660 bias-disable; 661 drive-strength-microamp = <500>; 662 }; 663 }; 664 665 pwm_a_pins: pwm-a { 666 mux { 667 groups = "pwm_a"; 668 function = "pwm_a"; 669 bias-disable; 670 }; 671 }; 672 673 pwm_b_x7_pins: pwm-b-x7 { 674 mux { 675 groups = "pwm_b_x7"; 676 function = "pwm_b"; 677 bias-disable; 678 }; 679 }; 680 681 pwm_b_x19_pins: pwm-b-x19 { 682 mux { 683 groups = "pwm_b_x19"; 684 function = "pwm_b"; 685 bias-disable; 686 }; 687 }; 688 689 pwm_c_c_pins: pwm-c-c { 690 mux { 691 groups = "pwm_c_c"; 692 function = "pwm_c"; 693 bias-disable; 694 }; 695 }; 696 697 pwm_c_x5_pins: pwm-c-x5 { 698 mux { 699 groups = "pwm_c_x5"; 700 function = "pwm_c"; 701 bias-disable; 702 }; 703 }; 704 705 pwm_c_x8_pins: pwm-c-x8 { 706 mux { 707 groups = "pwm_c_x8"; 708 function = "pwm_c"; 709 bias-disable; 710 }; 711 }; 712 713 pwm_d_x3_pins: pwm-d-x3 { 714 mux { 715 groups = "pwm_d_x3"; 716 function = "pwm_d"; 717 bias-disable; 718 }; 719 }; 720 721 pwm_d_x6_pins: pwm-d-x6 { 722 mux { 723 groups = "pwm_d_x6"; 724 function = "pwm_d"; 725 bias-disable; 726 }; 727 }; 728 729 pwm_e_pins: pwm-e { 730 mux { 731 groups = "pwm_e"; 732 function = "pwm_e"; 733 bias-disable; 734 }; 735 }; 736 737 pwm_f_x_pins: pwm-f-x { 738 mux { 739 groups = "pwm_f_x"; 740 function = "pwm_f"; 741 bias-disable; 742 }; 743 }; 744 745 pwm_f_h_pins: pwm-f-h { 746 mux { 747 groups = "pwm_f_h"; 748 function = "pwm_f"; 749 bias-disable; 750 }; 751 }; 752 753 sdcard_c_pins: sdcard_c { 754 mux-0 { 755 groups = "sdcard_d0_c", 756 "sdcard_d1_c", 757 "sdcard_d2_c", 758 "sdcard_d3_c", 759 "sdcard_cmd_c"; 760 function = "sdcard"; 761 bias-pull-up; 762 drive-strength-microamp = <4000>; 763 }; 764 765 mux-1 { 766 groups = "sdcard_clk_c"; 767 function = "sdcard"; 768 bias-disable; 769 drive-strength-microamp = <4000>; 770 }; 771 }; 772 773 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 774 mux { 775 groups = "GPIOC_4"; 776 function = "gpio_periphs"; 777 bias-pull-down; 778 drive-strength-microamp = <4000>; 779 }; 780 }; 781 782 sdcard_z_pins: sdcard_z { 783 mux-0 { 784 groups = "sdcard_d0_z", 785 "sdcard_d1_z", 786 "sdcard_d2_z", 787 "sdcard_d3_z", 788 "sdcard_cmd_z"; 789 function = "sdcard"; 790 bias-pull-up; 791 drive-strength-microamp = <4000>; 792 }; 793 794 mux-1 { 795 groups = "sdcard_clk_z"; 796 function = "sdcard"; 797 bias-disable; 798 drive-strength-microamp = <4000>; 799 }; 800 }; 801 802 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 803 mux { 804 groups = "GPIOZ_6"; 805 function = "gpio_periphs"; 806 bias-pull-down; 807 drive-strength-microamp = <4000>; 808 }; 809 }; 810 811 spdif_in_a10_pins: spdif-in-a10 { 812 mux { 813 groups = "spdif_in_a10"; 814 function = "spdif_in"; 815 bias-disable; 816 }; 817 }; 818 819 spdif_in_a12_pins: spdif-in-a12 { 820 mux { 821 groups = "spdif_in_a12"; 822 function = "spdif_in"; 823 bias-disable; 824 }; 825 }; 826 827 spdif_in_h_pins: spdif-in-h { 828 mux { 829 groups = "spdif_in_h"; 830 function = "spdif_in"; 831 bias-disable; 832 }; 833 }; 834 835 spdif_out_h_pins: spdif-out-h { 836 mux { 837 groups = "spdif_out_h"; 838 function = "spdif_out"; 839 drive-strength-microamp = <500>; 840 bias-disable; 841 }; 842 }; 843 844 spdif_out_a11_pins: spdif-out-a11 { 845 mux { 846 groups = "spdif_out_a11"; 847 function = "spdif_out"; 848 drive-strength-microamp = <500>; 849 bias-disable; 850 }; 851 }; 852 853 spdif_out_a13_pins: spdif-out-a13 { 854 mux { 855 groups = "spdif_out_a13"; 856 function = "spdif_out"; 857 drive-strength-microamp = <500>; 858 bias-disable; 859 }; 860 }; 861 862 tdm_a_din0_pins: tdm-a-din0 { 863 mux { 864 groups = "tdm_a_din0"; 865 function = "tdm_a"; 866 bias-disable; 867 }; 868 }; 869 870 871 tdm_a_din1_pins: tdm-a-din1 { 872 mux { 873 groups = "tdm_a_din1"; 874 function = "tdm_a"; 875 bias-disable; 876 }; 877 }; 878 879 tdm_a_dout0_pins: tdm-a-dout0 { 880 mux { 881 groups = "tdm_a_dout0"; 882 function = "tdm_a"; 883 bias-disable; 884 drive-strength-microamp = <3000>; 885 }; 886 }; 887 888 tdm_a_dout1_pins: tdm-a-dout1 { 889 mux { 890 groups = "tdm_a_dout1"; 891 function = "tdm_a"; 892 bias-disable; 893 drive-strength-microamp = <3000>; 894 }; 895 }; 896 897 tdm_a_fs_pins: tdm-a-fs { 898 mux { 899 groups = "tdm_a_fs"; 900 function = "tdm_a"; 901 bias-disable; 902 drive-strength-microamp = <3000>; 903 }; 904 }; 905 906 tdm_a_sclk_pins: tdm-a-sclk { 907 mux { 908 groups = "tdm_a_sclk"; 909 function = "tdm_a"; 910 bias-disable; 911 drive-strength-microamp = <3000>; 912 }; 913 }; 914 915 tdm_a_slv_fs_pins: tdm-a-slv-fs { 916 mux { 917 groups = "tdm_a_slv_fs"; 918 function = "tdm_a"; 919 bias-disable; 920 }; 921 }; 922 923 924 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 925 mux { 926 groups = "tdm_a_slv_sclk"; 927 function = "tdm_a"; 928 bias-disable; 929 }; 930 }; 931 932 tdm_b_din0_pins: tdm-b-din0 { 933 mux { 934 groups = "tdm_b_din0"; 935 function = "tdm_b"; 936 bias-disable; 937 }; 938 }; 939 940 tdm_b_din1_pins: tdm-b-din1 { 941 mux { 942 groups = "tdm_b_din1"; 943 function = "tdm_b"; 944 bias-disable; 945 }; 946 }; 947 948 tdm_b_din2_pins: tdm-b-din2 { 949 mux { 950 groups = "tdm_b_din2"; 951 function = "tdm_b"; 952 bias-disable; 953 }; 954 }; 955 956 tdm_b_din3_a_pins: tdm-b-din3-a { 957 mux { 958 groups = "tdm_b_din3_a"; 959 function = "tdm_b"; 960 bias-disable; 961 }; 962 }; 963 964 tdm_b_din3_h_pins: tdm-b-din3-h { 965 mux { 966 groups = "tdm_b_din3_h"; 967 function = "tdm_b"; 968 bias-disable; 969 }; 970 }; 971 972 tdm_b_dout0_pins: tdm-b-dout0 { 973 mux { 974 groups = "tdm_b_dout0"; 975 function = "tdm_b"; 976 bias-disable; 977 drive-strength-microamp = <3000>; 978 }; 979 }; 980 981 tdm_b_dout1_pins: tdm-b-dout1 { 982 mux { 983 groups = "tdm_b_dout1"; 984 function = "tdm_b"; 985 bias-disable; 986 drive-strength-microamp = <3000>; 987 }; 988 }; 989 990 tdm_b_dout2_pins: tdm-b-dout2 { 991 mux { 992 groups = "tdm_b_dout2"; 993 function = "tdm_b"; 994 bias-disable; 995 drive-strength-microamp = <3000>; 996 }; 997 }; 998 999 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1000 mux { 1001 groups = "tdm_b_dout3_a"; 1002 function = "tdm_b"; 1003 bias-disable; 1004 drive-strength-microamp = <3000>; 1005 }; 1006 }; 1007 1008 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1009 mux { 1010 groups = "tdm_b_dout3_h"; 1011 function = "tdm_b"; 1012 bias-disable; 1013 drive-strength-microamp = <3000>; 1014 }; 1015 }; 1016 1017 tdm_b_fs_pins: tdm-b-fs { 1018 mux { 1019 groups = "tdm_b_fs"; 1020 function = "tdm_b"; 1021 bias-disable; 1022 drive-strength-microamp = <3000>; 1023 }; 1024 }; 1025 1026 tdm_b_sclk_pins: tdm-b-sclk { 1027 mux { 1028 groups = "tdm_b_sclk"; 1029 function = "tdm_b"; 1030 bias-disable; 1031 drive-strength-microamp = <3000>; 1032 }; 1033 }; 1034 1035 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1036 mux { 1037 groups = "tdm_b_slv_fs"; 1038 function = "tdm_b"; 1039 bias-disable; 1040 }; 1041 }; 1042 1043 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1044 mux { 1045 groups = "tdm_b_slv_sclk"; 1046 function = "tdm_b"; 1047 bias-disable; 1048 }; 1049 }; 1050 1051 tdm_c_din0_a_pins: tdm-c-din0-a { 1052 mux { 1053 groups = "tdm_c_din0_a"; 1054 function = "tdm_c"; 1055 bias-disable; 1056 }; 1057 }; 1058 1059 tdm_c_din0_z_pins: tdm-c-din0-z { 1060 mux { 1061 groups = "tdm_c_din0_z"; 1062 function = "tdm_c"; 1063 bias-disable; 1064 }; 1065 }; 1066 1067 tdm_c_din1_a_pins: tdm-c-din1-a { 1068 mux { 1069 groups = "tdm_c_din1_a"; 1070 function = "tdm_c"; 1071 bias-disable; 1072 }; 1073 }; 1074 1075 tdm_c_din1_z_pins: tdm-c-din1-z { 1076 mux { 1077 groups = "tdm_c_din1_z"; 1078 function = "tdm_c"; 1079 bias-disable; 1080 }; 1081 }; 1082 1083 tdm_c_din2_a_pins: tdm-c-din2-a { 1084 mux { 1085 groups = "tdm_c_din2_a"; 1086 function = "tdm_c"; 1087 bias-disable; 1088 }; 1089 }; 1090 1091 tdm_c_din2_z_pins: tdm-c-din2-z { 1092 mux { 1093 groups = "tdm_c_din2_z"; 1094 function = "tdm_c"; 1095 bias-disable; 1096 }; 1097 }; 1098 1099 tdm_c_din3_a_pins: tdm-c-din3-a { 1100 mux { 1101 groups = "tdm_c_din3_a"; 1102 function = "tdm_c"; 1103 bias-disable; 1104 }; 1105 }; 1106 1107 tdm_c_din3_z_pins: tdm-c-din3-z { 1108 mux { 1109 groups = "tdm_c_din3_z"; 1110 function = "tdm_c"; 1111 bias-disable; 1112 }; 1113 }; 1114 1115 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1116 mux { 1117 groups = "tdm_c_dout0_a"; 1118 function = "tdm_c"; 1119 bias-disable; 1120 drive-strength-microamp = <3000>; 1121 }; 1122 }; 1123 1124 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1125 mux { 1126 groups = "tdm_c_dout0_z"; 1127 function = "tdm_c"; 1128 bias-disable; 1129 drive-strength-microamp = <3000>; 1130 }; 1131 }; 1132 1133 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1134 mux { 1135 groups = "tdm_c_dout1_a"; 1136 function = "tdm_c"; 1137 bias-disable; 1138 drive-strength-microamp = <3000>; 1139 }; 1140 }; 1141 1142 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1143 mux { 1144 groups = "tdm_c_dout1_z"; 1145 function = "tdm_c"; 1146 bias-disable; 1147 drive-strength-microamp = <3000>; 1148 }; 1149 }; 1150 1151 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1152 mux { 1153 groups = "tdm_c_dout2_a"; 1154 function = "tdm_c"; 1155 bias-disable; 1156 drive-strength-microamp = <3000>; 1157 }; 1158 }; 1159 1160 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1161 mux { 1162 groups = "tdm_c_dout2_z"; 1163 function = "tdm_c"; 1164 bias-disable; 1165 drive-strength-microamp = <3000>; 1166 }; 1167 }; 1168 1169 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1170 mux { 1171 groups = "tdm_c_dout3_a"; 1172 function = "tdm_c"; 1173 bias-disable; 1174 drive-strength-microamp = <3000>; 1175 }; 1176 }; 1177 1178 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1179 mux { 1180 groups = "tdm_c_dout3_z"; 1181 function = "tdm_c"; 1182 bias-disable; 1183 drive-strength-microamp = <3000>; 1184 }; 1185 }; 1186 1187 tdm_c_fs_a_pins: tdm-c-fs-a { 1188 mux { 1189 groups = "tdm_c_fs_a"; 1190 function = "tdm_c"; 1191 bias-disable; 1192 drive-strength-microamp = <3000>; 1193 }; 1194 }; 1195 1196 tdm_c_fs_z_pins: tdm-c-fs-z { 1197 mux { 1198 groups = "tdm_c_fs_z"; 1199 function = "tdm_c"; 1200 bias-disable; 1201 drive-strength-microamp = <3000>; 1202 }; 1203 }; 1204 1205 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1206 mux { 1207 groups = "tdm_c_sclk_a"; 1208 function = "tdm_c"; 1209 bias-disable; 1210 drive-strength-microamp = <3000>; 1211 }; 1212 }; 1213 1214 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1215 mux { 1216 groups = "tdm_c_sclk_z"; 1217 function = "tdm_c"; 1218 bias-disable; 1219 drive-strength-microamp = <3000>; 1220 }; 1221 }; 1222 1223 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1224 mux { 1225 groups = "tdm_c_slv_fs_a"; 1226 function = "tdm_c"; 1227 bias-disable; 1228 }; 1229 }; 1230 1231 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1232 mux { 1233 groups = "tdm_c_slv_fs_z"; 1234 function = "tdm_c"; 1235 bias-disable; 1236 }; 1237 }; 1238 1239 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1240 mux { 1241 groups = "tdm_c_slv_sclk_a"; 1242 function = "tdm_c"; 1243 bias-disable; 1244 }; 1245 }; 1246 1247 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1248 mux { 1249 groups = "tdm_c_slv_sclk_z"; 1250 function = "tdm_c"; 1251 bias-disable; 1252 }; 1253 }; 1254 1255 uart_a_pins: uart-a { 1256 mux { 1257 groups = "uart_a_tx", 1258 "uart_a_rx"; 1259 function = "uart_a"; 1260 bias-disable; 1261 }; 1262 }; 1263 1264 uart_a_cts_rts_pins: uart-a-cts-rts { 1265 mux { 1266 groups = "uart_a_cts", 1267 "uart_a_rts"; 1268 function = "uart_a"; 1269 bias-disable; 1270 }; 1271 }; 1272 1273 uart_b_pins: uart-b { 1274 mux { 1275 groups = "uart_b_tx", 1276 "uart_b_rx"; 1277 function = "uart_b"; 1278 bias-disable; 1279 }; 1280 }; 1281 1282 uart_c_pins: uart-c { 1283 mux { 1284 groups = "uart_c_tx", 1285 "uart_c_rx"; 1286 function = "uart_c"; 1287 bias-disable; 1288 }; 1289 }; 1290 1291 uart_c_cts_rts_pins: uart-c-cts-rts { 1292 mux { 1293 groups = "uart_c_cts", 1294 "uart_c_rts"; 1295 function = "uart_c"; 1296 bias-disable; 1297 }; 1298 }; 1299 }; 1300 }; 1301 1302 usb2_phy0: phy@36000 { 1303 compatible = "amlogic,g12a-usb2-phy"; 1304 reg = <0x0 0x36000 0x0 0x2000>; 1305 clocks = <&xtal>; 1306 clock-names = "xtal"; 1307 resets = <&reset RESET_USB_PHY20>; 1308 reset-names = "phy"; 1309 #phy-cells = <0>; 1310 }; 1311 1312 dmc: bus@38000 { 1313 compatible = "simple-bus"; 1314 reg = <0x0 0x38000 0x0 0x400>; 1315 #address-cells = <2>; 1316 #size-cells = <2>; 1317 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1318 1319 canvas: video-lut@48 { 1320 compatible = "amlogic,canvas"; 1321 reg = <0x0 0x48 0x0 0x14>; 1322 }; 1323 }; 1324 1325 usb2_phy1: phy@3a000 { 1326 compatible = "amlogic,g12a-usb2-phy"; 1327 reg = <0x0 0x3a000 0x0 0x2000>; 1328 clocks = <&xtal>; 1329 clock-names = "xtal"; 1330 resets = <&reset RESET_USB_PHY21>; 1331 reset-names = "phy"; 1332 #phy-cells = <0>; 1333 }; 1334 1335 hiu: bus@3c000 { 1336 compatible = "simple-bus"; 1337 reg = <0x0 0x3c000 0x0 0x1400>; 1338 #address-cells = <2>; 1339 #size-cells = <2>; 1340 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1341 1342 hhi: system-controller@0 { 1343 compatible = "amlogic,meson-gx-hhi-sysctrl", 1344 "simple-mfd", "syscon"; 1345 reg = <0 0 0 0x400>; 1346 1347 clkc: clock-controller { 1348 compatible = "amlogic,g12a-clkc"; 1349 #clock-cells = <1>; 1350 clocks = <&xtal>; 1351 clock-names = "xtal"; 1352 }; 1353 }; 1354 }; 1355 1356 pdm: audio-controller@40000 { 1357 compatible = "amlogic,g12a-pdm", 1358 "amlogic,axg-pdm"; 1359 reg = <0x0 0x40000 0x0 0x34>; 1360 #sound-dai-cells = <0>; 1361 sound-name-prefix = "PDM"; 1362 clocks = <&clkc_audio AUD_CLKID_PDM>, 1363 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1364 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1365 clock-names = "pclk", "dclk", "sysclk"; 1366 status = "disabled"; 1367 }; 1368 1369 audio: bus@42000 { 1370 compatible = "simple-bus"; 1371 reg = <0x0 0x42000 0x0 0x2000>; 1372 #address-cells = <2>; 1373 #size-cells = <2>; 1374 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1375 1376 clkc_audio: clock-controller@0 { 1377 status = "disabled"; 1378 compatible = "amlogic,g12a-audio-clkc"; 1379 reg = <0x0 0x0 0x0 0xb4>; 1380 #clock-cells = <1>; 1381 1382 clocks = <&clkc CLKID_AUDIO>, 1383 <&clkc CLKID_MPLL0>, 1384 <&clkc CLKID_MPLL1>, 1385 <&clkc CLKID_MPLL2>, 1386 <&clkc CLKID_MPLL3>, 1387 <&clkc CLKID_HIFI_PLL>, 1388 <&clkc CLKID_FCLK_DIV3>, 1389 <&clkc CLKID_FCLK_DIV4>, 1390 <&clkc CLKID_GP0_PLL>; 1391 clock-names = "pclk", 1392 "mst_in0", 1393 "mst_in1", 1394 "mst_in2", 1395 "mst_in3", 1396 "mst_in4", 1397 "mst_in5", 1398 "mst_in6", 1399 "mst_in7"; 1400 1401 resets = <&reset RESET_AUDIO>; 1402 }; 1403 1404 toddr_a: audio-controller@100 { 1405 compatible = "amlogic,g12a-toddr", 1406 "amlogic,axg-toddr"; 1407 reg = <0x0 0x100 0x0 0x1c>; 1408 #sound-dai-cells = <0>; 1409 sound-name-prefix = "TODDR_A"; 1410 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1411 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1412 resets = <&arb AXG_ARB_TODDR_A>; 1413 status = "disabled"; 1414 }; 1415 1416 toddr_b: audio-controller@140 { 1417 compatible = "amlogic,g12a-toddr", 1418 "amlogic,axg-toddr"; 1419 reg = <0x0 0x140 0x0 0x1c>; 1420 #sound-dai-cells = <0>; 1421 sound-name-prefix = "TODDR_B"; 1422 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1423 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1424 resets = <&arb AXG_ARB_TODDR_B>; 1425 status = "disabled"; 1426 }; 1427 1428 toddr_c: audio-controller@180 { 1429 compatible = "amlogic,g12a-toddr", 1430 "amlogic,axg-toddr"; 1431 reg = <0x0 0x180 0x0 0x1c>; 1432 #sound-dai-cells = <0>; 1433 sound-name-prefix = "TODDR_C"; 1434 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1435 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1436 resets = <&arb AXG_ARB_TODDR_C>; 1437 status = "disabled"; 1438 }; 1439 1440 frddr_a: audio-controller@1c0 { 1441 compatible = "amlogic,g12a-frddr", 1442 "amlogic,axg-frddr"; 1443 reg = <0x0 0x1c0 0x0 0x1c>; 1444 #sound-dai-cells = <0>; 1445 sound-name-prefix = "FRDDR_A"; 1446 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1447 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1448 resets = <&arb AXG_ARB_FRDDR_A>; 1449 status = "disabled"; 1450 }; 1451 1452 frddr_b: audio-controller@200 { 1453 compatible = "amlogic,g12a-frddr", 1454 "amlogic,axg-frddr"; 1455 reg = <0x0 0x200 0x0 0x1c>; 1456 #sound-dai-cells = <0>; 1457 sound-name-prefix = "FRDDR_B"; 1458 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1459 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1460 resets = <&arb AXG_ARB_FRDDR_B>; 1461 status = "disabled"; 1462 }; 1463 1464 frddr_c: audio-controller@240 { 1465 compatible = "amlogic,g12a-frddr", 1466 "amlogic,axg-frddr"; 1467 reg = <0x0 0x240 0x0 0x1c>; 1468 #sound-dai-cells = <0>; 1469 sound-name-prefix = "FRDDR_C"; 1470 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1471 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1472 resets = <&arb AXG_ARB_FRDDR_C>; 1473 status = "disabled"; 1474 }; 1475 1476 arb: reset-controller@280 { 1477 status = "disabled"; 1478 compatible = "amlogic,meson-axg-audio-arb"; 1479 reg = <0x0 0x280 0x0 0x4>; 1480 #reset-cells = <1>; 1481 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1482 }; 1483 1484 tdmin_a: audio-controller@300 { 1485 compatible = "amlogic,g12a-tdmin", 1486 "amlogic,axg-tdmin"; 1487 reg = <0x0 0x300 0x0 0x40>; 1488 sound-name-prefix = "TDMIN_A"; 1489 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1490 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1491 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1492 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1493 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1494 clock-names = "pclk", "sclk", "sclk_sel", 1495 "lrclk", "lrclk_sel"; 1496 status = "disabled"; 1497 }; 1498 1499 tdmin_b: audio-controller@340 { 1500 compatible = "amlogic,g12a-tdmin", 1501 "amlogic,axg-tdmin"; 1502 reg = <0x0 0x340 0x0 0x40>; 1503 sound-name-prefix = "TDMIN_B"; 1504 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1505 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1506 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1507 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1508 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1509 clock-names = "pclk", "sclk", "sclk_sel", 1510 "lrclk", "lrclk_sel"; 1511 status = "disabled"; 1512 }; 1513 1514 tdmin_c: audio-controller@380 { 1515 compatible = "amlogic,g12a-tdmin", 1516 "amlogic,axg-tdmin"; 1517 reg = <0x0 0x380 0x0 0x40>; 1518 sound-name-prefix = "TDMIN_C"; 1519 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1520 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1521 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1522 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1523 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1524 clock-names = "pclk", "sclk", "sclk_sel", 1525 "lrclk", "lrclk_sel"; 1526 status = "disabled"; 1527 }; 1528 1529 tdmin_lb: audio-controller@3c0 { 1530 compatible = "amlogic,g12a-tdmin", 1531 "amlogic,axg-tdmin"; 1532 reg = <0x0 0x3c0 0x0 0x40>; 1533 sound-name-prefix = "TDMIN_LB"; 1534 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1535 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1536 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1537 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1538 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1539 clock-names = "pclk", "sclk", "sclk_sel", 1540 "lrclk", "lrclk_sel"; 1541 status = "disabled"; 1542 }; 1543 1544 spdifin: audio-controller@400 { 1545 compatible = "amlogic,g12a-spdifin", 1546 "amlogic,axg-spdifin"; 1547 reg = <0x0 0x400 0x0 0x30>; 1548 #sound-dai-cells = <0>; 1549 sound-name-prefix = "SPDIFIN"; 1550 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1551 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1552 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1553 clock-names = "pclk", "refclk"; 1554 status = "disabled"; 1555 }; 1556 1557 spdifout: audio-controller@480 { 1558 compatible = "amlogic,g12a-spdifout", 1559 "amlogic,axg-spdifout"; 1560 reg = <0x0 0x480 0x0 0x50>; 1561 #sound-dai-cells = <0>; 1562 sound-name-prefix = "SPDIFOUT"; 1563 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1564 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1565 clock-names = "pclk", "mclk"; 1566 status = "disabled"; 1567 }; 1568 1569 tdmout_a: audio-controller@500 { 1570 compatible = "amlogic,g12a-tdmout"; 1571 reg = <0x0 0x500 0x0 0x40>; 1572 sound-name-prefix = "TDMOUT_A"; 1573 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1574 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1575 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1576 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1577 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1578 clock-names = "pclk", "sclk", "sclk_sel", 1579 "lrclk", "lrclk_sel"; 1580 status = "disabled"; 1581 }; 1582 1583 tdmout_b: audio-controller@540 { 1584 compatible = "amlogic,g12a-tdmout"; 1585 reg = <0x0 0x540 0x0 0x40>; 1586 sound-name-prefix = "TDMOUT_B"; 1587 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1588 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1589 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1590 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1591 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1592 clock-names = "pclk", "sclk", "sclk_sel", 1593 "lrclk", "lrclk_sel"; 1594 status = "disabled"; 1595 }; 1596 1597 tdmout_c: audio-controller@580 { 1598 compatible = "amlogic,g12a-tdmout"; 1599 reg = <0x0 0x580 0x0 0x40>; 1600 sound-name-prefix = "TDMOUT_C"; 1601 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1602 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1603 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1604 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1605 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1606 clock-names = "pclk", "sclk", "sclk_sel", 1607 "lrclk", "lrclk_sel"; 1608 status = "disabled"; 1609 }; 1610 1611 spdifout_b: audio-controller@680 { 1612 compatible = "amlogic,g12a-spdifout", 1613 "amlogic,axg-spdifout"; 1614 reg = <0x0 0x680 0x0 0x50>; 1615 #sound-dai-cells = <0>; 1616 sound-name-prefix = "SPDIFOUT_B"; 1617 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1618 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1619 clock-names = "pclk", "mclk"; 1620 status = "disabled"; 1621 }; 1622 }; 1623 1624 usb3_pcie_phy: phy@46000 { 1625 compatible = "amlogic,g12a-usb3-pcie-phy"; 1626 reg = <0x0 0x46000 0x0 0x2000>; 1627 clocks = <&clkc CLKID_PCIE_PLL>; 1628 clock-names = "ref_clk"; 1629 resets = <&reset RESET_PCIE_PHY>; 1630 reset-names = "phy"; 1631 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1632 assigned-clock-rates = <100000000>; 1633 #phy-cells = <1>; 1634 }; 1635 }; 1636 1637 aobus: bus@ff800000 { 1638 compatible = "simple-bus"; 1639 reg = <0x0 0xff800000 0x0 0x100000>; 1640 #address-cells = <2>; 1641 #size-cells = <2>; 1642 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1643 1644 rti: sys-ctrl@0 { 1645 compatible = "amlogic,meson-gx-ao-sysctrl", 1646 "simple-mfd", "syscon"; 1647 reg = <0x0 0x0 0x0 0x100>; 1648 #address-cells = <2>; 1649 #size-cells = <2>; 1650 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1651 1652 clkc_AO: clock-controller { 1653 compatible = "amlogic,meson-g12a-aoclkc"; 1654 #clock-cells = <1>; 1655 #reset-cells = <1>; 1656 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1657 clock-names = "xtal", "mpeg-clk"; 1658 }; 1659 1660 pwrc_vpu: power-controller-vpu { 1661 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1662 #power-domain-cells = <0>; 1663 amlogic,hhi-sysctrl = <&hhi>; 1664 resets = <&reset RESET_VIU>, 1665 <&reset RESET_VENC>, 1666 <&reset RESET_VCBUS>, 1667 <&reset RESET_BT656>, 1668 <&reset RESET_RDMA>, 1669 <&reset RESET_VENCI>, 1670 <&reset RESET_VENCP>, 1671 <&reset RESET_VDAC>, 1672 <&reset RESET_VDI6>, 1673 <&reset RESET_VENCL>, 1674 <&reset RESET_VID_LOCK>; 1675 clocks = <&clkc CLKID_VPU>, 1676 <&clkc CLKID_VAPB>; 1677 clock-names = "vpu", "vapb"; 1678 /* 1679 * VPU clocking is provided by two identical clock paths 1680 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1681 * free mux to safely change frequency while running. 1682 * Same for VAPB but with a final gate after the glitch free mux. 1683 */ 1684 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1685 <&clkc CLKID_VPU_0>, 1686 <&clkc CLKID_VPU>, /* Glitch free mux */ 1687 <&clkc CLKID_VAPB_0_SEL>, 1688 <&clkc CLKID_VAPB_0>, 1689 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1690 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1691 <0>, /* Do Nothing */ 1692 <&clkc CLKID_VPU_0>, 1693 <&clkc CLKID_FCLK_DIV4>, 1694 <0>, /* Do Nothing */ 1695 <&clkc CLKID_VAPB_0>; 1696 assigned-clock-rates = <0>, /* Do Nothing */ 1697 <666666666>, 1698 <0>, /* Do Nothing */ 1699 <0>, /* Do Nothing */ 1700 <250000000>, 1701 <0>; /* Do Nothing */ 1702 }; 1703 1704 ao_pinctrl: pinctrl@14 { 1705 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1706 #address-cells = <2>; 1707 #size-cells = <2>; 1708 ranges; 1709 1710 gpio_ao: bank@14 { 1711 reg = <0x0 0x14 0x0 0x8>, 1712 <0x0 0x1c 0x0 0x8>, 1713 <0x0 0x24 0x0 0x14>; 1714 reg-names = "mux", 1715 "ds", 1716 "gpio"; 1717 gpio-controller; 1718 #gpio-cells = <2>; 1719 gpio-ranges = <&ao_pinctrl 0 0 15>; 1720 }; 1721 1722 i2c_ao_sck_pins: i2c_ao_sck_pins { 1723 mux { 1724 groups = "i2c_ao_sck"; 1725 function = "i2c_ao"; 1726 bias-disable; 1727 drive-strength-microamp = <3000>; 1728 }; 1729 }; 1730 1731 i2c_ao_sda_pins: i2c_ao_sda { 1732 mux { 1733 groups = "i2c_ao_sda"; 1734 function = "i2c_ao"; 1735 bias-disable; 1736 drive-strength-microamp = <3000>; 1737 }; 1738 }; 1739 1740 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1741 mux { 1742 groups = "i2c_ao_sck_e"; 1743 function = "i2c_ao"; 1744 bias-disable; 1745 drive-strength-microamp = <3000>; 1746 }; 1747 }; 1748 1749 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1750 mux { 1751 groups = "i2c_ao_sda_e"; 1752 function = "i2c_ao"; 1753 bias-disable; 1754 drive-strength-microamp = <3000>; 1755 }; 1756 }; 1757 1758 mclk0_ao_pins: mclk0-ao { 1759 mux { 1760 groups = "mclk0_ao"; 1761 function = "mclk0_ao"; 1762 bias-disable; 1763 drive-strength-microamp = <3000>; 1764 }; 1765 }; 1766 1767 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1768 mux { 1769 groups = "tdm_ao_b_din0"; 1770 function = "tdm_ao_b"; 1771 bias-disable; 1772 }; 1773 }; 1774 1775 spdif_ao_out_pins: spdif-ao-out { 1776 mux { 1777 groups = "spdif_ao_out"; 1778 function = "spdif_ao_out"; 1779 drive-strength-microamp = <500>; 1780 bias-disable; 1781 }; 1782 }; 1783 1784 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1785 mux { 1786 groups = "tdm_ao_b_din1"; 1787 function = "tdm_ao_b"; 1788 bias-disable; 1789 }; 1790 }; 1791 1792 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1793 mux { 1794 groups = "tdm_ao_b_din2"; 1795 function = "tdm_ao_b"; 1796 bias-disable; 1797 }; 1798 }; 1799 1800 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1801 mux { 1802 groups = "tdm_ao_b_dout0"; 1803 function = "tdm_ao_b"; 1804 bias-disable; 1805 drive-strength-microamp = <3000>; 1806 }; 1807 }; 1808 1809 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1810 mux { 1811 groups = "tdm_ao_b_dout1"; 1812 function = "tdm_ao_b"; 1813 bias-disable; 1814 drive-strength-microamp = <3000>; 1815 }; 1816 }; 1817 1818 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1819 mux { 1820 groups = "tdm_ao_b_dout2"; 1821 function = "tdm_ao_b"; 1822 bias-disable; 1823 drive-strength-microamp = <3000>; 1824 }; 1825 }; 1826 1827 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1828 mux { 1829 groups = "tdm_ao_b_fs"; 1830 function = "tdm_ao_b"; 1831 bias-disable; 1832 drive-strength-microamp = <3000>; 1833 }; 1834 }; 1835 1836 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1837 mux { 1838 groups = "tdm_ao_b_sclk"; 1839 function = "tdm_ao_b"; 1840 bias-disable; 1841 drive-strength-microamp = <3000>; 1842 }; 1843 }; 1844 1845 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1846 mux { 1847 groups = "tdm_ao_b_slv_fs"; 1848 function = "tdm_ao_b"; 1849 bias-disable; 1850 }; 1851 }; 1852 1853 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1854 mux { 1855 groups = "tdm_ao_b_slv_sclk"; 1856 function = "tdm_ao_b"; 1857 bias-disable; 1858 }; 1859 }; 1860 1861 uart_ao_a_pins: uart-a-ao { 1862 mux { 1863 groups = "uart_ao_a_tx", 1864 "uart_ao_a_rx"; 1865 function = "uart_ao_a"; 1866 bias-disable; 1867 }; 1868 }; 1869 1870 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1871 mux { 1872 groups = "uart_ao_a_cts", 1873 "uart_ao_a_rts"; 1874 function = "uart_ao_a"; 1875 bias-disable; 1876 }; 1877 }; 1878 1879 pwm_ao_a_pins: pwm-ao-a { 1880 mux { 1881 groups = "pwm_ao_a"; 1882 function = "pwm_ao_a"; 1883 bias-disable; 1884 }; 1885 }; 1886 1887 pwm_ao_b_pins: pwm-ao-b { 1888 mux { 1889 groups = "pwm_ao_b"; 1890 function = "pwm_ao_b"; 1891 bias-disable; 1892 }; 1893 }; 1894 1895 pwm_ao_c_4_pins: pwm-ao-c-4 { 1896 mux { 1897 groups = "pwm_ao_c_4"; 1898 function = "pwm_ao_c"; 1899 bias-disable; 1900 }; 1901 }; 1902 1903 pwm_ao_c_6_pins: pwm-ao-c-6 { 1904 mux { 1905 groups = "pwm_ao_c_6"; 1906 function = "pwm_ao_c"; 1907 bias-disable; 1908 }; 1909 }; 1910 1911 pwm_ao_d_5_pins: pwm-ao-d-5 { 1912 mux { 1913 groups = "pwm_ao_d_5"; 1914 function = "pwm_ao_d"; 1915 bias-disable; 1916 }; 1917 }; 1918 1919 pwm_ao_d_10_pins: pwm-ao-d-10 { 1920 mux { 1921 groups = "pwm_ao_d_10"; 1922 function = "pwm_ao_d"; 1923 bias-disable; 1924 }; 1925 }; 1926 1927 pwm_ao_d_e_pins: pwm-ao-d-e { 1928 mux { 1929 groups = "pwm_ao_d_e"; 1930 function = "pwm_ao_d"; 1931 }; 1932 }; 1933 1934 remote_input_ao_pins: remote-input-ao { 1935 mux { 1936 groups = "remote_ao_input"; 1937 function = "remote_ao_input"; 1938 bias-disable; 1939 }; 1940 }; 1941 }; 1942 }; 1943 1944 cec_AO: cec@100 { 1945 compatible = "amlogic,meson-gx-ao-cec"; 1946 reg = <0x0 0x00100 0x0 0x14>; 1947 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1948 clocks = <&clkc_AO CLKID_AO_CEC>; 1949 clock-names = "core"; 1950 status = "disabled"; 1951 }; 1952 1953 sec_AO: ao-secure@140 { 1954 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1955 reg = <0x0 0x140 0x0 0x140>; 1956 amlogic,has-chip-id; 1957 }; 1958 1959 cecb_AO: cec@280 { 1960 compatible = "amlogic,meson-g12a-ao-cec"; 1961 reg = <0x0 0x00280 0x0 0x1c>; 1962 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1963 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1964 clock-names = "oscin"; 1965 status = "disabled"; 1966 }; 1967 1968 pwm_AO_cd: pwm@2000 { 1969 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1970 reg = <0x0 0x2000 0x0 0x20>; 1971 #pwm-cells = <3>; 1972 status = "disabled"; 1973 }; 1974 1975 uart_AO: serial@3000 { 1976 compatible = "amlogic,meson-gx-uart", 1977 "amlogic,meson-ao-uart"; 1978 reg = <0x0 0x3000 0x0 0x18>; 1979 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1980 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1981 clock-names = "xtal", "pclk", "baud"; 1982 status = "disabled"; 1983 }; 1984 1985 uart_AO_B: serial@4000 { 1986 compatible = "amlogic,meson-gx-uart", 1987 "amlogic,meson-ao-uart"; 1988 reg = <0x0 0x4000 0x0 0x18>; 1989 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1990 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1991 clock-names = "xtal", "pclk", "baud"; 1992 status = "disabled"; 1993 }; 1994 1995 i2c_AO: i2c@5000 { 1996 compatible = "amlogic,meson-axg-i2c"; 1997 status = "disabled"; 1998 reg = <0x0 0x05000 0x0 0x20>; 1999 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 clocks = <&clkc CLKID_I2C>; 2003 }; 2004 2005 pwm_AO_ab: pwm@7000 { 2006 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2007 reg = <0x0 0x7000 0x0 0x20>; 2008 #pwm-cells = <3>; 2009 status = "disabled"; 2010 }; 2011 2012 ir: ir@8000 { 2013 compatible = "amlogic,meson-gxbb-ir"; 2014 reg = <0x0 0x8000 0x0 0x20>; 2015 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2016 status = "disabled"; 2017 }; 2018 2019 saradc: adc@9000 { 2020 compatible = "amlogic,meson-g12a-saradc", 2021 "amlogic,meson-saradc"; 2022 reg = <0x0 0x9000 0x0 0x48>; 2023 #io-channel-cells = <1>; 2024 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2025 clocks = <&xtal>, 2026 <&clkc_AO CLKID_AO_SAR_ADC>, 2027 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2028 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2029 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2030 status = "disabled"; 2031 }; 2032 }; 2033 2034 vpu: vpu@ff900000 { 2035 compatible = "amlogic,meson-g12a-vpu"; 2036 reg = <0x0 0xff900000 0x0 0x100000>, 2037 <0x0 0xff63c000 0x0 0x1000>; 2038 reg-names = "vpu", "hhi"; 2039 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 amlogic,canvas = <&canvas>; 2043 power-domains = <&pwrc_vpu>; 2044 2045 /* CVBS VDAC output port */ 2046 cvbs_vdac_port: port@0 { 2047 reg = <0>; 2048 }; 2049 2050 /* HDMI-TX output port */ 2051 hdmi_tx_port: port@1 { 2052 reg = <1>; 2053 2054 hdmi_tx_out: endpoint { 2055 remote-endpoint = <&hdmi_tx_in>; 2056 }; 2057 }; 2058 }; 2059 2060 gic: interrupt-controller@ffc01000 { 2061 compatible = "arm,gic-400"; 2062 reg = <0x0 0xffc01000 0 0x1000>, 2063 <0x0 0xffc02000 0 0x2000>, 2064 <0x0 0xffc04000 0 0x2000>, 2065 <0x0 0xffc06000 0 0x2000>; 2066 interrupt-controller; 2067 interrupts = <GIC_PPI 9 2068 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2069 #interrupt-cells = <3>; 2070 #address-cells = <0>; 2071 }; 2072 2073 cbus: bus@ffd00000 { 2074 compatible = "simple-bus"; 2075 reg = <0x0 0xffd00000 0x0 0x100000>; 2076 #address-cells = <2>; 2077 #size-cells = <2>; 2078 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2079 2080 reset: reset-controller@1004 { 2081 compatible = "amlogic,meson-g12a-reset", 2082 "amlogic,meson-axg-reset"; 2083 reg = <0x0 0x1004 0x0 0x9c>; 2084 #reset-cells = <1>; 2085 }; 2086 2087 pwm_ef: pwm@19000 { 2088 compatible = "amlogic,meson-g12a-ee-pwm"; 2089 reg = <0x0 0x19000 0x0 0x20>; 2090 #pwm-cells = <3>; 2091 status = "disabled"; 2092 }; 2093 2094 pwm_cd: pwm@1a000 { 2095 compatible = "amlogic,meson-g12a-ee-pwm"; 2096 reg = <0x0 0x1a000 0x0 0x20>; 2097 #pwm-cells = <3>; 2098 status = "disabled"; 2099 }; 2100 2101 pwm_ab: pwm@1b000 { 2102 compatible = "amlogic,meson-g12a-ee-pwm"; 2103 reg = <0x0 0x1b000 0x0 0x20>; 2104 #pwm-cells = <3>; 2105 status = "disabled"; 2106 }; 2107 2108 i2c3: i2c@1c000 { 2109 compatible = "amlogic,meson-axg-i2c"; 2110 status = "disabled"; 2111 reg = <0x0 0x1c000 0x0 0x20>; 2112 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 clocks = <&clkc CLKID_I2C>; 2116 }; 2117 2118 i2c2: i2c@1d000 { 2119 compatible = "amlogic,meson-axg-i2c"; 2120 status = "disabled"; 2121 reg = <0x0 0x1d000 0x0 0x20>; 2122 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 clocks = <&clkc CLKID_I2C>; 2126 }; 2127 2128 i2c1: i2c@1e000 { 2129 compatible = "amlogic,meson-axg-i2c"; 2130 status = "disabled"; 2131 reg = <0x0 0x1e000 0x0 0x20>; 2132 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2133 #address-cells = <1>; 2134 #size-cells = <0>; 2135 clocks = <&clkc CLKID_I2C>; 2136 }; 2137 2138 i2c0: i2c@1f000 { 2139 compatible = "amlogic,meson-axg-i2c"; 2140 status = "disabled"; 2141 reg = <0x0 0x1f000 0x0 0x20>; 2142 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2143 #address-cells = <1>; 2144 #size-cells = <0>; 2145 clocks = <&clkc CLKID_I2C>; 2146 }; 2147 2148 clk_msr: clock-measure@18000 { 2149 compatible = "amlogic,meson-g12a-clk-measure"; 2150 reg = <0x0 0x18000 0x0 0x10>; 2151 }; 2152 2153 uart_C: serial@22000 { 2154 compatible = "amlogic,meson-gx-uart"; 2155 reg = <0x0 0x22000 0x0 0x18>; 2156 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2157 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2158 clock-names = "xtal", "pclk", "baud"; 2159 status = "disabled"; 2160 }; 2161 2162 uart_B: serial@23000 { 2163 compatible = "amlogic,meson-gx-uart"; 2164 reg = <0x0 0x23000 0x0 0x18>; 2165 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2166 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2167 clock-names = "xtal", "pclk", "baud"; 2168 status = "disabled"; 2169 }; 2170 2171 uart_A: serial@24000 { 2172 compatible = "amlogic,meson-gx-uart"; 2173 reg = <0x0 0x24000 0x0 0x18>; 2174 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2175 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2176 clock-names = "xtal", "pclk", "baud"; 2177 status = "disabled"; 2178 }; 2179 }; 2180 2181 sd_emmc_b: sd@ffe05000 { 2182 compatible = "amlogic,meson-axg-mmc"; 2183 reg = <0x0 0xffe05000 0x0 0x800>; 2184 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2185 status = "disabled"; 2186 clocks = <&clkc CLKID_SD_EMMC_B>, 2187 <&clkc CLKID_SD_EMMC_B_CLK0>, 2188 <&clkc CLKID_FCLK_DIV2>; 2189 clock-names = "core", "clkin0", "clkin1"; 2190 resets = <&reset RESET_SD_EMMC_B>; 2191 }; 2192 2193 sd_emmc_c: mmc@ffe07000 { 2194 compatible = "amlogic,meson-axg-mmc"; 2195 reg = <0x0 0xffe07000 0x0 0x800>; 2196 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2197 status = "disabled"; 2198 clocks = <&clkc CLKID_SD_EMMC_C>, 2199 <&clkc CLKID_SD_EMMC_C_CLK0>, 2200 <&clkc CLKID_FCLK_DIV2>; 2201 clock-names = "core", "clkin0", "clkin1"; 2202 resets = <&reset RESET_SD_EMMC_C>; 2203 }; 2204 2205 usb: usb@ffe09000 { 2206 status = "disabled"; 2207 compatible = "amlogic,meson-g12a-usb-ctrl"; 2208 reg = <0x0 0xffe09000 0x0 0xa0>; 2209 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2210 #address-cells = <2>; 2211 #size-cells = <2>; 2212 ranges; 2213 2214 clocks = <&clkc CLKID_USB>; 2215 resets = <&reset RESET_USB>; 2216 2217 dr_mode = "otg"; 2218 2219 phys = <&usb2_phy0>, <&usb2_phy1>, 2220 <&usb3_pcie_phy PHY_TYPE_USB3>; 2221 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2222 2223 dwc2: usb@ff400000 { 2224 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2225 reg = <0x0 0xff400000 0x0 0x40000>; 2226 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2228 clock-names = "ddr"; 2229 phys = <&usb2_phy1>; 2230 dr_mode = "peripheral"; 2231 g-rx-fifo-size = <192>; 2232 g-np-tx-fifo-size = <128>; 2233 g-tx-fifo-size = <128 128 16 16 16>; 2234 }; 2235 2236 dwc3: usb@ff500000 { 2237 compatible = "snps,dwc3"; 2238 reg = <0x0 0xff500000 0x0 0x100000>; 2239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2240 dr_mode = "host"; 2241 snps,dis_u2_susphy_quirk; 2242 snps,quirk-frame-length-adjustment; 2243 }; 2244 }; 2245 2246 mali: gpu@ffe40000 { 2247 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2248 reg = <0x0 0xffe40000 0x0 0x40000>; 2249 interrupt-parent = <&gic>; 2250 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2253 interrupt-names = "gpu", "mmu", "job"; 2254 clocks = <&clkc CLKID_MALI>; 2255 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2256 2257 /* 2258 * Mali clocking is provided by two identical clock paths 2259 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2260 * free mux to safely change frequency while running. 2261 */ 2262 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2263 <&clkc CLKID_MALI_0>, 2264 <&clkc CLKID_MALI>; /* Glitch free mux */ 2265 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2266 <0>, /* Do Nothing */ 2267 <&clkc CLKID_MALI_0>; 2268 assigned-clock-rates = <0>, /* Do Nothing */ 2269 <800000000>, 2270 <0>; /* Do Nothing */ 2271 }; 2272 }; 2273 2274 timer { 2275 compatible = "arm,armv8-timer"; 2276 interrupts = <GIC_PPI 13 2277 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2278 <GIC_PPI 14 2279 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2280 <GIC_PPI 11 2281 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2282 <GIC_PPI 10 2283 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2284 }; 2285 2286 xtal: xtal-clk { 2287 compatible = "fixed-clock"; 2288 clock-frequency = <24000000>; 2289 clock-output-names = "xtal"; 2290 #clock-cells = <0>; 2291 }; 2292 2293}; 2294