arm64: dts: qcom: sc7280: Add WCN6750 WiFi node

Add DTS node for WCN6750 WiFi chipset.

Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.o

arm64: dts: qcom: sc7280: Add WCN6750 WiFi node

Add DTS node for WCN6750 WiFi chipset.

Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220406111303.27670-1-quic_mpubbise@quicinc.com

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arm64: dts: qcom: sc7280: Add WPSS remoteproc node

Add the WPSS remoteproc node in dts for
PIL loading.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rakesh Pillai <quic_pillair@qu

arm64: dts: qcom: sc7280: Add WPSS remoteproc node

Add the WPSS remoteproc node in dts for
PIL loading.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rakesh Pillai <quic_pillair@quicinc.com>
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220328070701.28551-1-quic_mpubbise@quicinc.com

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arm64: dts: qcom: sc7280: Add cpu OPP tables

Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaeh

arm64: dts: qcom: sc7280: Add cpu OPP tables

Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644428757-25575-1-git-send-email-quic_sibis@quicinc.com

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arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Acked-by:

arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1634812857-10676-4-git-send-email-okukatla@codeaurora.org

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arm64: dts: qcom: sc7280: Add a blank line in the dp node

It's weird that there's a blank line between the two port nodes but
not between the attributes and the first port node. Add an extra blank
l

arm64: dts: qcom: sc7280: Add a blank line in the dp node

It's weird that there's a blank line between the two port nodes but
not between the attributes and the first port node. Add an extra blank
line to make it look right.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.11.Iecb7267402e697a5cfef4cd517116ea5b308ac9e@changeid

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arm64: dts: qcom: sc7280: Move dp_hot_plug_det pull from SoC dtsi file

Pulls should be in the board files, not in the SoC dtsi
file. Remove. Even though the sc7280 boards don't currently refer to
dp

arm64: dts: qcom: sc7280: Move dp_hot_plug_det pull from SoC dtsi file

Pulls should be in the board files, not in the SoC dtsi
file. Remove. Even though the sc7280 boards don't currently refer to
dp_hot_plug_det, let's re-add the pulls there just to keep this as a
no-op change. If boards don't need this / don't want it later then we
can remove it from them.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.10.Id346b23642f91e16d68d75f44bcdb5b9fbd155ea@changeid

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arm64: dts: qcom: sc7280: Move pcie1_clkreq pull / drive str to boards

Pullups and drive strength don't belong in the SoC dtsi file. Move to
the board file.

Signed-off-by: Douglas Anderson <diander

arm64: dts: qcom: sc7280: Move pcie1_clkreq pull / drive str to boards

Pullups and drive strength don't belong in the SoC dtsi file. Move to
the board file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.8.Iffff0c12440a047212a164601e637b03b9d2fc78@changeid

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arm64: dts: qcom: sc7280: Add edp_out port and HPD lines

Like dp_out, we should have defined edp_out in sc7280.dtsi so we don't
need to do this in the board files.

Like dp_hot_plug_det, we should d

arm64: dts: qcom: sc7280: Add edp_out port and HPD lines

Like dp_out, we should have defined edp_out in sc7280.dtsi so we don't
need to do this in the board files.

Like dp_hot_plug_det, we should define edp_hot_plug_det in
sc7280.dtsi.

We should set the default pinctrl for edp_hot_plug_det in
sc7280.dtsi. NOTE: this is _unlike_ the dp_hot_plug_det. It is
reasonable that in some boards the dedicated DP Hot Plug Detect will
not be hooked up in favor of Type C mechanisms. This is unlike eDP
where the Hot Plug Detect line (which functions as "panel ready" in
eDP) is highly likely to be used by boards.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.7.Ic84bb69c45be2fccf50e3bd17b845fe20eec624c@changeid

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arm64: dts: qcom: sc7280: Fix sort order of dp_hot_plug_det / pcie1_clkreq_n

The two nodes were mis-sorted. Reorder. This is a no-op change.

Signed-off-by: Douglas Anderson <dianders@chromium.org>

arm64: dts: qcom: sc7280: Fix sort order of dp_hot_plug_det / pcie1_clkreq_n

The two nodes were mis-sorted. Reorder. This is a no-op change.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.6.I874c6f2a62b7922a33e10d390a8983219a76250b@changeid

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arm64: dts: qcom: sc7280: Clean up sdc1 / sdc2 pinctrl

This patch makes a few improvements to the way that sdc1 / sdc2
pinctrl is specified on sc7280:

1. There's no reason to "group" the sdc pins i

arm64: dts: qcom: sc7280: Clean up sdc1 / sdc2 pinctrl

This patch makes a few improvements to the way that sdc1 / sdc2
pinctrl is specified on sc7280:

1. There's no reason to "group" the sdc pins into one overarching node
and there's a downside: we have to replicate the hierarchy in the
board device tree files. Let's clean this up.

2. There's really not a lot of reason not to list the "pinctrl" for
sdc1 (eMMC) in the SoC dtsi file. These aren't GPIO pins and
everyone's going to specify the same pins.

3. Even though it's likely that boards will need to override pinctrl
for sdc2 (SD card) to add the card detect GPIO, we can be symmetric
and add it to the SoC dsti file.

4. Let's get rid of the word "on" from the normal config and add a
"sleep" suffix to the sleep config. This looks cleaner to me.

This is intended to be a no-op change but it could plausibly change
behavior depending on how the pinctrl code parses things. One thing to
note is that "SD card detect" is explicitly listed now as keeping its
pull enabled in sleep since we still want to detect card insertions
even if the controller is suspended (because no card is inserted). The
pinctrl framework likely did this anyway, but it's nice to see it
explicit.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.4.I79baad7f52351aafb470f8b21a9fa79d7031ad6a@changeid

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arm64: dts: qcom: sc7280: Properly sort sdc pinctrl lines

The sdc1 / sdc2 pinctrl lines were randomly stuffed in the middle of
the qup pinctrl lines. Sort them properly. This is a no-op
change. Just

arm64: dts: qcom: sc7280: Properly sort sdc pinctrl lines

The sdc1 / sdc2 pinctrl lines were randomly stuffed in the middle of
the qup pinctrl lines. Sort them properly. This is a no-op
change. Just code movement.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.3.I6ae594129a8ad3d18af9f5ebffd895b4f6353a0a@changeid

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arm64: dts: qcom: add IPA qcom,qmp property

At least three platforms require the "qcom,qmp" property to be
specified, so the IPA driver can request register retention across
power collapse. Update

arm64: dts: qcom: add IPA qcom,qmp property

At least three platforms require the "qcom,qmp" property to be
specified, so the IPA driver can request register retention across
power collapse. Update DTS files accordingly.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220201140723.467431-1-elder@linaro.org

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arm64: dts: qcom: sc7280: Factor gpio.h include to sc7280.dtsi

Though sc7280 itself doesn't need any of the defines in gpio.h, it's
highly likely that the actual boards will use them. Let's add the

arm64: dts: qcom: sc7280: Factor gpio.h include to sc7280.dtsi

Though sc7280 itself doesn't need any of the defines in gpio.h, it's
highly likely that the actual boards will use them. Let's add the
include to the sc7280.dtsi file so that boards don't need to do it.

Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220125144316.v2.4.I3194c8bdb2ad3212665286fa273710a3c4840e94@changeid

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arm64: dts: qcom: sc7280: Fix gmu unit address

When processing sc7280 device trees, I can see:

Warning (simple_bus_reg): /soc@0/gmu@3d69000:
simple-bus unit address format error, expected "3d

arm64: dts: qcom: sc7280: Fix gmu unit address

When processing sc7280 device trees, I can see:

Warning (simple_bus_reg): /soc@0/gmu@3d69000:
simple-bus unit address format error, expected "3d6a000"

There's a clear typo in the node name. Fix it.

Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220125144316.v2.1.I19f60014e9be4b9dda4d66b5d56ef3d9600b6e10@changeid

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arm64: dts: qcom: sc7280: Add camcc clock node

Add the camera clock controller node for SC7280 SoC.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
S

arm64: dts: qcom: sc7280: Add camcc clock node

Add the camera clock controller node for SC7280 SoC.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220124184437.9278-1-tdas@codeaurora.org

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arm64: dts: qcom: sc7280: Add Display Port node

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sankeerth Billakanti <quic_sbilla

arm64: dts: qcom: sc7280: Add Display Port node

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-5-git-send-email-quic_sbillaka@quicinc.com

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arm64: dts: qcom: sc7280: add edp display dt nodes

Add edp controller and phy DT nodes for sc7280.

Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Krishna Manikandan

arm64: dts: qcom: sc7280: add edp display dt nodes

Add edp controller and phy DT nodes for sc7280.

Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-4-git-send-email-quic_sbillaka@quicinc.com

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arm64: dts: qcom: sc7280: Add DSI display nodes

Add DSI controller and PHY nodes for sc7280.

Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: Krishna Manikandan <quic_mkrishn

arm64: dts: qcom: sc7280: Add DSI display nodes

Add DSI controller and PHY nodes for sc7280.

Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-3-git-send-email-quic_sbillaka@quicinc.com

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arm64: dts: qcom: sc7280: add display dt nodes

Add mdss and mdp DT nodes for sc7280.

Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Sig

arm64: dts: qcom: sc7280: add display dt nodes

Add mdss and mdp DT nodes for sc7280.

Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-2-git-send-email-quic_sbillaka@quicinc.com

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arm64: qcom: dts: drop legacy property #stream-id-cells

Property #stream-id-cells is legacy leftover and isn't currently
documented nor used.

Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-

arm64: qcom: dts: drop legacy property #stream-id-cells

Property #stream-id-cells is legacy leftover and isn't currently
documented nor used.

Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211208184707.100716-1-david@ixit.cz

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arm64: dts: qcom: sc7280: Fix 'interrupt-map' parent address cells

Update interrupt-map parent address cells for sc7280
Similar to existing Qcom SoCs.

Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: A

arm64: dts: qcom: sc7280: Fix 'interrupt-map' parent address cells

Update interrupt-map parent address cells for sc7280
Similar to existing Qcom SoCs.

Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1637060508-30375-4-git-send-email-pmaliset@codeaurora.org

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arm64: dts: qcom: sc7280: Add pcie clock support

Add pcie clock phandle for sc7280 SoC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Sig

arm64: dts: qcom: sc7280: Add pcie clock support

Add pcie clock phandle for sc7280 SoC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1637060508-30375-3-git-send-email-pmaliset@codeaurora.org

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arm64: dts: qcom: sc7280: Fix incorrect clock name

Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk
To match with dt binding.

Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock

arm64: dts: qcom: sc7280: Fix incorrect clock name

Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk
To match with dt binding.

Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1637060508-30375-2-git-send-email-pmaliset@codeaurora.org

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arm64: dts: qcom: sc7280: Add venus DT node

Add DT entries for the sc7280 venus encoder/decoder.

Co-developed-by: Mansur Alisha Shaik <mansur@codeaurora.org>
Signed-off-by: Mansur Alisha Shaik <man

arm64: dts: qcom: sc7280: Add venus DT node

Add DT entries for the sc7280 venus encoder/decoder.

Co-developed-by: Mansur Alisha Shaik <mansur@codeaurora.org>
Signed-off-by: Mansur Alisha Shaik <mansur@codeaurora.org>
Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635259922-25378-1-git-send-email-quic_dikshita@quicinc.com

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arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes

Add PCIe controller and PHY nodes for sc7280 SOC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboy

arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes

Add PCIe controller and PHY nodes for sc7280 SOC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1633628923-25047-3-git-send-email-pmaliset@codeaurora.org

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