1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 video_mem: memory@8b200000 { 133 reg = <0x0 0x8b200000 0x0 0x500000>; 134 no-map; 135 }; 136 137 ipa_fw_mem: memory@8b700000 { 138 reg = <0 0x8b700000 0 0x10000>; 139 no-map; 140 }; 141 142 rmtfs_mem: memory@9c900000 { 143 compatible = "qcom,rmtfs-mem"; 144 reg = <0x0 0x9c900000 0x0 0x280000>; 145 no-map; 146 147 qcom,client-id = <1>; 148 qcom,vmid = <15>; 149 }; 150 }; 151 152 cpus { 153 #address-cells = <2>; 154 #size-cells = <0>; 155 156 CPU0: cpu@0 { 157 device_type = "cpu"; 158 compatible = "arm,kryo"; 159 reg = <0x0 0x0>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 #cooling-cells = <2>; 167 L2_0: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 L3_0: l3-cache { 171 compatible = "cache"; 172 }; 173 }; 174 }; 175 176 CPU1: cpu@100 { 177 device_type = "cpu"; 178 compatible = "arm,kryo"; 179 reg = <0x0 0x100>; 180 enable-method = "psci"; 181 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 182 &LITTLE_CPU_SLEEP_1 183 &CLUSTER_SLEEP_0>; 184 next-level-cache = <&L2_100>; 185 qcom,freq-domain = <&cpufreq_hw 0>; 186 #cooling-cells = <2>; 187 L2_100: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU2: cpu@200 { 194 device_type = "cpu"; 195 compatible = "arm,kryo"; 196 reg = <0x0 0x200>; 197 enable-method = "psci"; 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 199 &LITTLE_CPU_SLEEP_1 200 &CLUSTER_SLEEP_0>; 201 next-level-cache = <&L2_200>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_200: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU3: cpu@300 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x300>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_300>; 219 qcom,freq-domain = <&cpufreq_hw 0>; 220 #cooling-cells = <2>; 221 L2_300: l2-cache { 222 compatible = "cache"; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU4: cpu@400 { 228 device_type = "cpu"; 229 compatible = "arm,kryo"; 230 reg = <0x0 0x400>; 231 enable-method = "psci"; 232 cpu-idle-states = <&BIG_CPU_SLEEP_0 233 &BIG_CPU_SLEEP_1 234 &CLUSTER_SLEEP_0>; 235 next-level-cache = <&L2_400>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 #cooling-cells = <2>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "arm,kryo"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 250 &BIG_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 next-level-cache = <&L2_500>; 253 qcom,freq-domain = <&cpufreq_hw 1>; 254 #cooling-cells = <2>; 255 L2_500: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU6: cpu@600 { 262 device_type = "cpu"; 263 compatible = "arm,kryo"; 264 reg = <0x0 0x600>; 265 enable-method = "psci"; 266 cpu-idle-states = <&BIG_CPU_SLEEP_0 267 &BIG_CPU_SLEEP_1 268 &CLUSTER_SLEEP_0>; 269 next-level-cache = <&L2_600>; 270 qcom,freq-domain = <&cpufreq_hw 1>; 271 #cooling-cells = <2>; 272 L2_600: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "arm,kryo"; 281 reg = <0x0 0x700>; 282 enable-method = "psci"; 283 cpu-idle-states = <&BIG_CPU_SLEEP_0 284 &BIG_CPU_SLEEP_1 285 &CLUSTER_SLEEP_0>; 286 next-level-cache = <&L2_700>; 287 qcom,freq-domain = <&cpufreq_hw 2>; 288 #cooling-cells = <2>; 289 L2_700: l2-cache { 290 compatible = "cache"; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "little-power-down"; 337 arm,psci-suspend-param = <0x40000003>; 338 entry-latency-us = <549>; 339 exit-latency-us = <901>; 340 min-residency-us = <1774>; 341 local-timer-stop; 342 }; 343 344 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "little-rail-power-down"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <915>; 350 min-residency-us = <4001>; 351 local-timer-stop; 352 }; 353 354 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 355 compatible = "arm,idle-state"; 356 idle-state-name = "big-power-down"; 357 arm,psci-suspend-param = <0x40000003>; 358 entry-latency-us = <523>; 359 exit-latency-us = <1244>; 360 min-residency-us = <2207>; 361 local-timer-stop; 362 }; 363 364 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 365 compatible = "arm,idle-state"; 366 idle-state-name = "big-rail-power-down"; 367 arm,psci-suspend-param = <0x40000004>; 368 entry-latency-us = <526>; 369 exit-latency-us = <1854>; 370 min-residency-us = <5555>; 371 local-timer-stop; 372 }; 373 374 CLUSTER_SLEEP_0: cluster-sleep-0 { 375 compatible = "arm,idle-state"; 376 idle-state-name = "cluster-power-down"; 377 arm,psci-suspend-param = <0x40003444>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9926>; 381 local-timer-stop; 382 }; 383 }; 384 }; 385 386 memory@80000000 { 387 device_type = "memory"; 388 /* We expect the bootloader to fill in the size */ 389 reg = <0 0x80000000 0 0>; 390 }; 391 392 firmware { 393 scm { 394 compatible = "qcom,scm-sc7280", "qcom,scm"; 395 }; 396 }; 397 398 clk_virt: interconnect { 399 compatible = "qcom,sc7280-clk-virt"; 400 #interconnect-cells = <2>; 401 qcom,bcm-voters = <&apps_bcm_voter>; 402 }; 403 404 smem { 405 compatible = "qcom,smem"; 406 memory-region = <&smem_mem>; 407 hwlocks = <&tcsr_mutex 3>; 408 }; 409 410 smp2p-adsp { 411 compatible = "qcom,smp2p"; 412 qcom,smem = <443>, <429>; 413 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 414 IPCC_MPROC_SIGNAL_SMP2P 415 IRQ_TYPE_EDGE_RISING>; 416 mboxes = <&ipcc IPCC_CLIENT_LPASS 417 IPCC_MPROC_SIGNAL_SMP2P>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <2>; 421 422 adsp_smp2p_out: master-kernel { 423 qcom,entry-name = "master-kernel"; 424 #qcom,smem-state-cells = <1>; 425 }; 426 427 adsp_smp2p_in: slave-kernel { 428 qcom,entry-name = "slave-kernel"; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 smp2p-cdsp { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <94>, <432>; 437 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 438 IPCC_MPROC_SIGNAL_SMP2P 439 IRQ_TYPE_EDGE_RISING>; 440 mboxes = <&ipcc IPCC_CLIENT_CDSP 441 IPCC_MPROC_SIGNAL_SMP2P>; 442 443 qcom,local-pid = <0>; 444 qcom,remote-pid = <5>; 445 446 cdsp_smp2p_out: master-kernel { 447 qcom,entry-name = "master-kernel"; 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 cdsp_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 smp2p-mpss { 459 compatible = "qcom,smp2p"; 460 qcom,smem = <435>, <428>; 461 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 462 IPCC_MPROC_SIGNAL_SMP2P 463 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&ipcc IPCC_CLIENT_MPSS 465 IPCC_MPROC_SIGNAL_SMP2P>; 466 467 qcom,local-pid = <0>; 468 qcom,remote-pid = <1>; 469 470 modem_smp2p_out: master-kernel { 471 qcom,entry-name = "master-kernel"; 472 #qcom,smem-state-cells = <1>; 473 }; 474 475 modem_smp2p_in: slave-kernel { 476 qcom,entry-name = "slave-kernel"; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 ipa_smp2p_out: ipa-ap-to-modem { 482 qcom,entry-name = "ipa"; 483 #qcom,smem-state-cells = <1>; 484 }; 485 486 ipa_smp2p_in: ipa-modem-to-ap { 487 qcom,entry-name = "ipa"; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 }; 492 493 smp2p-wpss { 494 compatible = "qcom,smp2p"; 495 qcom,smem = <617>, <616>; 496 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 497 IPCC_MPROC_SIGNAL_SMP2P 498 IRQ_TYPE_EDGE_RISING>; 499 mboxes = <&ipcc IPCC_CLIENT_WPSS 500 IPCC_MPROC_SIGNAL_SMP2P>; 501 502 qcom,local-pid = <0>; 503 qcom,remote-pid = <13>; 504 505 wpss_smp2p_out: master-kernel { 506 qcom,entry-name = "master-kernel"; 507 #qcom,smem-state-cells = <1>; 508 }; 509 510 wpss_smp2p_in: slave-kernel { 511 qcom,entry-name = "slave-kernel"; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 }; 516 517 pmu { 518 compatible = "arm,armv8-pmuv3"; 519 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 520 }; 521 522 psci { 523 compatible = "arm,psci-1.0"; 524 method = "smc"; 525 }; 526 527 qspi_opp_table: qspi-opp-table { 528 compatible = "operating-points-v2"; 529 530 opp-75000000 { 531 opp-hz = /bits/ 64 <75000000>; 532 required-opps = <&rpmhpd_opp_low_svs>; 533 }; 534 535 opp-150000000 { 536 opp-hz = /bits/ 64 <150000000>; 537 required-opps = <&rpmhpd_opp_svs>; 538 }; 539 540 opp-200000000 { 541 opp-hz = /bits/ 64 <200000000>; 542 required-opps = <&rpmhpd_opp_svs_l1>; 543 }; 544 545 opp-300000000 { 546 opp-hz = /bits/ 64 <300000000>; 547 required-opps = <&rpmhpd_opp_nom>; 548 }; 549 }; 550 551 qup_opp_table: qup-opp-table { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 564 opp-128000000 { 565 opp-hz = /bits/ 64 <128000000>; 566 required-opps = <&rpmhpd_opp_nom>; 567 }; 568 }; 569 570 soc: soc@0 { 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges = <0 0 0 0 0x10 0>; 574 dma-ranges = <0 0 0 0 0x10 0>; 575 compatible = "simple-bus"; 576 577 gcc: clock-controller@100000 { 578 compatible = "qcom,gcc-sc7280"; 579 reg = <0 0x00100000 0 0x1f0000>; 580 clocks = <&rpmhcc RPMH_CXO_CLK>, 581 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 582 <0>, <&pcie1_lane 0>, 583 <0>, <0>, <0>, <0>; 584 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 585 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 586 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 587 "ufs_phy_tx_symbol_0_clk", 588 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 589 #clock-cells = <1>; 590 #reset-cells = <1>; 591 #power-domain-cells = <1>; 592 }; 593 594 ipcc: mailbox@408000 { 595 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 596 reg = <0 0x00408000 0 0x1000>; 597 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-controller; 599 #interrupt-cells = <3>; 600 #mbox-cells = <2>; 601 }; 602 603 qfprom: efuse@784000 { 604 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 605 reg = <0 0x00784000 0 0xa20>, 606 <0 0x00780000 0 0xa20>, 607 <0 0x00782000 0 0x120>, 608 <0 0x00786000 0 0x1fff>; 609 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 610 clock-names = "core"; 611 power-domains = <&rpmhpd SC7280_MX>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 }; 615 616 sdhc_1: sdhci@7c4000 { 617 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 618 status = "disabled"; 619 620 reg = <0 0x007c4000 0 0x1000>, 621 <0 0x007c5000 0 0x1000>; 622 reg-names = "hc", "cqhci"; 623 624 iommus = <&apps_smmu 0xc0 0x0>; 625 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "hc_irq", "pwr_irq"; 628 629 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 630 <&gcc GCC_SDCC1_AHB_CLK>, 631 <&rpmhcc RPMH_CXO_CLK>; 632 clock-names = "core", "iface", "xo"; 633 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 635 interconnect-names = "sdhc-ddr","cpu-sdhc"; 636 power-domains = <&rpmhpd SC7280_CX>; 637 operating-points-v2 = <&sdhc1_opp_table>; 638 639 bus-width = <8>; 640 supports-cqe; 641 642 qcom,dll-config = <0x0007642c>; 643 qcom,ddr-config = <0x80040868>; 644 645 mmc-ddr-1_8v; 646 mmc-hs200-1_8v; 647 mmc-hs400-1_8v; 648 mmc-hs400-enhanced-strobe; 649 650 sdhc1_opp_table: opp-table { 651 compatible = "operating-points-v2"; 652 653 opp-100000000 { 654 opp-hz = /bits/ 64 <100000000>; 655 required-opps = <&rpmhpd_opp_low_svs>; 656 opp-peak-kBps = <1800000 400000>; 657 opp-avg-kBps = <100000 0>; 658 }; 659 660 opp-384000000 { 661 opp-hz = /bits/ 64 <384000000>; 662 required-opps = <&rpmhpd_opp_nom>; 663 opp-peak-kBps = <5400000 1600000>; 664 opp-avg-kBps = <390000 0>; 665 }; 666 }; 667 668 }; 669 670 qupv3_id_0: geniqup@9c0000 { 671 compatible = "qcom,geni-se-qup"; 672 reg = <0 0x009c0000 0 0x2000>; 673 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 674 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 675 clock-names = "m-ahb", "s-ahb"; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 ranges; 679 iommus = <&apps_smmu 0x123 0x0>; 680 status = "disabled"; 681 682 i2c0: i2c@980000 { 683 compatible = "qcom,geni-i2c"; 684 reg = <0 0x00980000 0 0x4000>; 685 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 686 clock-names = "se"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&qup_i2c0_data_clk>; 689 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 694 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 695 interconnect-names = "qup-core", "qup-config", 696 "qup-memory"; 697 status = "disabled"; 698 }; 699 700 spi0: spi@980000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0 0x00980000 0 0x4000>; 703 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 704 clock-names = "se"; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 707 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 power-domains = <&rpmhpd SC7280_CX>; 711 operating-points-v2 = <&qup_opp_table>; 712 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 714 interconnect-names = "qup-core", "qup-config"; 715 status = "disabled"; 716 }; 717 718 uart0: serial@980000 { 719 compatible = "qcom,geni-uart"; 720 reg = <0 0x00980000 0 0x4000>; 721 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 722 clock-names = "se"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 725 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 726 power-domains = <&rpmhpd SC7280_CX>; 727 operating-points-v2 = <&qup_opp_table>; 728 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 729 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 730 interconnect-names = "qup-core", "qup-config"; 731 status = "disabled"; 732 }; 733 734 i2c1: i2c@984000 { 735 compatible = "qcom,geni-i2c"; 736 reg = <0 0x00984000 0 0x4000>; 737 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 738 clock-names = "se"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&qup_i2c1_data_clk>; 741 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 745 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 746 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 747 interconnect-names = "qup-core", "qup-config", 748 "qup-memory"; 749 status = "disabled"; 750 }; 751 752 spi1: spi@984000 { 753 compatible = "qcom,geni-spi"; 754 reg = <0 0x00984000 0 0x4000>; 755 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 756 clock-names = "se"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 759 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 power-domains = <&rpmhpd SC7280_CX>; 763 operating-points-v2 = <&qup_opp_table>; 764 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 765 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 766 interconnect-names = "qup-core", "qup-config"; 767 status = "disabled"; 768 }; 769 770 uart1: serial@984000 { 771 compatible = "qcom,geni-uart"; 772 reg = <0 0x00984000 0 0x4000>; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 774 clock-names = "se"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 777 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 778 power-domains = <&rpmhpd SC7280_CX>; 779 operating-points-v2 = <&qup_opp_table>; 780 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 781 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 782 interconnect-names = "qup-core", "qup-config"; 783 status = "disabled"; 784 }; 785 786 i2c2: i2c@988000 { 787 compatible = "qcom,geni-i2c"; 788 reg = <0 0x00988000 0 0x4000>; 789 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 790 clock-names = "se"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&qup_i2c2_data_clk>; 793 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 798 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 799 interconnect-names = "qup-core", "qup-config", 800 "qup-memory"; 801 status = "disabled"; 802 }; 803 804 spi2: spi@988000 { 805 compatible = "qcom,geni-spi"; 806 reg = <0 0x00988000 0 0x4000>; 807 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 808 clock-names = "se"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 811 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 power-domains = <&rpmhpd SC7280_CX>; 815 operating-points-v2 = <&qup_opp_table>; 816 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 818 interconnect-names = "qup-core", "qup-config"; 819 status = "disabled"; 820 }; 821 822 uart2: serial@988000 { 823 compatible = "qcom,geni-uart"; 824 reg = <0 0x00988000 0 0x4000>; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 826 clock-names = "se"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 829 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd SC7280_CX>; 831 operating-points-v2 = <&qup_opp_table>; 832 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 833 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 834 interconnect-names = "qup-core", "qup-config"; 835 status = "disabled"; 836 }; 837 838 i2c3: i2c@98c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0098c000 0 0x4000>; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 842 clock-names = "se"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c3_data_clk>; 845 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 849 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 850 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 851 interconnect-names = "qup-core", "qup-config", 852 "qup-memory"; 853 status = "disabled"; 854 }; 855 856 spi3: spi@98c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0098c000 0 0x4000>; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 860 clock-names = "se"; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 863 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 power-domains = <&rpmhpd SC7280_CX>; 867 operating-points-v2 = <&qup_opp_table>; 868 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 870 interconnect-names = "qup-core", "qup-config"; 871 status = "disabled"; 872 }; 873 874 uart3: serial@98c000 { 875 compatible = "qcom,geni-uart"; 876 reg = <0 0x0098c000 0 0x4000>; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 878 clock-names = "se"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 881 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 882 power-domains = <&rpmhpd SC7280_CX>; 883 operating-points-v2 = <&qup_opp_table>; 884 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 886 interconnect-names = "qup-core", "qup-config"; 887 status = "disabled"; 888 }; 889 890 i2c4: i2c@990000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00990000 0 0x4000>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 894 clock-names = "se"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c4_data_clk>; 897 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 901 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 902 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 903 interconnect-names = "qup-core", "qup-config", 904 "qup-memory"; 905 status = "disabled"; 906 }; 907 908 spi4: spi@990000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0 0x00990000 0 0x4000>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 912 clock-names = "se"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 915 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 power-domains = <&rpmhpd SC7280_CX>; 919 operating-points-v2 = <&qup_opp_table>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 922 interconnect-names = "qup-core", "qup-config"; 923 status = "disabled"; 924 }; 925 926 uart4: serial@990000 { 927 compatible = "qcom,geni-uart"; 928 reg = <0 0x00990000 0 0x4000>; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 930 clock-names = "se"; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 933 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC7280_CX>; 935 operating-points-v2 = <&qup_opp_table>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 938 interconnect-names = "qup-core", "qup-config"; 939 status = "disabled"; 940 }; 941 942 i2c5: i2c@994000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0 0x00994000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 946 clock-names = "se"; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_i2c5_data_clk>; 949 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 953 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 954 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 955 interconnect-names = "qup-core", "qup-config", 956 "qup-memory"; 957 status = "disabled"; 958 }; 959 960 spi5: spi@994000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00994000 0 0x4000>; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 964 clock-names = "se"; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 967 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 power-domains = <&rpmhpd SC7280_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 uart5: serial@994000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00994000 0 0x4000>; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 982 clock-names = "se"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 985 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7280_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c6: i2c@998000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00998000 0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 998 clock-names = "se"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c6_data_clk>; 1001 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 status = "disabled"; 1010 }; 1011 1012 spi6: spi@998000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00998000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1016 clock-names = "se"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1019 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 power-domains = <&rpmhpd SC7280_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 uart6: serial@998000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0 0x00998000 0 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1034 clock-names = "se"; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1037 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1038 power-domains = <&rpmhpd SC7280_CX>; 1039 operating-points-v2 = <&qup_opp_table>; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1042 interconnect-names = "qup-core", "qup-config"; 1043 status = "disabled"; 1044 }; 1045 1046 i2c7: i2c@99c000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x0099c000 0 0x4000>; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1050 clock-names = "se"; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c7_data_clk>; 1053 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1057 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1058 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1059 interconnect-names = "qup-core", "qup-config", 1060 "qup-memory"; 1061 status = "disabled"; 1062 }; 1063 1064 spi7: spi@99c000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x0099c000 0 0x4000>; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1068 clock-names = "se"; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1071 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 power-domains = <&rpmhpd SC7280_CX>; 1075 operating-points-v2 = <&qup_opp_table>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 status = "disabled"; 1080 }; 1081 1082 uart7: serial@99c000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x0099c000 0 0x4000>; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1086 clock-names = "se"; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1089 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1090 power-domains = <&rpmhpd SC7280_CX>; 1091 operating-points-v2 = <&qup_opp_table>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 qupv3_id_1: geniqup@ac0000 { 1100 compatible = "qcom,geni-se-qup"; 1101 reg = <0 0x00ac0000 0 0x2000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1103 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1104 clock-names = "m-ahb", "s-ahb"; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 iommus = <&apps_smmu 0x43 0x0>; 1109 status = "disabled"; 1110 1111 i2c8: i2c@a80000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x00a80000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c8_data_clk>; 1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1123 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1124 interconnect-names = "qup-core", "qup-config", 1125 "qup-memory"; 1126 status = "disabled"; 1127 }; 1128 1129 spi8: spi@a80000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0 0x00a80000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1136 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 power-domains = <&rpmhpd SC7280_CX>; 1140 operating-points-v2 = <&qup_opp_table>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1143 interconnect-names = "qup-core", "qup-config"; 1144 status = "disabled"; 1145 }; 1146 1147 uart8: serial@a80000 { 1148 compatible = "qcom,geni-uart"; 1149 reg = <0 0x00a80000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1154 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC7280_CX>; 1156 operating-points-v2 = <&qup_opp_table>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1159 interconnect-names = "qup-core", "qup-config"; 1160 status = "disabled"; 1161 }; 1162 1163 i2c9: i2c@a84000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00a84000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1167 clock-names = "se"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c9_data_clk>; 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", 1177 "qup-memory"; 1178 status = "disabled"; 1179 }; 1180 1181 spi9: spi@a84000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00a84000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1188 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 power-domains = <&rpmhpd SC7280_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 uart9: serial@a84000 { 1200 compatible = "qcom,geni-uart"; 1201 reg = <0 0x00a84000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1203 clock-names = "se"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c10: i2c@a88000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00a88000 0 0x4000>; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1219 clock-names = "se"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_i2c10_data_clk>; 1222 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1227 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1228 interconnect-names = "qup-core", "qup-config", 1229 "qup-memory"; 1230 status = "disabled"; 1231 }; 1232 1233 spi10: spi@a88000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0 0x00a88000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1240 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 power-domains = <&rpmhpd SC7280_CX>; 1244 operating-points-v2 = <&qup_opp_table>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1247 interconnect-names = "qup-core", "qup-config"; 1248 status = "disabled"; 1249 }; 1250 1251 uart10: serial@a88000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0 0x00a88000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1258 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1259 power-domains = <&rpmhpd SC7280_CX>; 1260 operating-points-v2 = <&qup_opp_table>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1262 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1263 interconnect-names = "qup-core", "qup-config"; 1264 status = "disabled"; 1265 }; 1266 1267 i2c11: i2c@a8c000 { 1268 compatible = "qcom,geni-i2c"; 1269 reg = <0 0x00a8c000 0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1271 clock-names = "se"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_i2c11_data_clk>; 1274 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1279 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1280 interconnect-names = "qup-core", "qup-config", 1281 "qup-memory"; 1282 status = "disabled"; 1283 }; 1284 1285 spi11: spi@a8c000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00a8c000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1292 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 uart11: serial@a8c000 { 1304 compatible = "qcom,geni-uart"; 1305 reg = <0 0x00a8c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1310 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1311 power-domains = <&rpmhpd SC7280_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1315 interconnect-names = "qup-core", "qup-config"; 1316 status = "disabled"; 1317 }; 1318 1319 i2c12: i2c@a90000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0 0x00a90000 0 0x4000>; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1323 clock-names = "se"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_i2c12_data_clk>; 1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1331 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", 1333 "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 spi12: spi@a90000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0 0x00a90000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 power-domains = <&rpmhpd SC7280_CX>; 1348 operating-points-v2 = <&qup_opp_table>; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1350 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1351 interconnect-names = "qup-core", "qup-config"; 1352 status = "disabled"; 1353 }; 1354 1355 uart12: serial@a90000 { 1356 compatible = "qcom,geni-uart"; 1357 reg = <0 0x00a90000 0 0x4000>; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1359 clock-names = "se"; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1362 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1363 power-domains = <&rpmhpd SC7280_CX>; 1364 operating-points-v2 = <&qup_opp_table>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1367 interconnect-names = "qup-core", "qup-config"; 1368 status = "disabled"; 1369 }; 1370 1371 i2c13: i2c@a94000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00a94000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1375 clock-names = "se"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_i2c13_data_clk>; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1382 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1383 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1384 interconnect-names = "qup-core", "qup-config", 1385 "qup-memory"; 1386 status = "disabled"; 1387 }; 1388 1389 spi13: spi@a94000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a94000 0 0x4000>; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1393 clock-names = "se"; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1396 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 power-domains = <&rpmhpd SC7280_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 1407 uart13: serial@a94000 { 1408 compatible = "qcom,geni-uart"; 1409 reg = <0 0x00a94000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1414 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC7280_CX>; 1416 operating-points-v2 = <&qup_opp_table>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1419 interconnect-names = "qup-core", "qup-config"; 1420 status = "disabled"; 1421 }; 1422 1423 i2c14: i2c@a98000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x00a98000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1427 clock-names = "se"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_i2c14_data_clk>; 1430 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1435 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", 1437 "qup-memory"; 1438 status = "disabled"; 1439 }; 1440 1441 spi14: spi@a98000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a98000 0 0x4000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1445 clock-names = "se"; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1448 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&rpmhpd SC7280_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1455 interconnect-names = "qup-core", "qup-config"; 1456 status = "disabled"; 1457 }; 1458 1459 uart14: serial@a98000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00a98000 0 0x4000>; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1463 clock-names = "se"; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1466 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SC7280_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 status = "disabled"; 1473 }; 1474 1475 i2c15: i2c@a9c000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a9c000 0 0x4000>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1479 clock-names = "se"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c15_data_clk>; 1482 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", 1489 "qup-memory"; 1490 status = "disabled"; 1491 }; 1492 1493 spi15: spi@a9c000 { 1494 compatible = "qcom,geni-spi"; 1495 reg = <0 0x00a9c000 0 0x4000>; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1497 clock-names = "se"; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1500 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 status = "disabled"; 1509 }; 1510 1511 uart15: serial@a9c000 { 1512 compatible = "qcom,geni-uart"; 1513 reg = <0 0x00a9c000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1518 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC7280_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1523 interconnect-names = "qup-core", "qup-config"; 1524 status = "disabled"; 1525 }; 1526 }; 1527 1528 cnoc2: interconnect@1500000 { 1529 reg = <0 0x01500000 0 0x1000>; 1530 compatible = "qcom,sc7280-cnoc2"; 1531 #interconnect-cells = <2>; 1532 qcom,bcm-voters = <&apps_bcm_voter>; 1533 }; 1534 1535 cnoc3: interconnect@1502000 { 1536 reg = <0 0x01502000 0 0x1000>; 1537 compatible = "qcom,sc7280-cnoc3"; 1538 #interconnect-cells = <2>; 1539 qcom,bcm-voters = <&apps_bcm_voter>; 1540 }; 1541 1542 mc_virt: interconnect@1580000 { 1543 reg = <0 0x01580000 0 0x4>; 1544 compatible = "qcom,sc7280-mc-virt"; 1545 #interconnect-cells = <2>; 1546 qcom,bcm-voters = <&apps_bcm_voter>; 1547 }; 1548 1549 system_noc: interconnect@1680000 { 1550 reg = <0 0x01680000 0 0x15480>; 1551 compatible = "qcom,sc7280-system-noc"; 1552 #interconnect-cells = <2>; 1553 qcom,bcm-voters = <&apps_bcm_voter>; 1554 }; 1555 1556 aggre1_noc: interconnect@16e0000 { 1557 compatible = "qcom,sc7280-aggre1-noc"; 1558 reg = <0 0x016e0000 0 0x1c080>; 1559 #interconnect-cells = <2>; 1560 qcom,bcm-voters = <&apps_bcm_voter>; 1561 }; 1562 1563 aggre2_noc: interconnect@1700000 { 1564 reg = <0 0x01700000 0 0x2b080>; 1565 compatible = "qcom,sc7280-aggre2-noc"; 1566 #interconnect-cells = <2>; 1567 qcom,bcm-voters = <&apps_bcm_voter>; 1568 }; 1569 1570 mmss_noc: interconnect@1740000 { 1571 reg = <0 0x01740000 0 0x1e080>; 1572 compatible = "qcom,sc7280-mmss-noc"; 1573 #interconnect-cells = <2>; 1574 qcom,bcm-voters = <&apps_bcm_voter>; 1575 }; 1576 1577 pcie1: pci@1c08000 { 1578 compatible = "qcom,pcie-sc7280"; 1579 reg = <0 0x01c08000 0 0x3000>, 1580 <0 0x40000000 0 0xf1d>, 1581 <0 0x40000f20 0 0xa8>, 1582 <0 0x40001000 0 0x1000>, 1583 <0 0x40100000 0 0x100000>; 1584 1585 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1586 device_type = "pci"; 1587 linux,pci-domain = <1>; 1588 bus-range = <0x00 0xff>; 1589 num-lanes = <2>; 1590 1591 #address-cells = <3>; 1592 #size-cells = <2>; 1593 1594 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1595 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1596 1597 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1598 interrupt-names = "msi"; 1599 #interrupt-cells = <1>; 1600 interrupt-map-mask = <0 0 0 0x7>; 1601 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1602 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1604 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1605 1606 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1607 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1608 <&pcie1_lane 0>, 1609 <&rpmhcc RPMH_CXO_CLK>, 1610 <&gcc GCC_PCIE_1_AUX_CLK>, 1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1615 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1616 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1617 1618 clock-names = "pipe", 1619 "pipe_mux", 1620 "phy_pipe", 1621 "ref", 1622 "aux", 1623 "cfg", 1624 "bus_master", 1625 "bus_slave", 1626 "slave_q2a", 1627 "tbu", 1628 "ddrss_sf_tbu"; 1629 1630 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1631 assigned-clock-rates = <19200000>; 1632 1633 resets = <&gcc GCC_PCIE_1_BCR>; 1634 reset-names = "pci"; 1635 1636 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1637 1638 phys = <&pcie1_lane>; 1639 phy-names = "pciephy"; 1640 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&pcie1_clkreq_n>; 1643 1644 iommus = <&apps_smmu 0x1c80 0x1>; 1645 1646 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1647 <0x100 &apps_smmu 0x1c81 0x1>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x1c0>; 1655 #address-cells = <2>; 1656 #size-cells = <2>; 1657 ranges; 1658 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1659 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1660 <&gcc GCC_PCIE_CLKREF_EN>, 1661 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1662 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1663 1664 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1665 reset-names = "phy"; 1666 1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1668 assigned-clock-rates = <100000000>; 1669 1670 status = "disabled"; 1671 1672 pcie1_lane: lanes@1c0e200 { 1673 reg = <0 0x01c0e200 0 0x170>, 1674 <0 0x01c0e400 0 0x200>, 1675 <0 0x01c0ea00 0 0x1f0>, 1676 <0 0x01c0e600 0 0x170>, 1677 <0 0x01c0e800 0 0x200>, 1678 <0 0x01c0ee00 0 0xf4>; 1679 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1680 clock-names = "pipe0"; 1681 1682 #phy-cells = <0>; 1683 #clock-cells = <1>; 1684 clock-output-names = "pcie_1_pipe_clk"; 1685 }; 1686 }; 1687 1688 ipa: ipa@1e40000 { 1689 compatible = "qcom,sc7280-ipa"; 1690 1691 iommus = <&apps_smmu 0x480 0x0>, 1692 <&apps_smmu 0x482 0x0>; 1693 reg = <0 0x1e40000 0 0x8000>, 1694 <0 0x1e50000 0 0x4ad0>, 1695 <0 0x1e04000 0 0x23000>; 1696 reg-names = "ipa-reg", 1697 "ipa-shared", 1698 "gsi"; 1699 1700 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1701 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1702 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1703 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1704 interrupt-names = "ipa", 1705 "gsi", 1706 "ipa-clock-query", 1707 "ipa-setup-ready"; 1708 1709 clocks = <&rpmhcc RPMH_IPA_CLK>; 1710 clock-names = "core"; 1711 1712 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1714 interconnect-names = "memory", 1715 "config"; 1716 1717 qcom,smem-states = <&ipa_smp2p_out 0>, 1718 <&ipa_smp2p_out 1>; 1719 qcom,smem-state-names = "ipa-clock-enabled-valid", 1720 "ipa-clock-enabled"; 1721 1722 status = "disabled"; 1723 }; 1724 1725 tcsr_mutex: hwlock@1f40000 { 1726 compatible = "qcom,tcsr-mutex", "syscon"; 1727 reg = <0 0x01f40000 0 0x40000>; 1728 #hwlock-cells = <1>; 1729 }; 1730 1731 tcsr: syscon@1fc0000 { 1732 compatible = "qcom,sc7280-tcsr", "syscon"; 1733 reg = <0 0x01fc0000 0 0x30000>; 1734 }; 1735 1736 lpasscc: lpasscc@3000000 { 1737 compatible = "qcom,sc7280-lpasscc"; 1738 reg = <0 0x03000000 0 0x40>, 1739 <0 0x03c04000 0 0x4>, 1740 <0 0x03389000 0 0x24>; 1741 reg-names = "qdsp6ss", "top_cc", "cc"; 1742 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1743 clock-names = "iface"; 1744 #clock-cells = <1>; 1745 }; 1746 1747 lpass_ag_noc: interconnect@3c40000 { 1748 reg = <0 0x03c40000 0 0xf080>; 1749 compatible = "qcom,sc7280-lpass-ag-noc"; 1750 #interconnect-cells = <2>; 1751 qcom,bcm-voters = <&apps_bcm_voter>; 1752 }; 1753 1754 gpu: gpu@3d00000 { 1755 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1756 reg = <0 0x03d00000 0 0x40000>, 1757 <0 0x03d9e000 0 0x1000>, 1758 <0 0x03d61000 0 0x800>; 1759 reg-names = "kgsl_3d0_reg_memory", 1760 "cx_mem", 1761 "cx_dbgc"; 1762 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1763 iommus = <&adreno_smmu 0 0x401>; 1764 operating-points-v2 = <&gpu_opp_table>; 1765 qcom,gmu = <&gmu>; 1766 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1767 interconnect-names = "gfx-mem"; 1768 #cooling-cells = <2>; 1769 1770 gpu_opp_table: opp-table { 1771 compatible = "operating-points-v2"; 1772 1773 opp-315000000 { 1774 opp-hz = /bits/ 64 <315000000>; 1775 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1776 opp-peak-kBps = <1804000>; 1777 }; 1778 1779 opp-450000000 { 1780 opp-hz = /bits/ 64 <450000000>; 1781 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1782 opp-peak-kBps = <4068000>; 1783 }; 1784 1785 opp-550000000 { 1786 opp-hz = /bits/ 64 <550000000>; 1787 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1788 opp-peak-kBps = <6832000>; 1789 }; 1790 }; 1791 }; 1792 1793 gmu: gmu@3d69000 { 1794 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1795 reg = <0 0x03d6a000 0 0x34000>, 1796 <0 0x3de0000 0 0x10000>, 1797 <0 0x0b290000 0 0x10000>; 1798 reg-names = "gmu", "rscc", "gmu_pdc"; 1799 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1801 interrupt-names = "hfi", "gmu"; 1802 clocks = <&gpucc 5>, 1803 <&gpucc 8>, 1804 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1805 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1806 <&gpucc 2>, 1807 <&gpucc 15>, 1808 <&gpucc 11>; 1809 clock-names = "gmu", 1810 "cxo", 1811 "axi", 1812 "memnoc", 1813 "ahb", 1814 "hub", 1815 "smmu_vote"; 1816 power-domains = <&gpucc 0>, 1817 <&gpucc 1>; 1818 power-domain-names = "cx", 1819 "gx"; 1820 iommus = <&adreno_smmu 5 0x400>; 1821 operating-points-v2 = <&gmu_opp_table>; 1822 1823 gmu_opp_table: opp-table { 1824 compatible = "operating-points-v2"; 1825 1826 opp-200000000 { 1827 opp-hz = /bits/ 64 <200000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1829 }; 1830 }; 1831 }; 1832 1833 gpucc: clock-controller@3d90000 { 1834 compatible = "qcom,sc7280-gpucc"; 1835 reg = <0 0x03d90000 0 0x9000>; 1836 clocks = <&rpmhcc RPMH_CXO_CLK>, 1837 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1838 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1839 clock-names = "bi_tcxo", 1840 "gcc_gpu_gpll0_clk_src", 1841 "gcc_gpu_gpll0_div_clk_src"; 1842 #clock-cells = <1>; 1843 #reset-cells = <1>; 1844 #power-domain-cells = <1>; 1845 }; 1846 1847 adreno_smmu: iommu@3da0000 { 1848 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1849 reg = <0 0x03da0000 0 0x20000>; 1850 #iommu-cells = <2>; 1851 #global-interrupts = <2>; 1852 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1864 1865 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1866 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1867 <&gpucc 2>, 1868 <&gpucc 11>, 1869 <&gpucc 5>, 1870 <&gpucc 15>, 1871 <&gpucc 13>; 1872 clock-names = "gcc_gpu_memnoc_gfx_clk", 1873 "gcc_gpu_snoc_dvm_gfx_clk", 1874 "gpu_cc_ahb_clk", 1875 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1876 "gpu_cc_cx_gmu_clk", 1877 "gpu_cc_hub_cx_int_clk", 1878 "gpu_cc_hub_aon_clk"; 1879 1880 power-domains = <&gpucc 0>; 1881 }; 1882 1883 remoteproc_mpss: remoteproc@4080000 { 1884 compatible = "qcom,sc7280-mpss-pas"; 1885 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1886 reg-names = "qdsp6", "rmb"; 1887 1888 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1889 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1890 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1891 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1894 interrupt-names = "wdog", "fatal", "ready", "handover", 1895 "stop-ack", "shutdown-ack"; 1896 1897 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1898 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1899 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1900 <&rpmhcc RPMH_PKA_CLK>, 1901 <&rpmhcc RPMH_CXO_CLK>; 1902 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1903 1904 power-domains = <&rpmhpd SC7280_CX>, 1905 <&rpmhpd SC7280_MSS>; 1906 power-domain-names = "cx", "mss"; 1907 1908 memory-region = <&mpss_mem>; 1909 1910 qcom,qmp = <&aoss_qmp>; 1911 1912 qcom,smem-states = <&modem_smp2p_out 0>; 1913 qcom,smem-state-names = "stop"; 1914 1915 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1916 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1917 reset-names = "mss_restart", "pdc_reset"; 1918 1919 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1920 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1921 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1922 1923 status = "disabled"; 1924 1925 glink-edge { 1926 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1927 IPCC_MPROC_SIGNAL_GLINK_QMP 1928 IRQ_TYPE_EDGE_RISING>; 1929 mboxes = <&ipcc IPCC_CLIENT_MPSS 1930 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1931 label = "modem"; 1932 qcom,remote-pid = <1>; 1933 }; 1934 }; 1935 1936 stm@6002000 { 1937 compatible = "arm,coresight-stm", "arm,primecell"; 1938 reg = <0 0x06002000 0 0x1000>, 1939 <0 0x16280000 0 0x180000>; 1940 reg-names = "stm-base", "stm-stimulus-base"; 1941 1942 clocks = <&aoss_qmp>; 1943 clock-names = "apb_pclk"; 1944 1945 out-ports { 1946 port { 1947 stm_out: endpoint { 1948 remote-endpoint = <&funnel0_in7>; 1949 }; 1950 }; 1951 }; 1952 }; 1953 1954 funnel@6041000 { 1955 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1956 reg = <0 0x06041000 0 0x1000>; 1957 1958 clocks = <&aoss_qmp>; 1959 clock-names = "apb_pclk"; 1960 1961 out-ports { 1962 port { 1963 funnel0_out: endpoint { 1964 remote-endpoint = <&merge_funnel_in0>; 1965 }; 1966 }; 1967 }; 1968 1969 in-ports { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 port@7 { 1974 reg = <7>; 1975 funnel0_in7: endpoint { 1976 remote-endpoint = <&stm_out>; 1977 }; 1978 }; 1979 }; 1980 }; 1981 1982 funnel@6042000 { 1983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1984 reg = <0 0x06042000 0 0x1000>; 1985 1986 clocks = <&aoss_qmp>; 1987 clock-names = "apb_pclk"; 1988 1989 out-ports { 1990 port { 1991 funnel1_out: endpoint { 1992 remote-endpoint = <&merge_funnel_in1>; 1993 }; 1994 }; 1995 }; 1996 1997 in-ports { 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 port@4 { 2002 reg = <4>; 2003 funnel1_in4: endpoint { 2004 remote-endpoint = <&apss_merge_funnel_out>; 2005 }; 2006 }; 2007 }; 2008 }; 2009 2010 funnel@6045000 { 2011 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2012 reg = <0 0x06045000 0 0x1000>; 2013 2014 clocks = <&aoss_qmp>; 2015 clock-names = "apb_pclk"; 2016 2017 out-ports { 2018 port { 2019 merge_funnel_out: endpoint { 2020 remote-endpoint = <&swao_funnel_in>; 2021 }; 2022 }; 2023 }; 2024 2025 in-ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 2029 port@0 { 2030 reg = <0>; 2031 merge_funnel_in0: endpoint { 2032 remote-endpoint = <&funnel0_out>; 2033 }; 2034 }; 2035 2036 port@1 { 2037 reg = <1>; 2038 merge_funnel_in1: endpoint { 2039 remote-endpoint = <&funnel1_out>; 2040 }; 2041 }; 2042 }; 2043 }; 2044 2045 replicator@6046000 { 2046 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2047 reg = <0 0x06046000 0 0x1000>; 2048 2049 clocks = <&aoss_qmp>; 2050 clock-names = "apb_pclk"; 2051 2052 out-ports { 2053 port { 2054 replicator_out: endpoint { 2055 remote-endpoint = <&etr_in>; 2056 }; 2057 }; 2058 }; 2059 2060 in-ports { 2061 port { 2062 replicator_in: endpoint { 2063 remote-endpoint = <&swao_replicator_out>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 etr@6048000 { 2070 compatible = "arm,coresight-tmc", "arm,primecell"; 2071 reg = <0 0x06048000 0 0x1000>; 2072 iommus = <&apps_smmu 0x04c0 0>; 2073 2074 clocks = <&aoss_qmp>; 2075 clock-names = "apb_pclk"; 2076 arm,scatter-gather; 2077 2078 in-ports { 2079 port { 2080 etr_in: endpoint { 2081 remote-endpoint = <&replicator_out>; 2082 }; 2083 }; 2084 }; 2085 }; 2086 2087 funnel@6b04000 { 2088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2089 reg = <0 0x06b04000 0 0x1000>; 2090 2091 clocks = <&aoss_qmp>; 2092 clock-names = "apb_pclk"; 2093 2094 out-ports { 2095 port { 2096 swao_funnel_out: endpoint { 2097 remote-endpoint = <&etf_in>; 2098 }; 2099 }; 2100 }; 2101 2102 in-ports { 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 port@7 { 2107 reg = <7>; 2108 swao_funnel_in: endpoint { 2109 remote-endpoint = <&merge_funnel_out>; 2110 }; 2111 }; 2112 }; 2113 }; 2114 2115 etf@6b05000 { 2116 compatible = "arm,coresight-tmc", "arm,primecell"; 2117 reg = <0 0x06b05000 0 0x1000>; 2118 2119 clocks = <&aoss_qmp>; 2120 clock-names = "apb_pclk"; 2121 2122 out-ports { 2123 port { 2124 etf_out: endpoint { 2125 remote-endpoint = <&swao_replicator_in>; 2126 }; 2127 }; 2128 }; 2129 2130 in-ports { 2131 port { 2132 etf_in: endpoint { 2133 remote-endpoint = <&swao_funnel_out>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 replicator@6b06000 { 2140 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2141 reg = <0 0x06b06000 0 0x1000>; 2142 2143 clocks = <&aoss_qmp>; 2144 clock-names = "apb_pclk"; 2145 qcom,replicator-loses-context; 2146 2147 out-ports { 2148 port { 2149 swao_replicator_out: endpoint { 2150 remote-endpoint = <&replicator_in>; 2151 }; 2152 }; 2153 }; 2154 2155 in-ports { 2156 port { 2157 swao_replicator_in: endpoint { 2158 remote-endpoint = <&etf_out>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 etm@7040000 { 2165 compatible = "arm,coresight-etm4x", "arm,primecell"; 2166 reg = <0 0x07040000 0 0x1000>; 2167 2168 cpu = <&CPU0>; 2169 2170 clocks = <&aoss_qmp>; 2171 clock-names = "apb_pclk"; 2172 arm,coresight-loses-context-with-cpu; 2173 qcom,skip-power-up; 2174 2175 out-ports { 2176 port { 2177 etm0_out: endpoint { 2178 remote-endpoint = <&apss_funnel_in0>; 2179 }; 2180 }; 2181 }; 2182 }; 2183 2184 etm@7140000 { 2185 compatible = "arm,coresight-etm4x", "arm,primecell"; 2186 reg = <0 0x07140000 0 0x1000>; 2187 2188 cpu = <&CPU1>; 2189 2190 clocks = <&aoss_qmp>; 2191 clock-names = "apb_pclk"; 2192 arm,coresight-loses-context-with-cpu; 2193 qcom,skip-power-up; 2194 2195 out-ports { 2196 port { 2197 etm1_out: endpoint { 2198 remote-endpoint = <&apss_funnel_in1>; 2199 }; 2200 }; 2201 }; 2202 }; 2203 2204 etm@7240000 { 2205 compatible = "arm,coresight-etm4x", "arm,primecell"; 2206 reg = <0 0x07240000 0 0x1000>; 2207 2208 cpu = <&CPU2>; 2209 2210 clocks = <&aoss_qmp>; 2211 clock-names = "apb_pclk"; 2212 arm,coresight-loses-context-with-cpu; 2213 qcom,skip-power-up; 2214 2215 out-ports { 2216 port { 2217 etm2_out: endpoint { 2218 remote-endpoint = <&apss_funnel_in2>; 2219 }; 2220 }; 2221 }; 2222 }; 2223 2224 etm@7340000 { 2225 compatible = "arm,coresight-etm4x", "arm,primecell"; 2226 reg = <0 0x07340000 0 0x1000>; 2227 2228 cpu = <&CPU3>; 2229 2230 clocks = <&aoss_qmp>; 2231 clock-names = "apb_pclk"; 2232 arm,coresight-loses-context-with-cpu; 2233 qcom,skip-power-up; 2234 2235 out-ports { 2236 port { 2237 etm3_out: endpoint { 2238 remote-endpoint = <&apss_funnel_in3>; 2239 }; 2240 }; 2241 }; 2242 }; 2243 2244 etm@7440000 { 2245 compatible = "arm,coresight-etm4x", "arm,primecell"; 2246 reg = <0 0x07440000 0 0x1000>; 2247 2248 cpu = <&CPU4>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 arm,coresight-loses-context-with-cpu; 2253 qcom,skip-power-up; 2254 2255 out-ports { 2256 port { 2257 etm4_out: endpoint { 2258 remote-endpoint = <&apss_funnel_in4>; 2259 }; 2260 }; 2261 }; 2262 }; 2263 2264 etm@7540000 { 2265 compatible = "arm,coresight-etm4x", "arm,primecell"; 2266 reg = <0 0x07540000 0 0x1000>; 2267 2268 cpu = <&CPU5>; 2269 2270 clocks = <&aoss_qmp>; 2271 clock-names = "apb_pclk"; 2272 arm,coresight-loses-context-with-cpu; 2273 qcom,skip-power-up; 2274 2275 out-ports { 2276 port { 2277 etm5_out: endpoint { 2278 remote-endpoint = <&apss_funnel_in5>; 2279 }; 2280 }; 2281 }; 2282 }; 2283 2284 etm@7640000 { 2285 compatible = "arm,coresight-etm4x", "arm,primecell"; 2286 reg = <0 0x07640000 0 0x1000>; 2287 2288 cpu = <&CPU6>; 2289 2290 clocks = <&aoss_qmp>; 2291 clock-names = "apb_pclk"; 2292 arm,coresight-loses-context-with-cpu; 2293 qcom,skip-power-up; 2294 2295 out-ports { 2296 port { 2297 etm6_out: endpoint { 2298 remote-endpoint = <&apss_funnel_in6>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 etm@7740000 { 2305 compatible = "arm,coresight-etm4x", "arm,primecell"; 2306 reg = <0 0x07740000 0 0x1000>; 2307 2308 cpu = <&CPU7>; 2309 2310 clocks = <&aoss_qmp>; 2311 clock-names = "apb_pclk"; 2312 arm,coresight-loses-context-with-cpu; 2313 qcom,skip-power-up; 2314 2315 out-ports { 2316 port { 2317 etm7_out: endpoint { 2318 remote-endpoint = <&apss_funnel_in7>; 2319 }; 2320 }; 2321 }; 2322 }; 2323 2324 funnel@7800000 { /* APSS Funnel */ 2325 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2326 reg = <0 0x07800000 0 0x1000>; 2327 2328 clocks = <&aoss_qmp>; 2329 clock-names = "apb_pclk"; 2330 2331 out-ports { 2332 port { 2333 apss_funnel_out: endpoint { 2334 remote-endpoint = <&apss_merge_funnel_in>; 2335 }; 2336 }; 2337 }; 2338 2339 in-ports { 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 2343 port@0 { 2344 reg = <0>; 2345 apss_funnel_in0: endpoint { 2346 remote-endpoint = <&etm0_out>; 2347 }; 2348 }; 2349 2350 port@1 { 2351 reg = <1>; 2352 apss_funnel_in1: endpoint { 2353 remote-endpoint = <&etm1_out>; 2354 }; 2355 }; 2356 2357 port@2 { 2358 reg = <2>; 2359 apss_funnel_in2: endpoint { 2360 remote-endpoint = <&etm2_out>; 2361 }; 2362 }; 2363 2364 port@3 { 2365 reg = <3>; 2366 apss_funnel_in3: endpoint { 2367 remote-endpoint = <&etm3_out>; 2368 }; 2369 }; 2370 2371 port@4 { 2372 reg = <4>; 2373 apss_funnel_in4: endpoint { 2374 remote-endpoint = <&etm4_out>; 2375 }; 2376 }; 2377 2378 port@5 { 2379 reg = <5>; 2380 apss_funnel_in5: endpoint { 2381 remote-endpoint = <&etm5_out>; 2382 }; 2383 }; 2384 2385 port@6 { 2386 reg = <6>; 2387 apss_funnel_in6: endpoint { 2388 remote-endpoint = <&etm6_out>; 2389 }; 2390 }; 2391 2392 port@7 { 2393 reg = <7>; 2394 apss_funnel_in7: endpoint { 2395 remote-endpoint = <&etm7_out>; 2396 }; 2397 }; 2398 }; 2399 }; 2400 2401 funnel@7810000 { 2402 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2403 reg = <0 0x07810000 0 0x1000>; 2404 2405 clocks = <&aoss_qmp>; 2406 clock-names = "apb_pclk"; 2407 2408 out-ports { 2409 port { 2410 apss_merge_funnel_out: endpoint { 2411 remote-endpoint = <&funnel1_in4>; 2412 }; 2413 }; 2414 }; 2415 2416 in-ports { 2417 port { 2418 apss_merge_funnel_in: endpoint { 2419 remote-endpoint = <&apss_funnel_out>; 2420 }; 2421 }; 2422 }; 2423 }; 2424 2425 sdhc_2: sdhci@8804000 { 2426 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2427 status = "disabled"; 2428 2429 reg = <0 0x08804000 0 0x1000>; 2430 2431 iommus = <&apps_smmu 0x100 0x0>; 2432 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2434 interrupt-names = "hc_irq", "pwr_irq"; 2435 2436 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2437 <&gcc GCC_SDCC2_AHB_CLK>, 2438 <&rpmhcc RPMH_CXO_CLK>; 2439 clock-names = "core", "iface", "xo"; 2440 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2442 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2443 power-domains = <&rpmhpd SC7280_CX>; 2444 operating-points-v2 = <&sdhc2_opp_table>; 2445 2446 bus-width = <4>; 2447 2448 qcom,dll-config = <0x0007642c>; 2449 2450 sdhc2_opp_table: opp-table { 2451 compatible = "operating-points-v2"; 2452 2453 opp-100000000 { 2454 opp-hz = /bits/ 64 <100000000>; 2455 required-opps = <&rpmhpd_opp_low_svs>; 2456 opp-peak-kBps = <1800000 400000>; 2457 opp-avg-kBps = <100000 0>; 2458 }; 2459 2460 opp-202000000 { 2461 opp-hz = /bits/ 64 <202000000>; 2462 required-opps = <&rpmhpd_opp_nom>; 2463 opp-peak-kBps = <5400000 1600000>; 2464 opp-avg-kBps = <200000 0>; 2465 }; 2466 }; 2467 2468 }; 2469 2470 usb_1_hsphy: phy@88e3000 { 2471 compatible = "qcom,sc7280-usb-hs-phy", 2472 "qcom,usb-snps-hs-7nm-phy"; 2473 reg = <0 0x088e3000 0 0x400>; 2474 status = "disabled"; 2475 #phy-cells = <0>; 2476 2477 clocks = <&rpmhcc RPMH_CXO_CLK>; 2478 clock-names = "ref"; 2479 2480 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2481 }; 2482 2483 usb_2_hsphy: phy@88e4000 { 2484 compatible = "qcom,sc7280-usb-hs-phy", 2485 "qcom,usb-snps-hs-7nm-phy"; 2486 reg = <0 0x088e4000 0 0x400>; 2487 status = "disabled"; 2488 #phy-cells = <0>; 2489 2490 clocks = <&rpmhcc RPMH_CXO_CLK>; 2491 clock-names = "ref"; 2492 2493 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2494 }; 2495 2496 usb_1_qmpphy: phy-wrapper@88e9000 { 2497 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2498 "qcom,sm8250-qmp-usb3-dp-phy"; 2499 reg = <0 0x088e9000 0 0x200>, 2500 <0 0x088e8000 0 0x40>, 2501 <0 0x088ea000 0 0x200>; 2502 status = "disabled"; 2503 #address-cells = <2>; 2504 #size-cells = <2>; 2505 ranges; 2506 2507 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2508 <&rpmhcc RPMH_CXO_CLK>, 2509 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2510 clock-names = "aux", "ref_clk_src", "com_aux"; 2511 2512 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2513 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2514 reset-names = "phy", "common"; 2515 2516 usb_1_ssphy: usb3-phy@88e9200 { 2517 reg = <0 0x088e9200 0 0x200>, 2518 <0 0x088e9400 0 0x200>, 2519 <0 0x088e9c00 0 0x400>, 2520 <0 0x088e9600 0 0x200>, 2521 <0 0x088e9800 0 0x200>, 2522 <0 0x088e9a00 0 0x100>; 2523 #clock-cells = <0>; 2524 #phy-cells = <0>; 2525 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2526 clock-names = "pipe0"; 2527 clock-output-names = "usb3_phy_pipe_clk_src"; 2528 }; 2529 2530 dp_phy: dp-phy@88ea200 { 2531 reg = <0 0x088ea200 0 0x200>, 2532 <0 0x088ea400 0 0x200>, 2533 <0 0x088eaa00 0 0x200>, 2534 <0 0x088ea600 0 0x200>, 2535 <0 0x088ea800 0 0x200>; 2536 #phy-cells = <0>; 2537 #clock-cells = <1>; 2538 }; 2539 }; 2540 2541 usb_2: usb@8cf8800 { 2542 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2543 reg = <0 0x08cf8800 0 0x400>; 2544 status = "disabled"; 2545 #address-cells = <2>; 2546 #size-cells = <2>; 2547 ranges; 2548 dma-ranges; 2549 2550 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2551 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2552 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2553 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2554 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2555 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2556 "sleep"; 2557 2558 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2559 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2560 assigned-clock-rates = <19200000>, <200000000>; 2561 2562 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2563 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2564 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2565 interrupt-names = "hs_phy_irq", 2566 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2567 2568 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2569 2570 resets = <&gcc GCC_USB30_SEC_BCR>; 2571 2572 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2574 interconnect-names = "usb-ddr", "apps-usb"; 2575 2576 usb_2_dwc3: usb@8c00000 { 2577 compatible = "snps,dwc3"; 2578 reg = <0 0x08c00000 0 0xe000>; 2579 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2580 iommus = <&apps_smmu 0xa0 0x0>; 2581 snps,dis_u2_susphy_quirk; 2582 snps,dis_enblslpm_quirk; 2583 phys = <&usb_2_hsphy>; 2584 phy-names = "usb2-phy"; 2585 maximum-speed = "high-speed"; 2586 }; 2587 }; 2588 2589 qspi: spi@88dc000 { 2590 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2591 reg = <0 0x088dc000 0 0x1000>; 2592 #address-cells = <1>; 2593 #size-cells = <0>; 2594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2596 <&gcc GCC_QSPI_CORE_CLK>; 2597 clock-names = "iface", "core"; 2598 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2599 &cnoc2 SLAVE_QSPI_0 0>; 2600 interconnect-names = "qspi-config"; 2601 power-domains = <&rpmhpd SC7280_CX>; 2602 operating-points-v2 = <&qspi_opp_table>; 2603 status = "disabled"; 2604 }; 2605 2606 dc_noc: interconnect@90e0000 { 2607 reg = <0 0x090e0000 0 0x5080>; 2608 compatible = "qcom,sc7280-dc-noc"; 2609 #interconnect-cells = <2>; 2610 qcom,bcm-voters = <&apps_bcm_voter>; 2611 }; 2612 2613 gem_noc: interconnect@9100000 { 2614 reg = <0 0x9100000 0 0xe2200>; 2615 compatible = "qcom,sc7280-gem-noc"; 2616 #interconnect-cells = <2>; 2617 qcom,bcm-voters = <&apps_bcm_voter>; 2618 }; 2619 2620 system-cache-controller@9200000 { 2621 compatible = "qcom,sc7280-llcc"; 2622 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2623 reg-names = "llcc_base", "llcc_broadcast_base"; 2624 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2625 }; 2626 2627 nsp_noc: interconnect@a0c0000 { 2628 reg = <0 0x0a0c0000 0 0x10000>; 2629 compatible = "qcom,sc7280-nsp-noc"; 2630 #interconnect-cells = <2>; 2631 qcom,bcm-voters = <&apps_bcm_voter>; 2632 }; 2633 2634 usb_1: usb@a6f8800 { 2635 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2636 reg = <0 0x0a6f8800 0 0x400>; 2637 status = "disabled"; 2638 #address-cells = <2>; 2639 #size-cells = <2>; 2640 ranges; 2641 dma-ranges; 2642 2643 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2644 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2645 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2646 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2647 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2648 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2649 "sleep"; 2650 2651 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2652 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2653 assigned-clock-rates = <19200000>, <200000000>; 2654 2655 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2656 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2657 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2658 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2659 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2660 "dm_hs_phy_irq", "ss_phy_irq"; 2661 2662 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2663 2664 resets = <&gcc GCC_USB30_PRIM_BCR>; 2665 2666 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2667 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2668 interconnect-names = "usb-ddr", "apps-usb"; 2669 2670 usb_1_dwc3: usb@a600000 { 2671 compatible = "snps,dwc3"; 2672 reg = <0 0x0a600000 0 0xe000>; 2673 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2674 iommus = <&apps_smmu 0xe0 0x0>; 2675 snps,dis_u2_susphy_quirk; 2676 snps,dis_enblslpm_quirk; 2677 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2678 phy-names = "usb2-phy", "usb3-phy"; 2679 maximum-speed = "super-speed"; 2680 }; 2681 }; 2682 2683 venus: video-codec@aa00000 { 2684 compatible = "qcom,sc7280-venus"; 2685 reg = <0 0x0aa00000 0 0xd0600>; 2686 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2689 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2690 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2691 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2692 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2693 clock-names = "core", "bus", "iface", 2694 "vcodec_core", "vcodec_bus"; 2695 2696 power-domains = <&videocc MVSC_GDSC>, 2697 <&videocc MVS0_GDSC>, 2698 <&rpmhpd SC7280_CX>; 2699 power-domain-names = "venus", "vcodec0", "cx"; 2700 operating-points-v2 = <&venus_opp_table>; 2701 2702 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2703 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2704 interconnect-names = "cpu-cfg", "video-mem"; 2705 2706 iommus = <&apps_smmu 0x2180 0x20>, 2707 <&apps_smmu 0x2184 0x20>; 2708 memory-region = <&video_mem>; 2709 2710 video-decoder { 2711 compatible = "venus-decoder"; 2712 }; 2713 2714 video-encoder { 2715 compatible = "venus-encoder"; 2716 }; 2717 2718 video-firmware { 2719 iommus = <&apps_smmu 0x21a2 0x0>; 2720 }; 2721 2722 venus_opp_table: venus-opp-table { 2723 compatible = "operating-points-v2"; 2724 2725 opp-133330000 { 2726 opp-hz = /bits/ 64 <133330000>; 2727 required-opps = <&rpmhpd_opp_low_svs>; 2728 }; 2729 2730 opp-240000000 { 2731 opp-hz = /bits/ 64 <240000000>; 2732 required-opps = <&rpmhpd_opp_svs>; 2733 }; 2734 2735 opp-335000000 { 2736 opp-hz = /bits/ 64 <335000000>; 2737 required-opps = <&rpmhpd_opp_svs_l1>; 2738 }; 2739 2740 opp-424000000 { 2741 opp-hz = /bits/ 64 <424000000>; 2742 required-opps = <&rpmhpd_opp_nom>; 2743 }; 2744 2745 opp-460000048 { 2746 opp-hz = /bits/ 64 <460000048>; 2747 required-opps = <&rpmhpd_opp_turbo>; 2748 }; 2749 }; 2750 2751 }; 2752 2753 videocc: clock-controller@aaf0000 { 2754 compatible = "qcom,sc7280-videocc"; 2755 reg = <0 0xaaf0000 0 0x10000>; 2756 clocks = <&rpmhcc RPMH_CXO_CLK>, 2757 <&rpmhcc RPMH_CXO_CLK_A>; 2758 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2759 #clock-cells = <1>; 2760 #reset-cells = <1>; 2761 #power-domain-cells = <1>; 2762 }; 2763 2764 dispcc: clock-controller@af00000 { 2765 compatible = "qcom,sc7280-dispcc"; 2766 reg = <0 0xaf00000 0 0x20000>; 2767 clocks = <&rpmhcc RPMH_CXO_CLK>, 2768 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2769 <&mdss_dsi_phy 0>, 2770 <&mdss_dsi_phy 1>, 2771 <0>, 2772 <0>, 2773 <0>, 2774 <0>; 2775 clock-names = "bi_tcxo", 2776 "gcc_disp_gpll0_clk", 2777 "dsi0_phy_pll_out_byteclk", 2778 "dsi0_phy_pll_out_dsiclk", 2779 "dp_phy_pll_link_clk", 2780 "dp_phy_pll_vco_div_clk", 2781 "edp_phy_pll_link_clk", 2782 "edp_phy_pll_vco_div_clk"; 2783 #clock-cells = <1>; 2784 #reset-cells = <1>; 2785 #power-domain-cells = <1>; 2786 }; 2787 2788 mdss: display-subsystem@ae00000 { 2789 compatible = "qcom,sc7280-mdss"; 2790 reg = <0 0x0ae00000 0 0x1000>; 2791 reg-names = "mdss"; 2792 2793 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 2794 2795 clocks = <&gcc GCC_DISP_AHB_CLK>, 2796 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2797 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2798 clock-names = "iface", 2799 "ahb", 2800 "core"; 2801 2802 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2803 assigned-clock-rates = <300000000>; 2804 2805 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2806 interrupt-controller; 2807 #interrupt-cells = <1>; 2808 2809 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2810 interconnect-names = "mdp0-mem"; 2811 2812 iommus = <&apps_smmu 0x900 0x402>; 2813 2814 #address-cells = <2>; 2815 #size-cells = <2>; 2816 ranges; 2817 2818 status = "disabled"; 2819 2820 mdss_mdp: display-controller@ae01000 { 2821 compatible = "qcom,sc7280-dpu"; 2822 reg = <0 0x0ae01000 0 0x8f030>, 2823 <0 0x0aeb0000 0 0x2008>; 2824 reg-names = "mdp", "vbif"; 2825 2826 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2827 <&gcc GCC_DISP_SF_AXI_CLK>, 2828 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2829 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2830 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2831 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2832 clock-names = "bus", 2833 "nrt_bus", 2834 "iface", 2835 "lut", 2836 "core", 2837 "vsync"; 2838 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2839 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2840 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2841 assigned-clock-rates = <300000000>, 2842 <19200000>, 2843 <19200000>; 2844 operating-points-v2 = <&mdp_opp_table>; 2845 power-domains = <&rpmhpd SC7280_CX>; 2846 2847 interrupt-parent = <&mdss>; 2848 interrupts = <0>; 2849 2850 status = "disabled"; 2851 2852 ports { 2853 #address-cells = <1>; 2854 #size-cells = <0>; 2855 2856 port@0 { 2857 reg = <0>; 2858 dpu_intf1_out: endpoint { 2859 remote-endpoint = <&dsi0_in>; 2860 }; 2861 }; 2862 }; 2863 2864 mdp_opp_table: opp-table { 2865 compatible = "operating-points-v2"; 2866 2867 opp-200000000 { 2868 opp-hz = /bits/ 64 <200000000>; 2869 required-opps = <&rpmhpd_opp_low_svs>; 2870 }; 2871 2872 opp-300000000 { 2873 opp-hz = /bits/ 64 <300000000>; 2874 required-opps = <&rpmhpd_opp_svs>; 2875 }; 2876 2877 opp-380000000 { 2878 opp-hz = /bits/ 64 <380000000>; 2879 required-opps = <&rpmhpd_opp_svs_l1>; 2880 }; 2881 2882 opp-506666667 { 2883 opp-hz = /bits/ 64 <506666667>; 2884 required-opps = <&rpmhpd_opp_nom>; 2885 }; 2886 }; 2887 }; 2888 2889 mdss_dsi: dsi@ae94000 { 2890 compatible = "qcom,mdss-dsi-ctrl"; 2891 reg = <0 0x0ae94000 0 0x400>; 2892 reg-names = "dsi_ctrl"; 2893 2894 interrupt-parent = <&mdss>; 2895 interrupts = <4>; 2896 2897 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2898 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2899 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2900 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2901 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2902 <&gcc GCC_DISP_HF_AXI_CLK>; 2903 clock-names = "byte", 2904 "byte_intf", 2905 "pixel", 2906 "core", 2907 "iface", 2908 "bus"; 2909 2910 operating-points-v2 = <&dsi_opp_table>; 2911 power-domains = <&rpmhpd SC7280_CX>; 2912 2913 phys = <&mdss_dsi_phy>; 2914 phy-names = "dsi"; 2915 2916 #address-cells = <1>; 2917 #size-cells = <0>; 2918 2919 status = "disabled"; 2920 2921 ports { 2922 #address-cells = <1>; 2923 #size-cells = <0>; 2924 2925 port@0 { 2926 reg = <0>; 2927 dsi0_in: endpoint { 2928 remote-endpoint = <&dpu_intf1_out>; 2929 }; 2930 }; 2931 2932 port@1 { 2933 reg = <1>; 2934 dsi0_out: endpoint { 2935 }; 2936 }; 2937 }; 2938 2939 dsi_opp_table: opp-table { 2940 compatible = "operating-points-v2"; 2941 2942 opp-187500000 { 2943 opp-hz = /bits/ 64 <187500000>; 2944 required-opps = <&rpmhpd_opp_low_svs>; 2945 }; 2946 2947 opp-300000000 { 2948 opp-hz = /bits/ 64 <300000000>; 2949 required-opps = <&rpmhpd_opp_svs>; 2950 }; 2951 2952 opp-358000000 { 2953 opp-hz = /bits/ 64 <358000000>; 2954 required-opps = <&rpmhpd_opp_svs_l1>; 2955 }; 2956 }; 2957 }; 2958 2959 mdss_dsi_phy: phy@ae94400 { 2960 compatible = "qcom,sc7280-dsi-phy-7nm"; 2961 reg = <0 0x0ae94400 0 0x200>, 2962 <0 0x0ae94600 0 0x280>, 2963 <0 0x0ae94900 0 0x280>; 2964 reg-names = "dsi_phy", 2965 "dsi_phy_lane", 2966 "dsi_pll"; 2967 2968 #clock-cells = <1>; 2969 #phy-cells = <0>; 2970 2971 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2972 <&rpmhcc RPMH_CXO_CLK>; 2973 clock-names = "iface", "ref"; 2974 2975 status = "disabled"; 2976 }; 2977 }; 2978 2979 pdc: interrupt-controller@b220000 { 2980 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2981 reg = <0 0x0b220000 0 0x30000>; 2982 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2983 <55 306 4>, <59 312 3>, <62 374 2>, 2984 <64 434 2>, <66 438 3>, <69 86 1>, 2985 <70 520 54>, <124 609 31>, <155 63 1>, 2986 <156 716 12>; 2987 #interrupt-cells = <2>; 2988 interrupt-parent = <&intc>; 2989 interrupt-controller; 2990 }; 2991 2992 pdc_reset: reset-controller@b5e0000 { 2993 compatible = "qcom,sc7280-pdc-global"; 2994 reg = <0 0x0b5e0000 0 0x20000>; 2995 #reset-cells = <1>; 2996 }; 2997 2998 tsens0: thermal-sensor@c263000 { 2999 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3000 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3001 <0 0x0c222000 0 0x1ff>; /* SROT */ 3002 #qcom,sensors = <15>; 3003 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3004 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3005 interrupt-names = "uplow","critical"; 3006 #thermal-sensor-cells = <1>; 3007 }; 3008 3009 tsens1: thermal-sensor@c265000 { 3010 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3011 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3012 <0 0x0c223000 0 0x1ff>; /* SROT */ 3013 #qcom,sensors = <12>; 3014 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3016 interrupt-names = "uplow","critical"; 3017 #thermal-sensor-cells = <1>; 3018 }; 3019 3020 aoss_reset: reset-controller@c2a0000 { 3021 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3022 reg = <0 0x0c2a0000 0 0x31000>; 3023 #reset-cells = <1>; 3024 }; 3025 3026 aoss_qmp: power-controller@c300000 { 3027 compatible = "qcom,sc7280-aoss-qmp"; 3028 reg = <0 0x0c300000 0 0x400>; 3029 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3030 IPCC_MPROC_SIGNAL_GLINK_QMP 3031 IRQ_TYPE_EDGE_RISING>; 3032 mboxes = <&ipcc IPCC_CLIENT_AOP 3033 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3034 3035 #clock-cells = <0>; 3036 }; 3037 3038 sram@c3f0000 { 3039 compatible = "qcom,rpmh-stats"; 3040 reg = <0 0x0c3f0000 0 0x400>; 3041 }; 3042 3043 spmi_bus: spmi@c440000 { 3044 compatible = "qcom,spmi-pmic-arb"; 3045 reg = <0 0x0c440000 0 0x1100>, 3046 <0 0x0c600000 0 0x2000000>, 3047 <0 0x0e600000 0 0x100000>, 3048 <0 0x0e700000 0 0xa0000>, 3049 <0 0x0c40a000 0 0x26000>; 3050 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3051 interrupt-names = "periph_irq"; 3052 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3053 qcom,ee = <0>; 3054 qcom,channel = <0>; 3055 #address-cells = <1>; 3056 #size-cells = <1>; 3057 interrupt-controller; 3058 #interrupt-cells = <4>; 3059 }; 3060 3061 tlmm: pinctrl@f100000 { 3062 compatible = "qcom,sc7280-pinctrl"; 3063 reg = <0 0x0f100000 0 0x300000>; 3064 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3065 gpio-controller; 3066 #gpio-cells = <2>; 3067 interrupt-controller; 3068 #interrupt-cells = <2>; 3069 gpio-ranges = <&tlmm 0 0 175>; 3070 wakeup-parent = <&pdc>; 3071 3072 pcie1_clkreq_n: pcie1-clkreq-n { 3073 pins = "gpio79"; 3074 function = "pcie1_clkreqn"; 3075 drive-strength = <2>; 3076 bias-pull-up; 3077 }; 3078 3079 qspi_clk: qspi-clk { 3080 pins = "gpio14"; 3081 function = "qspi_clk"; 3082 }; 3083 3084 qspi_cs0: qspi-cs0 { 3085 pins = "gpio15"; 3086 function = "qspi_cs"; 3087 }; 3088 3089 qspi_cs1: qspi-cs1 { 3090 pins = "gpio19"; 3091 function = "qspi_cs"; 3092 }; 3093 3094 qspi_data01: qspi-data01 { 3095 pins = "gpio12", "gpio13"; 3096 function = "qspi_data"; 3097 }; 3098 3099 qspi_data12: qspi-data12 { 3100 pins = "gpio16", "gpio17"; 3101 function = "qspi_data"; 3102 }; 3103 3104 qup_i2c0_data_clk: qup-i2c0-data-clk { 3105 pins = "gpio0", "gpio1"; 3106 function = "qup00"; 3107 }; 3108 3109 qup_i2c1_data_clk: qup-i2c1-data-clk { 3110 pins = "gpio4", "gpio5"; 3111 function = "qup01"; 3112 }; 3113 3114 qup_i2c2_data_clk: qup-i2c2-data-clk { 3115 pins = "gpio8", "gpio9"; 3116 function = "qup02"; 3117 }; 3118 3119 qup_i2c3_data_clk: qup-i2c3-data-clk { 3120 pins = "gpio12", "gpio13"; 3121 function = "qup03"; 3122 }; 3123 3124 qup_i2c4_data_clk: qup-i2c4-data-clk { 3125 pins = "gpio16", "gpio17"; 3126 function = "qup04"; 3127 }; 3128 3129 qup_i2c5_data_clk: qup-i2c5-data-clk { 3130 pins = "gpio20", "gpio21"; 3131 function = "qup05"; 3132 }; 3133 3134 qup_i2c6_data_clk: qup-i2c6-data-clk { 3135 pins = "gpio24", "gpio25"; 3136 function = "qup06"; 3137 }; 3138 3139 qup_i2c7_data_clk: qup-i2c7-data-clk { 3140 pins = "gpio28", "gpio29"; 3141 function = "qup07"; 3142 }; 3143 3144 qup_i2c8_data_clk: qup-i2c8-data-clk { 3145 pins = "gpio32", "gpio33"; 3146 function = "qup10"; 3147 }; 3148 3149 qup_i2c9_data_clk: qup-i2c9-data-clk { 3150 pins = "gpio36", "gpio37"; 3151 function = "qup11"; 3152 }; 3153 3154 qup_i2c10_data_clk: qup-i2c10-data-clk { 3155 pins = "gpio40", "gpio41"; 3156 function = "qup12"; 3157 }; 3158 3159 qup_i2c11_data_clk: qup-i2c11-data-clk { 3160 pins = "gpio44", "gpio45"; 3161 function = "qup13"; 3162 }; 3163 3164 qup_i2c12_data_clk: qup-i2c12-data-clk { 3165 pins = "gpio48", "gpio49"; 3166 function = "qup14"; 3167 }; 3168 3169 qup_i2c13_data_clk: qup-i2c13-data-clk { 3170 pins = "gpio52", "gpio53"; 3171 function = "qup15"; 3172 }; 3173 3174 qup_i2c14_data_clk: qup-i2c14-data-clk { 3175 pins = "gpio56", "gpio57"; 3176 function = "qup16"; 3177 }; 3178 3179 qup_i2c15_data_clk: qup-i2c15-data-clk { 3180 pins = "gpio60", "gpio61"; 3181 function = "qup17"; 3182 }; 3183 3184 qup_spi0_data_clk: qup-spi0-data-clk { 3185 pins = "gpio0", "gpio1", "gpio2"; 3186 function = "qup00"; 3187 }; 3188 3189 qup_spi0_cs: qup-spi0-cs { 3190 pins = "gpio3"; 3191 function = "qup00"; 3192 }; 3193 3194 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3195 pins = "gpio3"; 3196 function = "gpio"; 3197 }; 3198 3199 qup_spi1_data_clk: qup-spi1-data-clk { 3200 pins = "gpio4", "gpio5", "gpio6"; 3201 function = "qup01"; 3202 }; 3203 3204 qup_spi1_cs: qup-spi1-cs { 3205 pins = "gpio7"; 3206 function = "qup01"; 3207 }; 3208 3209 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3210 pins = "gpio7"; 3211 function = "gpio"; 3212 }; 3213 3214 qup_spi2_data_clk: qup-spi2-data-clk { 3215 pins = "gpio8", "gpio9", "gpio10"; 3216 function = "qup02"; 3217 }; 3218 3219 qup_spi2_cs: qup-spi2-cs { 3220 pins = "gpio11"; 3221 function = "qup02"; 3222 }; 3223 3224 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3225 pins = "gpio11"; 3226 function = "gpio"; 3227 }; 3228 3229 qup_spi3_data_clk: qup-spi3-data-clk { 3230 pins = "gpio12", "gpio13", "gpio14"; 3231 function = "qup03"; 3232 }; 3233 3234 qup_spi3_cs: qup-spi3-cs { 3235 pins = "gpio15"; 3236 function = "qup03"; 3237 }; 3238 3239 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3240 pins = "gpio15"; 3241 function = "gpio"; 3242 }; 3243 3244 qup_spi4_data_clk: qup-spi4-data-clk { 3245 pins = "gpio16", "gpio17", "gpio18"; 3246 function = "qup04"; 3247 }; 3248 3249 qup_spi4_cs: qup-spi4-cs { 3250 pins = "gpio19"; 3251 function = "qup04"; 3252 }; 3253 3254 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3255 pins = "gpio19"; 3256 function = "gpio"; 3257 }; 3258 3259 qup_spi5_data_clk: qup-spi5-data-clk { 3260 pins = "gpio20", "gpio21", "gpio22"; 3261 function = "qup05"; 3262 }; 3263 3264 qup_spi5_cs: qup-spi5-cs { 3265 pins = "gpio23"; 3266 function = "qup05"; 3267 }; 3268 3269 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3270 pins = "gpio23"; 3271 function = "gpio"; 3272 }; 3273 3274 qup_spi6_data_clk: qup-spi6-data-clk { 3275 pins = "gpio24", "gpio25", "gpio26"; 3276 function = "qup06"; 3277 }; 3278 3279 qup_spi6_cs: qup-spi6-cs { 3280 pins = "gpio27"; 3281 function = "qup06"; 3282 }; 3283 3284 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3285 pins = "gpio27"; 3286 function = "gpio"; 3287 }; 3288 3289 qup_spi7_data_clk: qup-spi7-data-clk { 3290 pins = "gpio28", "gpio29", "gpio30"; 3291 function = "qup07"; 3292 }; 3293 3294 qup_spi7_cs: qup-spi7-cs { 3295 pins = "gpio31"; 3296 function = "qup07"; 3297 }; 3298 3299 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3300 pins = "gpio31"; 3301 function = "gpio"; 3302 }; 3303 3304 qup_spi8_data_clk: qup-spi8-data-clk { 3305 pins = "gpio32", "gpio33", "gpio34"; 3306 function = "qup10"; 3307 }; 3308 3309 qup_spi8_cs: qup-spi8-cs { 3310 pins = "gpio35"; 3311 function = "qup10"; 3312 }; 3313 3314 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3315 pins = "gpio35"; 3316 function = "gpio"; 3317 }; 3318 3319 qup_spi9_data_clk: qup-spi9-data-clk { 3320 pins = "gpio36", "gpio37", "gpio38"; 3321 function = "qup11"; 3322 }; 3323 3324 qup_spi9_cs: qup-spi9-cs { 3325 pins = "gpio39"; 3326 function = "qup11"; 3327 }; 3328 3329 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3330 pins = "gpio39"; 3331 function = "gpio"; 3332 }; 3333 3334 qup_spi10_data_clk: qup-spi10-data-clk { 3335 pins = "gpio40", "gpio41", "gpio42"; 3336 function = "qup12"; 3337 }; 3338 3339 qup_spi10_cs: qup-spi10-cs { 3340 pins = "gpio43"; 3341 function = "qup12"; 3342 }; 3343 3344 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3345 pins = "gpio43"; 3346 function = "gpio"; 3347 }; 3348 3349 qup_spi11_data_clk: qup-spi11-data-clk { 3350 pins = "gpio44", "gpio45", "gpio46"; 3351 function = "qup13"; 3352 }; 3353 3354 qup_spi11_cs: qup-spi11-cs { 3355 pins = "gpio47"; 3356 function = "qup13"; 3357 }; 3358 3359 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3360 pins = "gpio47"; 3361 function = "gpio"; 3362 }; 3363 3364 qup_spi12_data_clk: qup-spi12-data-clk { 3365 pins = "gpio48", "gpio49", "gpio50"; 3366 function = "qup14"; 3367 }; 3368 3369 qup_spi12_cs: qup-spi12-cs { 3370 pins = "gpio51"; 3371 function = "qup14"; 3372 }; 3373 3374 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3375 pins = "gpio51"; 3376 function = "gpio"; 3377 }; 3378 3379 qup_spi13_data_clk: qup-spi13-data-clk { 3380 pins = "gpio52", "gpio53", "gpio54"; 3381 function = "qup15"; 3382 }; 3383 3384 qup_spi13_cs: qup-spi13-cs { 3385 pins = "gpio55"; 3386 function = "qup15"; 3387 }; 3388 3389 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3390 pins = "gpio55"; 3391 function = "gpio"; 3392 }; 3393 3394 qup_spi14_data_clk: qup-spi14-data-clk { 3395 pins = "gpio56", "gpio57", "gpio58"; 3396 function = "qup16"; 3397 }; 3398 3399 qup_spi14_cs: qup-spi14-cs { 3400 pins = "gpio59"; 3401 function = "qup16"; 3402 }; 3403 3404 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3405 pins = "gpio59"; 3406 function = "gpio"; 3407 }; 3408 3409 qup_spi15_data_clk: qup-spi15-data-clk { 3410 pins = "gpio60", "gpio61", "gpio62"; 3411 function = "qup17"; 3412 }; 3413 3414 qup_spi15_cs: qup-spi15-cs { 3415 pins = "gpio63"; 3416 function = "qup17"; 3417 }; 3418 3419 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3420 pins = "gpio63"; 3421 function = "gpio"; 3422 }; 3423 3424 qup_uart0_cts: qup-uart0-cts { 3425 pins = "gpio0"; 3426 function = "qup00"; 3427 }; 3428 3429 qup_uart0_rts: qup-uart0-rts { 3430 pins = "gpio1"; 3431 function = "qup00"; 3432 }; 3433 3434 qup_uart0_tx: qup-uart0-tx { 3435 pins = "gpio2"; 3436 function = "qup00"; 3437 }; 3438 3439 qup_uart0_rx: qup-uart0-rx { 3440 pins = "gpio3"; 3441 function = "qup00"; 3442 }; 3443 3444 qup_uart1_cts: qup-uart1-cts { 3445 pins = "gpio4"; 3446 function = "qup01"; 3447 }; 3448 3449 qup_uart1_rts: qup-uart1-rts { 3450 pins = "gpio5"; 3451 function = "qup01"; 3452 }; 3453 3454 qup_uart1_tx: qup-uart1-tx { 3455 pins = "gpio6"; 3456 function = "qup01"; 3457 }; 3458 3459 qup_uart1_rx: qup-uart1-rx { 3460 pins = "gpio7"; 3461 function = "qup01"; 3462 }; 3463 3464 qup_uart2_cts: qup-uart2-cts { 3465 pins = "gpio8"; 3466 function = "qup02"; 3467 }; 3468 3469 qup_uart2_rts: qup-uart2-rts { 3470 pins = "gpio9"; 3471 function = "qup02"; 3472 }; 3473 3474 qup_uart2_tx: qup-uart2-tx { 3475 pins = "gpio10"; 3476 function = "qup02"; 3477 }; 3478 3479 qup_uart2_rx: qup-uart2-rx { 3480 pins = "gpio11"; 3481 function = "qup02"; 3482 }; 3483 3484 qup_uart3_cts: qup-uart3-cts { 3485 pins = "gpio12"; 3486 function = "qup03"; 3487 }; 3488 3489 qup_uart3_rts: qup-uart3-rts { 3490 pins = "gpio13"; 3491 function = "qup03"; 3492 }; 3493 3494 qup_uart3_tx: qup-uart3-tx { 3495 pins = "gpio14"; 3496 function = "qup03"; 3497 }; 3498 3499 qup_uart3_rx: qup-uart3-rx { 3500 pins = "gpio15"; 3501 function = "qup03"; 3502 }; 3503 3504 qup_uart4_cts: qup-uart4-cts { 3505 pins = "gpio16"; 3506 function = "qup04"; 3507 }; 3508 3509 qup_uart4_rts: qup-uart4-rts { 3510 pins = "gpio17"; 3511 function = "qup04"; 3512 }; 3513 3514 qup_uart4_tx: qup-uart4-tx { 3515 pins = "gpio18"; 3516 function = "qup04"; 3517 }; 3518 3519 qup_uart4_rx: qup-uart4-rx { 3520 pins = "gpio19"; 3521 function = "qup04"; 3522 }; 3523 3524 qup_uart5_cts: qup-uart5-cts { 3525 pins = "gpio20"; 3526 function = "qup05"; 3527 }; 3528 3529 qup_uart5_rts: qup-uart5-rts { 3530 pins = "gpio21"; 3531 function = "qup05"; 3532 }; 3533 3534 qup_uart5_tx: qup-uart5-tx { 3535 pins = "gpio22"; 3536 function = "qup05"; 3537 }; 3538 3539 qup_uart5_rx: qup-uart5-rx { 3540 pins = "gpio23"; 3541 function = "qup05"; 3542 }; 3543 3544 qup_uart6_cts: qup-uart6-cts { 3545 pins = "gpio24"; 3546 function = "qup06"; 3547 }; 3548 3549 qup_uart6_rts: qup-uart6-rts { 3550 pins = "gpio25"; 3551 function = "qup06"; 3552 }; 3553 3554 qup_uart6_tx: qup-uart6-tx { 3555 pins = "gpio26"; 3556 function = "qup06"; 3557 }; 3558 3559 qup_uart6_rx: qup-uart6-rx { 3560 pins = "gpio27"; 3561 function = "qup06"; 3562 }; 3563 3564 qup_uart7_cts: qup-uart7-cts { 3565 pins = "gpio28"; 3566 function = "qup07"; 3567 }; 3568 3569 qup_uart7_rts: qup-uart7-rts { 3570 pins = "gpio29"; 3571 function = "qup07"; 3572 }; 3573 3574 qup_uart7_tx: qup-uart7-tx { 3575 pins = "gpio30"; 3576 function = "qup07"; 3577 }; 3578 3579 qup_uart7_rx: qup-uart7-rx { 3580 pins = "gpio31"; 3581 function = "qup07"; 3582 }; 3583 3584 sdc1_on: sdc1-on { 3585 clk { 3586 pins = "sdc1_clk"; 3587 }; 3588 3589 cmd { 3590 pins = "sdc1_cmd"; 3591 }; 3592 3593 data { 3594 pins = "sdc1_data"; 3595 }; 3596 3597 rclk { 3598 pins = "sdc1_rclk"; 3599 }; 3600 }; 3601 3602 sdc1_off: sdc1-off { 3603 clk { 3604 pins = "sdc1_clk"; 3605 drive-strength = <2>; 3606 bias-bus-hold; 3607 }; 3608 3609 cmd { 3610 pins = "sdc1_cmd"; 3611 drive-strength = <2>; 3612 bias-bus-hold; 3613 }; 3614 3615 data { 3616 pins = "sdc1_data"; 3617 drive-strength = <2>; 3618 bias-bus-hold; 3619 }; 3620 3621 rclk { 3622 pins = "sdc1_rclk"; 3623 bias-bus-hold; 3624 }; 3625 }; 3626 3627 sdc2_on: sdc2-on { 3628 clk { 3629 pins = "sdc2_clk"; 3630 }; 3631 3632 cmd { 3633 pins = "sdc2_cmd"; 3634 }; 3635 3636 data { 3637 pins = "sdc2_data"; 3638 }; 3639 }; 3640 3641 sdc2_off: sdc2-off { 3642 clk { 3643 pins = "sdc2_clk"; 3644 drive-strength = <2>; 3645 bias-bus-hold; 3646 }; 3647 3648 cmd { 3649 pins ="sdc2_cmd"; 3650 drive-strength = <2>; 3651 bias-bus-hold; 3652 }; 3653 3654 data { 3655 pins ="sdc2_data"; 3656 drive-strength = <2>; 3657 bias-bus-hold; 3658 }; 3659 }; 3660 3661 qup_uart8_cts: qup-uart8-cts { 3662 pins = "gpio32"; 3663 function = "qup10"; 3664 }; 3665 3666 qup_uart8_rts: qup-uart8-rts { 3667 pins = "gpio33"; 3668 function = "qup10"; 3669 }; 3670 3671 qup_uart8_tx: qup-uart8-tx { 3672 pins = "gpio34"; 3673 function = "qup10"; 3674 }; 3675 3676 qup_uart8_rx: qup-uart8-rx { 3677 pins = "gpio35"; 3678 function = "qup10"; 3679 }; 3680 3681 qup_uart9_cts: qup-uart9-cts { 3682 pins = "gpio36"; 3683 function = "qup11"; 3684 }; 3685 3686 qup_uart9_rts: qup-uart9-rts { 3687 pins = "gpio37"; 3688 function = "qup11"; 3689 }; 3690 3691 qup_uart9_tx: qup-uart9-tx { 3692 pins = "gpio38"; 3693 function = "qup11"; 3694 }; 3695 3696 qup_uart9_rx: qup-uart9-rx { 3697 pins = "gpio39"; 3698 function = "qup11"; 3699 }; 3700 3701 qup_uart10_cts: qup-uart10-cts { 3702 pins = "gpio40"; 3703 function = "qup12"; 3704 }; 3705 3706 qup_uart10_rts: qup-uart10-rts { 3707 pins = "gpio41"; 3708 function = "qup12"; 3709 }; 3710 3711 qup_uart10_tx: qup-uart10-tx { 3712 pins = "gpio42"; 3713 function = "qup12"; 3714 }; 3715 3716 qup_uart10_rx: qup-uart10-rx { 3717 pins = "gpio43"; 3718 function = "qup12"; 3719 }; 3720 3721 qup_uart11_cts: qup-uart11-cts { 3722 pins = "gpio44"; 3723 function = "qup13"; 3724 }; 3725 3726 qup_uart11_rts: qup-uart11-rts { 3727 pins = "gpio45"; 3728 function = "qup13"; 3729 }; 3730 3731 qup_uart11_tx: qup-uart11-tx { 3732 pins = "gpio46"; 3733 function = "qup13"; 3734 }; 3735 3736 qup_uart11_rx: qup-uart11-rx { 3737 pins = "gpio47"; 3738 function = "qup13"; 3739 }; 3740 3741 qup_uart12_cts: qup-uart12-cts { 3742 pins = "gpio48"; 3743 function = "qup14"; 3744 }; 3745 3746 qup_uart12_rts: qup-uart12-rts { 3747 pins = "gpio49"; 3748 function = "qup14"; 3749 }; 3750 3751 qup_uart12_tx: qup-uart12-tx { 3752 pins = "gpio50"; 3753 function = "qup14"; 3754 }; 3755 3756 qup_uart12_rx: qup-uart12-rx { 3757 pins = "gpio51"; 3758 function = "qup14"; 3759 }; 3760 3761 qup_uart13_cts: qup-uart13-cts { 3762 pins = "gpio52"; 3763 function = "qup15"; 3764 }; 3765 3766 qup_uart13_rts: qup-uart13-rts { 3767 pins = "gpio53"; 3768 function = "qup15"; 3769 }; 3770 3771 qup_uart13_tx: qup-uart13-tx { 3772 pins = "gpio54"; 3773 function = "qup15"; 3774 }; 3775 3776 qup_uart13_rx: qup-uart13-rx { 3777 pins = "gpio55"; 3778 function = "qup15"; 3779 }; 3780 3781 qup_uart14_cts: qup-uart14-cts { 3782 pins = "gpio56"; 3783 function = "qup16"; 3784 }; 3785 3786 qup_uart14_rts: qup-uart14-rts { 3787 pins = "gpio57"; 3788 function = "qup16"; 3789 }; 3790 3791 qup_uart14_tx: qup-uart14-tx { 3792 pins = "gpio58"; 3793 function = "qup16"; 3794 }; 3795 3796 qup_uart14_rx: qup-uart14-rx { 3797 pins = "gpio59"; 3798 function = "qup16"; 3799 }; 3800 3801 qup_uart15_cts: qup-uart15-cts { 3802 pins = "gpio60"; 3803 function = "qup17"; 3804 }; 3805 3806 qup_uart15_rts: qup-uart15-rts { 3807 pins = "gpio61"; 3808 function = "qup17"; 3809 }; 3810 3811 qup_uart15_tx: qup-uart15-tx { 3812 pins = "gpio62"; 3813 function = "qup17"; 3814 }; 3815 3816 qup_uart15_rx: qup-uart15-rx { 3817 pins = "gpio63"; 3818 function = "qup17"; 3819 }; 3820 }; 3821 3822 imem@146a5000 { 3823 compatible = "qcom,sc7280-imem", "syscon"; 3824 reg = <0 0x146a5000 0 0x6000>; 3825 3826 #address-cells = <1>; 3827 #size-cells = <1>; 3828 3829 ranges = <0 0 0x146a5000 0x6000>; 3830 3831 pil-reloc@594c { 3832 compatible = "qcom,pil-reloc-info"; 3833 reg = <0x594c 0xc8>; 3834 }; 3835 }; 3836 3837 apps_smmu: iommu@15000000 { 3838 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3839 reg = <0 0x15000000 0 0x100000>; 3840 #iommu-cells = <2>; 3841 #global-interrupts = <1>; 3842 dma-coherent; 3843 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3924 }; 3925 3926 intc: interrupt-controller@17a00000 { 3927 compatible = "arm,gic-v3"; 3928 #address-cells = <2>; 3929 #size-cells = <2>; 3930 ranges; 3931 #interrupt-cells = <3>; 3932 interrupt-controller; 3933 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3934 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3935 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3936 3937 gic-its@17a40000 { 3938 compatible = "arm,gic-v3-its"; 3939 msi-controller; 3940 #msi-cells = <1>; 3941 reg = <0 0x17a40000 0 0x20000>; 3942 status = "disabled"; 3943 }; 3944 }; 3945 3946 watchdog@17c10000 { 3947 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3948 reg = <0 0x17c10000 0 0x1000>; 3949 clocks = <&sleep_clk>; 3950 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3951 }; 3952 3953 timer@17c20000 { 3954 #address-cells = <2>; 3955 #size-cells = <2>; 3956 ranges; 3957 compatible = "arm,armv7-timer-mem"; 3958 reg = <0 0x17c20000 0 0x1000>; 3959 3960 frame@17c21000 { 3961 frame-number = <0>; 3962 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3964 reg = <0 0x17c21000 0 0x1000>, 3965 <0 0x17c22000 0 0x1000>; 3966 }; 3967 3968 frame@17c23000 { 3969 frame-number = <1>; 3970 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3971 reg = <0 0x17c23000 0 0x1000>; 3972 status = "disabled"; 3973 }; 3974 3975 frame@17c25000 { 3976 frame-number = <2>; 3977 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3978 reg = <0 0x17c25000 0 0x1000>; 3979 status = "disabled"; 3980 }; 3981 3982 frame@17c27000 { 3983 frame-number = <3>; 3984 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3985 reg = <0 0x17c27000 0 0x1000>; 3986 status = "disabled"; 3987 }; 3988 3989 frame@17c29000 { 3990 frame-number = <4>; 3991 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3992 reg = <0 0x17c29000 0 0x1000>; 3993 status = "disabled"; 3994 }; 3995 3996 frame@17c2b000 { 3997 frame-number = <5>; 3998 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3999 reg = <0 0x17c2b000 0 0x1000>; 4000 status = "disabled"; 4001 }; 4002 4003 frame@17c2d000 { 4004 frame-number = <6>; 4005 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4006 reg = <0 0x17c2d000 0 0x1000>; 4007 status = "disabled"; 4008 }; 4009 }; 4010 4011 apps_rsc: rsc@18200000 { 4012 compatible = "qcom,rpmh-rsc"; 4013 reg = <0 0x18200000 0 0x10000>, 4014 <0 0x18210000 0 0x10000>, 4015 <0 0x18220000 0 0x10000>; 4016 reg-names = "drv-0", "drv-1", "drv-2"; 4017 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4020 qcom,tcs-offset = <0xd00>; 4021 qcom,drv-id = <2>; 4022 qcom,tcs-config = <ACTIVE_TCS 2>, 4023 <SLEEP_TCS 3>, 4024 <WAKE_TCS 3>, 4025 <CONTROL_TCS 1>; 4026 4027 apps_bcm_voter: bcm-voter { 4028 compatible = "qcom,bcm-voter"; 4029 }; 4030 4031 rpmhpd: power-controller { 4032 compatible = "qcom,sc7280-rpmhpd"; 4033 #power-domain-cells = <1>; 4034 operating-points-v2 = <&rpmhpd_opp_table>; 4035 4036 rpmhpd_opp_table: opp-table { 4037 compatible = "operating-points-v2"; 4038 4039 rpmhpd_opp_ret: opp1 { 4040 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4041 }; 4042 4043 rpmhpd_opp_low_svs: opp2 { 4044 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4045 }; 4046 4047 rpmhpd_opp_svs: opp3 { 4048 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4049 }; 4050 4051 rpmhpd_opp_svs_l1: opp4 { 4052 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4053 }; 4054 4055 rpmhpd_opp_svs_l2: opp5 { 4056 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4057 }; 4058 4059 rpmhpd_opp_nom: opp6 { 4060 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4061 }; 4062 4063 rpmhpd_opp_nom_l1: opp7 { 4064 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4065 }; 4066 4067 rpmhpd_opp_turbo: opp8 { 4068 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4069 }; 4070 4071 rpmhpd_opp_turbo_l1: opp9 { 4072 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4073 }; 4074 }; 4075 }; 4076 4077 rpmhcc: clock-controller { 4078 compatible = "qcom,sc7280-rpmh-clk"; 4079 clocks = <&xo_board>; 4080 clock-names = "xo"; 4081 #clock-cells = <1>; 4082 }; 4083 }; 4084 4085 cpufreq_hw: cpufreq@18591000 { 4086 compatible = "qcom,cpufreq-epss"; 4087 reg = <0 0x18591000 0 0x1000>, 4088 <0 0x18592000 0 0x1000>, 4089 <0 0x18593000 0 0x1000>; 4090 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4091 clock-names = "xo", "alternate"; 4092 #freq-domain-cells = <1>; 4093 }; 4094 }; 4095 4096 thermal_zones: thermal-zones { 4097 cpu0-thermal { 4098 polling-delay-passive = <250>; 4099 polling-delay = <0>; 4100 4101 thermal-sensors = <&tsens0 1>; 4102 4103 trips { 4104 cpu0_alert0: trip-point0 { 4105 temperature = <90000>; 4106 hysteresis = <2000>; 4107 type = "passive"; 4108 }; 4109 4110 cpu0_alert1: trip-point1 { 4111 temperature = <95000>; 4112 hysteresis = <2000>; 4113 type = "passive"; 4114 }; 4115 4116 cpu0_crit: cpu-crit { 4117 temperature = <110000>; 4118 hysteresis = <0>; 4119 type = "critical"; 4120 }; 4121 }; 4122 4123 cooling-maps { 4124 map0 { 4125 trip = <&cpu0_alert0>; 4126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4130 }; 4131 map1 { 4132 trip = <&cpu0_alert1>; 4133 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4137 }; 4138 }; 4139 }; 4140 4141 cpu1-thermal { 4142 polling-delay-passive = <250>; 4143 polling-delay = <0>; 4144 4145 thermal-sensors = <&tsens0 2>; 4146 4147 trips { 4148 cpu1_alert0: trip-point0 { 4149 temperature = <90000>; 4150 hysteresis = <2000>; 4151 type = "passive"; 4152 }; 4153 4154 cpu1_alert1: trip-point1 { 4155 temperature = <95000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 cpu1_crit: cpu-crit { 4161 temperature = <110000>; 4162 hysteresis = <0>; 4163 type = "critical"; 4164 }; 4165 }; 4166 4167 cooling-maps { 4168 map0 { 4169 trip = <&cpu1_alert0>; 4170 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4172 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4173 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4174 }; 4175 map1 { 4176 trip = <&cpu1_alert1>; 4177 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4178 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4179 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4181 }; 4182 }; 4183 }; 4184 4185 cpu2-thermal { 4186 polling-delay-passive = <250>; 4187 polling-delay = <0>; 4188 4189 thermal-sensors = <&tsens0 3>; 4190 4191 trips { 4192 cpu2_alert0: trip-point0 { 4193 temperature = <90000>; 4194 hysteresis = <2000>; 4195 type = "passive"; 4196 }; 4197 4198 cpu2_alert1: trip-point1 { 4199 temperature = <95000>; 4200 hysteresis = <2000>; 4201 type = "passive"; 4202 }; 4203 4204 cpu2_crit: cpu-crit { 4205 temperature = <110000>; 4206 hysteresis = <0>; 4207 type = "critical"; 4208 }; 4209 }; 4210 4211 cooling-maps { 4212 map0 { 4213 trip = <&cpu2_alert0>; 4214 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4215 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4216 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4217 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4218 }; 4219 map1 { 4220 trip = <&cpu2_alert1>; 4221 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4223 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4224 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4225 }; 4226 }; 4227 }; 4228 4229 cpu3-thermal { 4230 polling-delay-passive = <250>; 4231 polling-delay = <0>; 4232 4233 thermal-sensors = <&tsens0 4>; 4234 4235 trips { 4236 cpu3_alert0: trip-point0 { 4237 temperature = <90000>; 4238 hysteresis = <2000>; 4239 type = "passive"; 4240 }; 4241 4242 cpu3_alert1: trip-point1 { 4243 temperature = <95000>; 4244 hysteresis = <2000>; 4245 type = "passive"; 4246 }; 4247 4248 cpu3_crit: cpu-crit { 4249 temperature = <110000>; 4250 hysteresis = <0>; 4251 type = "critical"; 4252 }; 4253 }; 4254 4255 cooling-maps { 4256 map0 { 4257 trip = <&cpu3_alert0>; 4258 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4259 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4260 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4261 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4262 }; 4263 map1 { 4264 trip = <&cpu3_alert1>; 4265 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4266 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4267 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4268 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4269 }; 4270 }; 4271 }; 4272 4273 cpu4-thermal { 4274 polling-delay-passive = <250>; 4275 polling-delay = <0>; 4276 4277 thermal-sensors = <&tsens0 7>; 4278 4279 trips { 4280 cpu4_alert0: trip-point0 { 4281 temperature = <90000>; 4282 hysteresis = <2000>; 4283 type = "passive"; 4284 }; 4285 4286 cpu4_alert1: trip-point1 { 4287 temperature = <95000>; 4288 hysteresis = <2000>; 4289 type = "passive"; 4290 }; 4291 4292 cpu4_crit: cpu-crit { 4293 temperature = <110000>; 4294 hysteresis = <0>; 4295 type = "critical"; 4296 }; 4297 }; 4298 4299 cooling-maps { 4300 map0 { 4301 trip = <&cpu4_alert0>; 4302 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4303 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4304 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4305 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4306 }; 4307 map1 { 4308 trip = <&cpu4_alert1>; 4309 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4310 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4311 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4312 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4313 }; 4314 }; 4315 }; 4316 4317 cpu5-thermal { 4318 polling-delay-passive = <250>; 4319 polling-delay = <0>; 4320 4321 thermal-sensors = <&tsens0 8>; 4322 4323 trips { 4324 cpu5_alert0: trip-point0 { 4325 temperature = <90000>; 4326 hysteresis = <2000>; 4327 type = "passive"; 4328 }; 4329 4330 cpu5_alert1: trip-point1 { 4331 temperature = <95000>; 4332 hysteresis = <2000>; 4333 type = "passive"; 4334 }; 4335 4336 cpu5_crit: cpu-crit { 4337 temperature = <110000>; 4338 hysteresis = <0>; 4339 type = "critical"; 4340 }; 4341 }; 4342 4343 cooling-maps { 4344 map0 { 4345 trip = <&cpu5_alert0>; 4346 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4347 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4348 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4349 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4350 }; 4351 map1 { 4352 trip = <&cpu5_alert1>; 4353 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4354 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4355 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4356 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4357 }; 4358 }; 4359 }; 4360 4361 cpu6-thermal { 4362 polling-delay-passive = <250>; 4363 polling-delay = <0>; 4364 4365 thermal-sensors = <&tsens0 9>; 4366 4367 trips { 4368 cpu6_alert0: trip-point0 { 4369 temperature = <90000>; 4370 hysteresis = <2000>; 4371 type = "passive"; 4372 }; 4373 4374 cpu6_alert1: trip-point1 { 4375 temperature = <95000>; 4376 hysteresis = <2000>; 4377 type = "passive"; 4378 }; 4379 4380 cpu6_crit: cpu-crit { 4381 temperature = <110000>; 4382 hysteresis = <0>; 4383 type = "critical"; 4384 }; 4385 }; 4386 4387 cooling-maps { 4388 map0 { 4389 trip = <&cpu6_alert0>; 4390 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4391 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4392 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4393 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4394 }; 4395 map1 { 4396 trip = <&cpu6_alert1>; 4397 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4399 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4400 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4401 }; 4402 }; 4403 }; 4404 4405 cpu7-thermal { 4406 polling-delay-passive = <250>; 4407 polling-delay = <0>; 4408 4409 thermal-sensors = <&tsens0 10>; 4410 4411 trips { 4412 cpu7_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "passive"; 4416 }; 4417 4418 cpu7_alert1: trip-point1 { 4419 temperature = <95000>; 4420 hysteresis = <2000>; 4421 type = "passive"; 4422 }; 4423 4424 cpu7_crit: cpu-crit { 4425 temperature = <110000>; 4426 hysteresis = <0>; 4427 type = "critical"; 4428 }; 4429 }; 4430 4431 cooling-maps { 4432 map0 { 4433 trip = <&cpu7_alert0>; 4434 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4435 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4436 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4437 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4438 }; 4439 map1 { 4440 trip = <&cpu7_alert1>; 4441 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4442 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4443 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4444 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4445 }; 4446 }; 4447 }; 4448 4449 cpu8-thermal { 4450 polling-delay-passive = <250>; 4451 polling-delay = <0>; 4452 4453 thermal-sensors = <&tsens0 11>; 4454 4455 trips { 4456 cpu8_alert0: trip-point0 { 4457 temperature = <90000>; 4458 hysteresis = <2000>; 4459 type = "passive"; 4460 }; 4461 4462 cpu8_alert1: trip-point1 { 4463 temperature = <95000>; 4464 hysteresis = <2000>; 4465 type = "passive"; 4466 }; 4467 4468 cpu8_crit: cpu-crit { 4469 temperature = <110000>; 4470 hysteresis = <0>; 4471 type = "critical"; 4472 }; 4473 }; 4474 4475 cooling-maps { 4476 map0 { 4477 trip = <&cpu8_alert0>; 4478 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4479 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4480 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4481 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4482 }; 4483 map1 { 4484 trip = <&cpu8_alert1>; 4485 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4486 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4487 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4488 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4489 }; 4490 }; 4491 }; 4492 4493 cpu9-thermal { 4494 polling-delay-passive = <250>; 4495 polling-delay = <0>; 4496 4497 thermal-sensors = <&tsens0 12>; 4498 4499 trips { 4500 cpu9_alert0: trip-point0 { 4501 temperature = <90000>; 4502 hysteresis = <2000>; 4503 type = "passive"; 4504 }; 4505 4506 cpu9_alert1: trip-point1 { 4507 temperature = <95000>; 4508 hysteresis = <2000>; 4509 type = "passive"; 4510 }; 4511 4512 cpu9_crit: cpu-crit { 4513 temperature = <110000>; 4514 hysteresis = <0>; 4515 type = "critical"; 4516 }; 4517 }; 4518 4519 cooling-maps { 4520 map0 { 4521 trip = <&cpu9_alert0>; 4522 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4523 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4524 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4525 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4526 }; 4527 map1 { 4528 trip = <&cpu9_alert1>; 4529 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4530 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4531 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4532 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4533 }; 4534 }; 4535 }; 4536 4537 cpu10-thermal { 4538 polling-delay-passive = <250>; 4539 polling-delay = <0>; 4540 4541 thermal-sensors = <&tsens0 13>; 4542 4543 trips { 4544 cpu10_alert0: trip-point0 { 4545 temperature = <90000>; 4546 hysteresis = <2000>; 4547 type = "passive"; 4548 }; 4549 4550 cpu10_alert1: trip-point1 { 4551 temperature = <95000>; 4552 hysteresis = <2000>; 4553 type = "passive"; 4554 }; 4555 4556 cpu10_crit: cpu-crit { 4557 temperature = <110000>; 4558 hysteresis = <0>; 4559 type = "critical"; 4560 }; 4561 }; 4562 4563 cooling-maps { 4564 map0 { 4565 trip = <&cpu10_alert0>; 4566 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4567 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4568 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4569 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4570 }; 4571 map1 { 4572 trip = <&cpu10_alert1>; 4573 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4574 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4575 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4576 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4577 }; 4578 }; 4579 }; 4580 4581 cpu11-thermal { 4582 polling-delay-passive = <250>; 4583 polling-delay = <0>; 4584 4585 thermal-sensors = <&tsens0 14>; 4586 4587 trips { 4588 cpu11_alert0: trip-point0 { 4589 temperature = <90000>; 4590 hysteresis = <2000>; 4591 type = "passive"; 4592 }; 4593 4594 cpu11_alert1: trip-point1 { 4595 temperature = <95000>; 4596 hysteresis = <2000>; 4597 type = "passive"; 4598 }; 4599 4600 cpu11_crit: cpu-crit { 4601 temperature = <110000>; 4602 hysteresis = <0>; 4603 type = "critical"; 4604 }; 4605 }; 4606 4607 cooling-maps { 4608 map0 { 4609 trip = <&cpu11_alert0>; 4610 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4611 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4612 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4613 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4614 }; 4615 map1 { 4616 trip = <&cpu11_alert1>; 4617 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4618 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4619 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4620 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4621 }; 4622 }; 4623 }; 4624 4625 aoss0-thermal { 4626 polling-delay-passive = <0>; 4627 polling-delay = <0>; 4628 4629 thermal-sensors = <&tsens0 0>; 4630 4631 trips { 4632 aoss0_alert0: trip-point0 { 4633 temperature = <90000>; 4634 hysteresis = <2000>; 4635 type = "hot"; 4636 }; 4637 4638 aoss0_crit: aoss0-crit { 4639 temperature = <110000>; 4640 hysteresis = <0>; 4641 type = "critical"; 4642 }; 4643 }; 4644 }; 4645 4646 aoss1-thermal { 4647 polling-delay-passive = <0>; 4648 polling-delay = <0>; 4649 4650 thermal-sensors = <&tsens1 0>; 4651 4652 trips { 4653 aoss1_alert0: trip-point0 { 4654 temperature = <90000>; 4655 hysteresis = <2000>; 4656 type = "hot"; 4657 }; 4658 4659 aoss1_crit: aoss1-crit { 4660 temperature = <110000>; 4661 hysteresis = <0>; 4662 type = "critical"; 4663 }; 4664 }; 4665 }; 4666 4667 cpuss0-thermal { 4668 polling-delay-passive = <0>; 4669 polling-delay = <0>; 4670 4671 thermal-sensors = <&tsens0 5>; 4672 4673 trips { 4674 cpuss0_alert0: trip-point0 { 4675 temperature = <90000>; 4676 hysteresis = <2000>; 4677 type = "hot"; 4678 }; 4679 cpuss0_crit: cluster0-crit { 4680 temperature = <110000>; 4681 hysteresis = <0>; 4682 type = "critical"; 4683 }; 4684 }; 4685 }; 4686 4687 cpuss1-thermal { 4688 polling-delay-passive = <0>; 4689 polling-delay = <0>; 4690 4691 thermal-sensors = <&tsens0 6>; 4692 4693 trips { 4694 cpuss1_alert0: trip-point0 { 4695 temperature = <90000>; 4696 hysteresis = <2000>; 4697 type = "hot"; 4698 }; 4699 cpuss1_crit: cluster0-crit { 4700 temperature = <110000>; 4701 hysteresis = <0>; 4702 type = "critical"; 4703 }; 4704 }; 4705 }; 4706 4707 gpuss0-thermal { 4708 polling-delay-passive = <100>; 4709 polling-delay = <0>; 4710 4711 thermal-sensors = <&tsens1 1>; 4712 4713 trips { 4714 gpuss0_alert0: trip-point0 { 4715 temperature = <95000>; 4716 hysteresis = <2000>; 4717 type = "passive"; 4718 }; 4719 4720 gpuss0_crit: gpuss0-crit { 4721 temperature = <110000>; 4722 hysteresis = <0>; 4723 type = "critical"; 4724 }; 4725 }; 4726 4727 cooling-maps { 4728 map0 { 4729 trip = <&gpuss0_alert0>; 4730 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4731 }; 4732 }; 4733 }; 4734 4735 gpuss1-thermal { 4736 polling-delay-passive = <100>; 4737 polling-delay = <0>; 4738 4739 thermal-sensors = <&tsens1 2>; 4740 4741 trips { 4742 gpuss1_alert0: trip-point0 { 4743 temperature = <95000>; 4744 hysteresis = <2000>; 4745 type = "passive"; 4746 }; 4747 4748 gpuss1_crit: gpuss1-crit { 4749 temperature = <110000>; 4750 hysteresis = <0>; 4751 type = "critical"; 4752 }; 4753 }; 4754 4755 cooling-maps { 4756 map0 { 4757 trip = <&gpuss1_alert0>; 4758 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4759 }; 4760 }; 4761 }; 4762 4763 nspss0-thermal { 4764 polling-delay-passive = <0>; 4765 polling-delay = <0>; 4766 4767 thermal-sensors = <&tsens1 3>; 4768 4769 trips { 4770 nspss0_alert0: trip-point0 { 4771 temperature = <90000>; 4772 hysteresis = <2000>; 4773 type = "hot"; 4774 }; 4775 4776 nspss0_crit: nspss0-crit { 4777 temperature = <110000>; 4778 hysteresis = <0>; 4779 type = "critical"; 4780 }; 4781 }; 4782 }; 4783 4784 nspss1-thermal { 4785 polling-delay-passive = <0>; 4786 polling-delay = <0>; 4787 4788 thermal-sensors = <&tsens1 4>; 4789 4790 trips { 4791 nspss1_alert0: trip-point0 { 4792 temperature = <90000>; 4793 hysteresis = <2000>; 4794 type = "hot"; 4795 }; 4796 4797 nspss1_crit: nspss1-crit { 4798 temperature = <110000>; 4799 hysteresis = <0>; 4800 type = "critical"; 4801 }; 4802 }; 4803 }; 4804 4805 video-thermal { 4806 polling-delay-passive = <0>; 4807 polling-delay = <0>; 4808 4809 thermal-sensors = <&tsens1 5>; 4810 4811 trips { 4812 video_alert0: trip-point0 { 4813 temperature = <90000>; 4814 hysteresis = <2000>; 4815 type = "hot"; 4816 }; 4817 4818 video_crit: video-crit { 4819 temperature = <110000>; 4820 hysteresis = <0>; 4821 type = "critical"; 4822 }; 4823 }; 4824 }; 4825 4826 ddr-thermal { 4827 polling-delay-passive = <0>; 4828 polling-delay = <0>; 4829 4830 thermal-sensors = <&tsens1 6>; 4831 4832 trips { 4833 ddr_alert0: trip-point0 { 4834 temperature = <90000>; 4835 hysteresis = <2000>; 4836 type = "hot"; 4837 }; 4838 4839 ddr_crit: ddr-crit { 4840 temperature = <110000>; 4841 hysteresis = <0>; 4842 type = "critical"; 4843 }; 4844 }; 4845 }; 4846 4847 mdmss0-thermal { 4848 polling-delay-passive = <0>; 4849 polling-delay = <0>; 4850 4851 thermal-sensors = <&tsens1 7>; 4852 4853 trips { 4854 mdmss0_alert0: trip-point0 { 4855 temperature = <90000>; 4856 hysteresis = <2000>; 4857 type = "hot"; 4858 }; 4859 4860 mdmss0_crit: mdmss0-crit { 4861 temperature = <110000>; 4862 hysteresis = <0>; 4863 type = "critical"; 4864 }; 4865 }; 4866 }; 4867 4868 mdmss1-thermal { 4869 polling-delay-passive = <0>; 4870 polling-delay = <0>; 4871 4872 thermal-sensors = <&tsens1 8>; 4873 4874 trips { 4875 mdmss1_alert0: trip-point0 { 4876 temperature = <90000>; 4877 hysteresis = <2000>; 4878 type = "hot"; 4879 }; 4880 4881 mdmss1_crit: mdmss1-crit { 4882 temperature = <110000>; 4883 hysteresis = <0>; 4884 type = "critical"; 4885 }; 4886 }; 4887 }; 4888 4889 mdmss2-thermal { 4890 polling-delay-passive = <0>; 4891 polling-delay = <0>; 4892 4893 thermal-sensors = <&tsens1 9>; 4894 4895 trips { 4896 mdmss2_alert0: trip-point0 { 4897 temperature = <90000>; 4898 hysteresis = <2000>; 4899 type = "hot"; 4900 }; 4901 4902 mdmss2_crit: mdmss2-crit { 4903 temperature = <110000>; 4904 hysteresis = <0>; 4905 type = "critical"; 4906 }; 4907 }; 4908 }; 4909 4910 mdmss3-thermal { 4911 polling-delay-passive = <0>; 4912 polling-delay = <0>; 4913 4914 thermal-sensors = <&tsens1 10>; 4915 4916 trips { 4917 mdmss3_alert0: trip-point0 { 4918 temperature = <90000>; 4919 hysteresis = <2000>; 4920 type = "hot"; 4921 }; 4922 4923 mdmss3_crit: mdmss3-crit { 4924 temperature = <110000>; 4925 hysteresis = <0>; 4926 type = "critical"; 4927 }; 4928 }; 4929 }; 4930 4931 camera0-thermal { 4932 polling-delay-passive = <0>; 4933 polling-delay = <0>; 4934 4935 thermal-sensors = <&tsens1 11>; 4936 4937 trips { 4938 camera0_alert0: trip-point0 { 4939 temperature = <90000>; 4940 hysteresis = <2000>; 4941 type = "hot"; 4942 }; 4943 4944 camera0_crit: camera0-crit { 4945 temperature = <110000>; 4946 hysteresis = <0>; 4947 type = "critical"; 4948 }; 4949 }; 4950 }; 4951 }; 4952 4953 timer { 4954 compatible = "arm,armv8-timer"; 4955 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4956 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4957 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4958 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4959 }; 4960}; 4961