1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,lpass.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 aliases { 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 i2c6 = &i2c6; 45 i2c7 = &i2c7; 46 i2c8 = &i2c8; 47 i2c9 = &i2c9; 48 i2c10 = &i2c10; 49 i2c11 = &i2c11; 50 i2c12 = &i2c12; 51 i2c13 = &i2c13; 52 i2c14 = &i2c14; 53 i2c15 = &i2c15; 54 mmc1 = &sdhc_1; 55 mmc2 = &sdhc_2; 56 spi0 = &spi0; 57 spi1 = &spi1; 58 spi2 = &spi2; 59 spi3 = &spi3; 60 spi4 = &spi4; 61 spi5 = &spi5; 62 spi6 = &spi6; 63 spi7 = &spi7; 64 spi8 = &spi8; 65 spi9 = &spi9; 66 spi10 = &spi10; 67 spi11 = &spi11; 68 spi12 = &spi12; 69 spi13 = &spi13; 70 spi14 = &spi14; 71 spi15 = &spi15; 72 }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 clock-frequency = <76800000>; 78 #clock-cells = <0>; 79 }; 80 81 sleep_clk: sleep-clk { 82 compatible = "fixed-clock"; 83 clock-frequency = <32000>; 84 #clock-cells = <0>; 85 }; 86 }; 87 88 reserved-memory { 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 wlan_ce_mem: memory@4cd000 { 94 no-map; 95 reg = <0x0 0x004cd000 0x0 0x1000>; 96 }; 97 98 hyp_mem: memory@80000000 { 99 reg = <0x0 0x80000000 0x0 0x600000>; 100 no-map; 101 }; 102 103 xbl_mem: memory@80600000 { 104 reg = <0x0 0x80600000 0x0 0x200000>; 105 no-map; 106 }; 107 108 aop_mem: memory@80800000 { 109 reg = <0x0 0x80800000 0x0 0x60000>; 110 no-map; 111 }; 112 113 aop_cmd_db_mem: memory@80860000 { 114 reg = <0x0 0x80860000 0x0 0x20000>; 115 compatible = "qcom,cmd-db"; 116 no-map; 117 }; 118 119 reserved_xbl_uefi_log: memory@80880000 { 120 reg = <0x0 0x80884000 0x0 0x10000>; 121 no-map; 122 }; 123 124 sec_apps_mem: memory@808ff000 { 125 reg = <0x0 0x808ff000 0x0 0x1000>; 126 no-map; 127 }; 128 129 smem_mem: memory@80900000 { 130 reg = <0x0 0x80900000 0x0 0x200000>; 131 no-map; 132 }; 133 134 cpucp_mem: memory@80b00000 { 135 no-map; 136 reg = <0x0 0x80b00000 0x0 0x100000>; 137 }; 138 139 wlan_fw_mem: memory@80c00000 { 140 reg = <0x0 0x80c00000 0x0 0xc00000>; 141 no-map; 142 }; 143 144 video_mem: memory@8b200000 { 145 reg = <0x0 0x8b200000 0x0 0x500000>; 146 no-map; 147 }; 148 149 ipa_fw_mem: memory@8b700000 { 150 reg = <0 0x8b700000 0 0x10000>; 151 no-map; 152 }; 153 154 rmtfs_mem: memory@9c900000 { 155 compatible = "qcom,rmtfs-mem"; 156 reg = <0x0 0x9c900000 0x0 0x280000>; 157 no-map; 158 159 qcom,client-id = <1>; 160 qcom,vmid = <15>; 161 }; 162 }; 163 164 cpus { 165 #address-cells = <2>; 166 #size-cells = <0>; 167 168 CPU0: cpu@0 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo"; 171 reg = <0x0 0x0>; 172 clocks = <&cpufreq_hw 0>; 173 enable-method = "psci"; 174 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 175 &LITTLE_CPU_SLEEP_1 176 &CLUSTER_SLEEP_0>; 177 next-level-cache = <&L2_0>; 178 operating-points-v2 = <&cpu0_opp_table>; 179 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 180 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 181 qcom,freq-domain = <&cpufreq_hw 0>; 182 #cooling-cells = <2>; 183 L2_0: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 L3_0: l3-cache { 189 compatible = "cache"; 190 cache-level = <3>; 191 cache-unified; 192 }; 193 }; 194 }; 195 196 CPU1: cpu@100 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo"; 199 reg = <0x0 0x100>; 200 clocks = <&cpufreq_hw 0>; 201 enable-method = "psci"; 202 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 203 &LITTLE_CPU_SLEEP_1 204 &CLUSTER_SLEEP_0>; 205 next-level-cache = <&L2_100>; 206 operating-points-v2 = <&cpu0_opp_table>; 207 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 208 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 #cooling-cells = <2>; 211 L2_100: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-unified; 215 next-level-cache = <&L3_0>; 216 }; 217 }; 218 219 CPU2: cpu@200 { 220 device_type = "cpu"; 221 compatible = "qcom,kryo"; 222 reg = <0x0 0x200>; 223 clocks = <&cpufreq_hw 0>; 224 enable-method = "psci"; 225 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 226 &LITTLE_CPU_SLEEP_1 227 &CLUSTER_SLEEP_0>; 228 next-level-cache = <&L2_200>; 229 operating-points-v2 = <&cpu0_opp_table>; 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 231 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 232 qcom,freq-domain = <&cpufreq_hw 0>; 233 #cooling-cells = <2>; 234 L2_200: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 CPU3: cpu@300 { 243 device_type = "cpu"; 244 compatible = "qcom,kryo"; 245 reg = <0x0 0x300>; 246 clocks = <&cpufreq_hw 0>; 247 enable-method = "psci"; 248 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 249 &LITTLE_CPU_SLEEP_1 250 &CLUSTER_SLEEP_0>; 251 next-level-cache = <&L2_300>; 252 operating-points-v2 = <&cpu0_opp_table>; 253 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 254 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 255 qcom,freq-domain = <&cpufreq_hw 0>; 256 #cooling-cells = <2>; 257 L2_300: l2-cache { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-unified; 261 next-level-cache = <&L3_0>; 262 }; 263 }; 264 265 CPU4: cpu@400 { 266 device_type = "cpu"; 267 compatible = "qcom,kryo"; 268 reg = <0x0 0x400>; 269 clocks = <&cpufreq_hw 1>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 next-level-cache = <&L2_400>; 275 operating-points-v2 = <&cpu4_opp_table>; 276 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 277 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 278 qcom,freq-domain = <&cpufreq_hw 1>; 279 #cooling-cells = <2>; 280 L2_400: l2-cache { 281 compatible = "cache"; 282 cache-level = <2>; 283 cache-unified; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU5: cpu@500 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo"; 291 reg = <0x0 0x500>; 292 clocks = <&cpufreq_hw 1>; 293 enable-method = "psci"; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 next-level-cache = <&L2_500>; 298 operating-points-v2 = <&cpu4_opp_table>; 299 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 300 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 301 qcom,freq-domain = <&cpufreq_hw 1>; 302 #cooling-cells = <2>; 303 L2_500: l2-cache { 304 compatible = "cache"; 305 cache-level = <2>; 306 cache-unified; 307 next-level-cache = <&L3_0>; 308 }; 309 }; 310 311 CPU6: cpu@600 { 312 device_type = "cpu"; 313 compatible = "qcom,kryo"; 314 reg = <0x0 0x600>; 315 clocks = <&cpufreq_hw 1>; 316 enable-method = "psci"; 317 cpu-idle-states = <&BIG_CPU_SLEEP_0 318 &BIG_CPU_SLEEP_1 319 &CLUSTER_SLEEP_0>; 320 next-level-cache = <&L2_600>; 321 operating-points-v2 = <&cpu4_opp_table>; 322 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 323 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 324 qcom,freq-domain = <&cpufreq_hw 1>; 325 #cooling-cells = <2>; 326 L2_600: l2-cache { 327 compatible = "cache"; 328 cache-level = <2>; 329 cache-unified; 330 next-level-cache = <&L3_0>; 331 }; 332 }; 333 334 CPU7: cpu@700 { 335 device_type = "cpu"; 336 compatible = "qcom,kryo"; 337 reg = <0x0 0x700>; 338 clocks = <&cpufreq_hw 2>; 339 enable-method = "psci"; 340 cpu-idle-states = <&BIG_CPU_SLEEP_0 341 &BIG_CPU_SLEEP_1 342 &CLUSTER_SLEEP_0>; 343 next-level-cache = <&L2_700>; 344 operating-points-v2 = <&cpu7_opp_table>; 345 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 346 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 347 qcom,freq-domain = <&cpufreq_hw 2>; 348 #cooling-cells = <2>; 349 L2_700: l2-cache { 350 compatible = "cache"; 351 cache-level = <2>; 352 cache-unified; 353 next-level-cache = <&L3_0>; 354 }; 355 }; 356 357 cpu-map { 358 cluster0 { 359 core0 { 360 cpu = <&CPU0>; 361 }; 362 363 core1 { 364 cpu = <&CPU1>; 365 }; 366 367 core2 { 368 cpu = <&CPU2>; 369 }; 370 371 core3 { 372 cpu = <&CPU3>; 373 }; 374 375 core4 { 376 cpu = <&CPU4>; 377 }; 378 379 core5 { 380 cpu = <&CPU5>; 381 }; 382 383 core6 { 384 cpu = <&CPU6>; 385 }; 386 387 core7 { 388 cpu = <&CPU7>; 389 }; 390 }; 391 }; 392 393 idle-states { 394 entry-method = "psci"; 395 396 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-power-down"; 399 arm,psci-suspend-param = <0x40000003>; 400 entry-latency-us = <549>; 401 exit-latency-us = <901>; 402 min-residency-us = <1774>; 403 local-timer-stop; 404 }; 405 406 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "little-rail-power-down"; 409 arm,psci-suspend-param = <0x40000004>; 410 entry-latency-us = <702>; 411 exit-latency-us = <915>; 412 min-residency-us = <4001>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-power-down"; 419 arm,psci-suspend-param = <0x40000003>; 420 entry-latency-us = <523>; 421 exit-latency-us = <1244>; 422 min-residency-us = <2207>; 423 local-timer-stop; 424 }; 425 426 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "big-rail-power-down"; 429 arm,psci-suspend-param = <0x40000004>; 430 entry-latency-us = <526>; 431 exit-latency-us = <1854>; 432 min-residency-us = <5555>; 433 local-timer-stop; 434 }; 435 436 CLUSTER_SLEEP_0: cluster-sleep-0 { 437 compatible = "arm,idle-state"; 438 idle-state-name = "cluster-power-down"; 439 arm,psci-suspend-param = <0x40003444>; 440 entry-latency-us = <3263>; 441 exit-latency-us = <6562>; 442 min-residency-us = <9926>; 443 local-timer-stop; 444 }; 445 }; 446 }; 447 448 cpu0_opp_table: opp-table-cpu0 { 449 compatible = "operating-points-v2"; 450 opp-shared; 451 452 cpu0_opp_300mhz: opp-300000000 { 453 opp-hz = /bits/ 64 <300000000>; 454 opp-peak-kBps = <800000 9600000>; 455 }; 456 457 cpu0_opp_691mhz: opp-691200000 { 458 opp-hz = /bits/ 64 <691200000>; 459 opp-peak-kBps = <800000 17817600>; 460 }; 461 462 cpu0_opp_806mhz: opp-806400000 { 463 opp-hz = /bits/ 64 <806400000>; 464 opp-peak-kBps = <800000 20889600>; 465 }; 466 467 cpu0_opp_941mhz: opp-940800000 { 468 opp-hz = /bits/ 64 <940800000>; 469 opp-peak-kBps = <1804000 24576000>; 470 }; 471 472 cpu0_opp_1152mhz: opp-1152000000 { 473 opp-hz = /bits/ 64 <1152000000>; 474 opp-peak-kBps = <2188000 27033600>; 475 }; 476 477 cpu0_opp_1325mhz: opp-1324800000 { 478 opp-hz = /bits/ 64 <1324800000>; 479 opp-peak-kBps = <2188000 33792000>; 480 }; 481 482 cpu0_opp_1517mhz: opp-1516800000 { 483 opp-hz = /bits/ 64 <1516800000>; 484 opp-peak-kBps = <3072000 38092800>; 485 }; 486 487 cpu0_opp_1651mhz: opp-1651200000 { 488 opp-hz = /bits/ 64 <1651200000>; 489 opp-peak-kBps = <3072000 41779200>; 490 }; 491 492 cpu0_opp_1805mhz: opp-1804800000 { 493 opp-hz = /bits/ 64 <1804800000>; 494 opp-peak-kBps = <4068000 48537600>; 495 }; 496 497 cpu0_opp_1958mhz: opp-1958400000 { 498 opp-hz = /bits/ 64 <1958400000>; 499 opp-peak-kBps = <4068000 48537600>; 500 }; 501 502 cpu0_opp_2016mhz: opp-2016000000 { 503 opp-hz = /bits/ 64 <2016000000>; 504 opp-peak-kBps = <6220000 48537600>; 505 }; 506 }; 507 508 cpu4_opp_table: opp-table-cpu4 { 509 compatible = "operating-points-v2"; 510 opp-shared; 511 512 cpu4_opp_691mhz: opp-691200000 { 513 opp-hz = /bits/ 64 <691200000>; 514 opp-peak-kBps = <1804000 9600000>; 515 }; 516 517 cpu4_opp_941mhz: opp-940800000 { 518 opp-hz = /bits/ 64 <940800000>; 519 opp-peak-kBps = <2188000 17817600>; 520 }; 521 522 cpu4_opp_1229mhz: opp-1228800000 { 523 opp-hz = /bits/ 64 <1228800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1344mhz: opp-1344000000 { 528 opp-hz = /bits/ 64 <1344000000>; 529 opp-peak-kBps = <4068000 24576000>; 530 }; 531 532 cpu4_opp_1517mhz: opp-1516800000 { 533 opp-hz = /bits/ 64 <1516800000>; 534 opp-peak-kBps = <4068000 24576000>; 535 }; 536 537 cpu4_opp_1651mhz: opp-1651200000 { 538 opp-hz = /bits/ 64 <1651200000>; 539 opp-peak-kBps = <6220000 38092800>; 540 }; 541 542 cpu4_opp_1901mhz: opp-1900800000 { 543 opp-hz = /bits/ 64 <1900800000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2054mhz: opp-2054400000 { 548 opp-hz = /bits/ 64 <2054400000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2112mhz: opp-2112000000 { 553 opp-hz = /bits/ 64 <2112000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2131mhz: opp-2131200000 { 558 opp-hz = /bits/ 64 <2131200000>; 559 opp-peak-kBps = <6220000 44851200>; 560 }; 561 562 cpu4_opp_2208mhz: opp-2208000000 { 563 opp-hz = /bits/ 64 <2208000000>; 564 opp-peak-kBps = <6220000 44851200>; 565 }; 566 567 cpu4_opp_2400mhz: opp-2400000000 { 568 opp-hz = /bits/ 64 <2400000000>; 569 opp-peak-kBps = <8532000 48537600>; 570 }; 571 572 cpu4_opp_2611mhz: opp-2611200000 { 573 opp-hz = /bits/ 64 <2611200000>; 574 opp-peak-kBps = <8532000 48537600>; 575 }; 576 }; 577 578 cpu7_opp_table: opp-table-cpu7 { 579 compatible = "operating-points-v2"; 580 opp-shared; 581 582 cpu7_opp_806mhz: opp-806400000 { 583 opp-hz = /bits/ 64 <806400000>; 584 opp-peak-kBps = <1804000 9600000>; 585 }; 586 587 cpu7_opp_1056mhz: opp-1056000000 { 588 opp-hz = /bits/ 64 <1056000000>; 589 opp-peak-kBps = <2188000 17817600>; 590 }; 591 592 cpu7_opp_1325mhz: opp-1324800000 { 593 opp-hz = /bits/ 64 <1324800000>; 594 opp-peak-kBps = <4068000 24576000>; 595 }; 596 597 cpu7_opp_1517mhz: opp-1516800000 { 598 opp-hz = /bits/ 64 <1516800000>; 599 opp-peak-kBps = <4068000 24576000>; 600 }; 601 602 cpu7_opp_1766mhz: opp-1766400000 { 603 opp-hz = /bits/ 64 <1766400000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_1862mhz: opp-1862400000 { 608 opp-hz = /bits/ 64 <1862400000>; 609 opp-peak-kBps = <6220000 38092800>; 610 }; 611 612 cpu7_opp_2035mhz: opp-2035200000 { 613 opp-hz = /bits/ 64 <2035200000>; 614 opp-peak-kBps = <6220000 38092800>; 615 }; 616 617 cpu7_opp_2112mhz: opp-2112000000 { 618 opp-hz = /bits/ 64 <2112000000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu7_opp_2208mhz: opp-2208000000 { 623 opp-hz = /bits/ 64 <2208000000>; 624 opp-peak-kBps = <6220000 44851200>; 625 }; 626 627 cpu7_opp_2381mhz: opp-2380800000 { 628 opp-hz = /bits/ 64 <2380800000>; 629 opp-peak-kBps = <6832000 44851200>; 630 }; 631 632 cpu7_opp_2400mhz: opp-2400000000 { 633 opp-hz = /bits/ 64 <2400000000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_2515mhz: opp-2515200000 { 638 opp-hz = /bits/ 64 <2515200000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 642 cpu7_opp_2707mhz: opp-2707200000 { 643 opp-hz = /bits/ 64 <2707200000>; 644 opp-peak-kBps = <8532000 48537600>; 645 }; 646 647 cpu7_opp_3014mhz: opp-3014400000 { 648 opp-hz = /bits/ 64 <3014400000>; 649 opp-peak-kBps = <8532000 48537600>; 650 }; 651 }; 652 653 memory@80000000 { 654 device_type = "memory"; 655 /* We expect the bootloader to fill in the size */ 656 reg = <0 0x80000000 0 0>; 657 }; 658 659 firmware { 660 scm: scm { 661 compatible = "qcom,scm-sc7280", "qcom,scm"; 662 }; 663 }; 664 665 clk_virt: interconnect { 666 compatible = "qcom,sc7280-clk-virt"; 667 #interconnect-cells = <2>; 668 qcom,bcm-voters = <&apps_bcm_voter>; 669 }; 670 671 smem { 672 compatible = "qcom,smem"; 673 memory-region = <&smem_mem>; 674 hwlocks = <&tcsr_mutex 3>; 675 }; 676 677 smp2p-adsp { 678 compatible = "qcom,smp2p"; 679 qcom,smem = <443>, <429>; 680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 681 IPCC_MPROC_SIGNAL_SMP2P 682 IRQ_TYPE_EDGE_RISING>; 683 mboxes = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P>; 685 686 qcom,local-pid = <0>; 687 qcom,remote-pid = <2>; 688 689 adsp_smp2p_out: master-kernel { 690 qcom,entry-name = "master-kernel"; 691 #qcom,smem-state-cells = <1>; 692 }; 693 694 adsp_smp2p_in: slave-kernel { 695 qcom,entry-name = "slave-kernel"; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 }; 700 701 smp2p-cdsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <94>, <432>; 704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P 706 IRQ_TYPE_EDGE_RISING>; 707 mboxes = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 cdsp_smp2p_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 cdsp_smp2p_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-mpss { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <435>, <428>; 728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 mboxes = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <1>; 736 737 modem_smp2p_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 modem_smp2p_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 748 ipa_smp2p_out: ipa-ap-to-modem { 749 qcom,entry-name = "ipa"; 750 #qcom,smem-state-cells = <1>; 751 }; 752 753 ipa_smp2p_in: ipa-modem-to-ap { 754 qcom,entry-name = "ipa"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 }; 758 }; 759 760 smp2p-wpss { 761 compatible = "qcom,smp2p"; 762 qcom,smem = <617>, <616>; 763 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 764 IPCC_MPROC_SIGNAL_SMP2P 765 IRQ_TYPE_EDGE_RISING>; 766 mboxes = <&ipcc IPCC_CLIENT_WPSS 767 IPCC_MPROC_SIGNAL_SMP2P>; 768 769 qcom,local-pid = <0>; 770 qcom,remote-pid = <13>; 771 772 wpss_smp2p_out: master-kernel { 773 qcom,entry-name = "master-kernel"; 774 #qcom,smem-state-cells = <1>; 775 }; 776 777 wpss_smp2p_in: slave-kernel { 778 qcom,entry-name = "slave-kernel"; 779 interrupt-controller; 780 #interrupt-cells = <2>; 781 }; 782 783 wlan_smp2p_out: wlan-ap-to-wpss { 784 qcom,entry-name = "wlan"; 785 #qcom,smem-state-cells = <1>; 786 }; 787 788 wlan_smp2p_in: wlan-wpss-to-ap { 789 qcom,entry-name = "wlan"; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 }; 793 }; 794 795 pmu { 796 compatible = "arm,armv8-pmuv3"; 797 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 798 }; 799 800 psci { 801 compatible = "arm,psci-1.0"; 802 method = "smc"; 803 }; 804 805 qspi_opp_table: opp-table-qspi { 806 compatible = "operating-points-v2"; 807 808 opp-75000000 { 809 opp-hz = /bits/ 64 <75000000>; 810 required-opps = <&rpmhpd_opp_low_svs>; 811 }; 812 813 opp-150000000 { 814 opp-hz = /bits/ 64 <150000000>; 815 required-opps = <&rpmhpd_opp_svs>; 816 }; 817 818 opp-200000000 { 819 opp-hz = /bits/ 64 <200000000>; 820 required-opps = <&rpmhpd_opp_svs_l1>; 821 }; 822 823 opp-300000000 { 824 opp-hz = /bits/ 64 <300000000>; 825 required-opps = <&rpmhpd_opp_nom>; 826 }; 827 }; 828 829 qup_opp_table: opp-table-qup { 830 compatible = "operating-points-v2"; 831 832 opp-75000000 { 833 opp-hz = /bits/ 64 <75000000>; 834 required-opps = <&rpmhpd_opp_low_svs>; 835 }; 836 837 opp-100000000 { 838 opp-hz = /bits/ 64 <100000000>; 839 required-opps = <&rpmhpd_opp_svs>; 840 }; 841 842 opp-128000000 { 843 opp-hz = /bits/ 64 <128000000>; 844 required-opps = <&rpmhpd_opp_nom>; 845 }; 846 }; 847 848 soc: soc@0 { 849 #address-cells = <2>; 850 #size-cells = <2>; 851 ranges = <0 0 0 0 0x10 0>; 852 dma-ranges = <0 0 0 0 0x10 0>; 853 compatible = "simple-bus"; 854 855 gcc: clock-controller@100000 { 856 compatible = "qcom,gcc-sc7280"; 857 reg = <0 0x00100000 0 0x1f0000>; 858 clocks = <&rpmhcc RPMH_CXO_CLK>, 859 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 860 <0>, <&pcie1_lane>, 861 <0>, <0>, <0>, 862 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 863 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 864 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 865 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 866 "ufs_phy_tx_symbol_0_clk", 867 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 868 #clock-cells = <1>; 869 #reset-cells = <1>; 870 #power-domain-cells = <1>; 871 power-domains = <&rpmhpd SC7280_CX>; 872 }; 873 874 ipcc: mailbox@408000 { 875 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 876 reg = <0 0x00408000 0 0x1000>; 877 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-controller; 879 #interrupt-cells = <3>; 880 #mbox-cells = <2>; 881 }; 882 883 qfprom: efuse@784000 { 884 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 885 reg = <0 0x00784000 0 0xa20>, 886 <0 0x00780000 0 0xa20>, 887 <0 0x00782000 0 0x120>, 888 <0 0x00786000 0 0x1fff>; 889 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 890 clock-names = "core"; 891 power-domains = <&rpmhpd SC7280_MX>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 895 gpu_speed_bin: gpu_speed_bin@1e9 { 896 reg = <0x1e9 0x2>; 897 bits = <5 8>; 898 }; 899 }; 900 901 sdhc_1: mmc@7c4000 { 902 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 903 pinctrl-names = "default", "sleep"; 904 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 905 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 906 status = "disabled"; 907 908 reg = <0 0x007c4000 0 0x1000>, 909 <0 0x007c5000 0 0x1000>; 910 reg-names = "hc", "cqhci"; 911 912 iommus = <&apps_smmu 0xc0 0x0>; 913 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "hc_irq", "pwr_irq"; 916 917 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 918 <&gcc GCC_SDCC1_APPS_CLK>, 919 <&rpmhcc RPMH_CXO_CLK>; 920 clock-names = "iface", "core", "xo"; 921 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 923 interconnect-names = "sdhc-ddr","cpu-sdhc"; 924 power-domains = <&rpmhpd SC7280_CX>; 925 operating-points-v2 = <&sdhc1_opp_table>; 926 927 bus-width = <8>; 928 supports-cqe; 929 dma-coherent; 930 931 qcom,dll-config = <0x0007642c>; 932 qcom,ddr-config = <0x80040868>; 933 934 mmc-ddr-1_8v; 935 mmc-hs200-1_8v; 936 mmc-hs400-1_8v; 937 mmc-hs400-enhanced-strobe; 938 939 resets = <&gcc GCC_SDCC1_BCR>; 940 941 sdhc1_opp_table: opp-table { 942 compatible = "operating-points-v2"; 943 944 opp-100000000 { 945 opp-hz = /bits/ 64 <100000000>; 946 required-opps = <&rpmhpd_opp_low_svs>; 947 opp-peak-kBps = <1800000 400000>; 948 opp-avg-kBps = <100000 0>; 949 }; 950 951 opp-384000000 { 952 opp-hz = /bits/ 64 <384000000>; 953 required-opps = <&rpmhpd_opp_nom>; 954 opp-peak-kBps = <5400000 1600000>; 955 opp-avg-kBps = <390000 0>; 956 }; 957 }; 958 }; 959 960 gpi_dma0: dma-controller@900000 { 961 #dma-cells = <3>; 962 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 963 reg = <0 0x00900000 0 0x60000>; 964 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 976 dma-channels = <12>; 977 dma-channel-mask = <0x7f>; 978 iommus = <&apps_smmu 0x0136 0x0>; 979 status = "disabled"; 980 }; 981 982 qupv3_id_0: geniqup@9c0000 { 983 compatible = "qcom,geni-se-qup"; 984 reg = <0 0x009c0000 0 0x2000>; 985 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 986 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 987 clock-names = "m-ahb", "s-ahb"; 988 #address-cells = <2>; 989 #size-cells = <2>; 990 ranges; 991 iommus = <&apps_smmu 0x123 0x0>; 992 status = "disabled"; 993 994 i2c0: i2c@980000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00980000 0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 998 clock-names = "se"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c0_data_clk>; 1001 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd SC7280_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 spi0: spi@980000 { 1018 compatible = "qcom,geni-spi"; 1019 reg = <0 0x00980000 0 0x4000>; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1021 clock-names = "se"; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1024 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1033 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1034 dma-names = "tx", "rx"; 1035 status = "disabled"; 1036 }; 1037 1038 uart0: serial@980000 { 1039 compatible = "qcom,geni-uart"; 1040 reg = <0 0x00980000 0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1042 clock-names = "se"; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1045 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1046 power-domains = <&rpmhpd SC7280_CX>; 1047 operating-points-v2 = <&qup_opp_table>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1049 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 status = "disabled"; 1052 }; 1053 1054 i2c1: i2c@984000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00984000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1058 clock-names = "se"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_i2c1_data_clk>; 1061 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1066 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1067 interconnect-names = "qup-core", "qup-config", 1068 "qup-memory"; 1069 power-domains = <&rpmhpd SC7280_CX>; 1070 required-opps = <&rpmhpd_opp_low_svs>; 1071 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1072 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1073 dma-names = "tx", "rx"; 1074 status = "disabled"; 1075 }; 1076 1077 spi1: spi@984000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x00984000 0 0x4000>; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1081 clock-names = "se"; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1084 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 power-domains = <&rpmhpd SC7280_CX>; 1088 operating-points-v2 = <&qup_opp_table>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1091 interconnect-names = "qup-core", "qup-config"; 1092 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1093 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1094 dma-names = "tx", "rx"; 1095 status = "disabled"; 1096 }; 1097 1098 uart1: serial@984000 { 1099 compatible = "qcom,geni-uart"; 1100 reg = <0 0x00984000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1102 clock-names = "se"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1105 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd SC7280_CX>; 1107 operating-points-v2 = <&qup_opp_table>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1110 interconnect-names = "qup-core", "qup-config"; 1111 status = "disabled"; 1112 }; 1113 1114 i2c2: i2c@988000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00988000 0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1118 clock-names = "se"; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c2_data_clk>; 1121 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1126 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", 1128 "qup-memory"; 1129 power-domains = <&rpmhpd SC7280_CX>; 1130 required-opps = <&rpmhpd_opp_low_svs>; 1131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1132 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1133 dma-names = "tx", "rx"; 1134 status = "disabled"; 1135 }; 1136 1137 spi2: spi@988000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x00988000 0 0x4000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1141 clock-names = "se"; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1144 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 power-domains = <&rpmhpd SC7280_CX>; 1148 operating-points-v2 = <&qup_opp_table>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1151 interconnect-names = "qup-core", "qup-config"; 1152 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1153 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1154 dma-names = "tx", "rx"; 1155 status = "disabled"; 1156 }; 1157 1158 uart2: serial@988000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00988000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1162 clock-names = "se"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1165 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SC7280_CX>; 1167 operating-points-v2 = <&qup_opp_table>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 1174 i2c3: i2c@98c000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0 0x0098c000 0 0x4000>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1178 clock-names = "se"; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c3_data_clk>; 1181 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1186 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", 1188 "qup-memory"; 1189 power-domains = <&rpmhpd SC7280_CX>; 1190 required-opps = <&rpmhpd_opp_low_svs>; 1191 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1192 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 spi3: spi@98c000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0 0x0098c000 0 0x4000>; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1201 clock-names = "se"; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1204 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1213 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1214 dma-names = "tx", "rx"; 1215 status = "disabled"; 1216 }; 1217 1218 uart3: serial@98c000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0 0x0098c000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1222 clock-names = "se"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1225 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd SC7280_CX>; 1227 operating-points-v2 = <&qup_opp_table>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c4: i2c@990000 { 1235 compatible = "qcom,geni-i2c"; 1236 reg = <0 0x00990000 0 0x4000>; 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1238 clock-names = "se"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_i2c4_data_clk>; 1241 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1247 interconnect-names = "qup-core", "qup-config", 1248 "qup-memory"; 1249 power-domains = <&rpmhpd SC7280_CX>; 1250 required-opps = <&rpmhpd_opp_low_svs>; 1251 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1252 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1253 dma-names = "tx", "rx"; 1254 status = "disabled"; 1255 }; 1256 1257 spi4: spi@990000 { 1258 compatible = "qcom,geni-spi"; 1259 reg = <0 0x00990000 0 0x4000>; 1260 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1261 clock-names = "se"; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 power-domains = <&rpmhpd SC7280_CX>; 1268 operating-points-v2 = <&qup_opp_table>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1271 interconnect-names = "qup-core", "qup-config"; 1272 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1273 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 uart4: serial@990000 { 1279 compatible = "qcom,geni-uart"; 1280 reg = <0 0x00990000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1285 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&rpmhpd SC7280_CX>; 1287 operating-points-v2 = <&qup_opp_table>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1290 interconnect-names = "qup-core", "qup-config"; 1291 status = "disabled"; 1292 }; 1293 1294 i2c5: i2c@994000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x00994000 0 0x4000>; 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1298 clock-names = "se"; 1299 pinctrl-names = "default"; 1300 pinctrl-0 = <&qup_i2c5_data_clk>; 1301 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", 1308 "qup-memory"; 1309 power-domains = <&rpmhpd SC7280_CX>; 1310 required-opps = <&rpmhpd_opp_low_svs>; 1311 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1312 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 status = "disabled"; 1315 }; 1316 1317 spi5: spi@994000 { 1318 compatible = "qcom,geni-spi"; 1319 reg = <0 0x00994000 0 0x4000>; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1321 clock-names = "se"; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1324 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 power-domains = <&rpmhpd SC7280_CX>; 1328 operating-points-v2 = <&qup_opp_table>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1331 interconnect-names = "qup-core", "qup-config"; 1332 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1333 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1334 dma-names = "tx", "rx"; 1335 status = "disabled"; 1336 }; 1337 1338 uart5: serial@994000 { 1339 compatible = "qcom,geni-uart"; 1340 reg = <0 0x00994000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd SC7280_CX>; 1347 operating-points-v2 = <&qup_opp_table>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1350 interconnect-names = "qup-core", "qup-config"; 1351 status = "disabled"; 1352 }; 1353 1354 i2c6: i2c@998000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00998000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1358 clock-names = "se"; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c6_data_clk>; 1361 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1366 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", 1368 "qup-memory"; 1369 power-domains = <&rpmhpd SC7280_CX>; 1370 required-opps = <&rpmhpd_opp_low_svs>; 1371 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1372 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1373 dma-names = "tx", "rx"; 1374 status = "disabled"; 1375 }; 1376 1377 spi6: spi@998000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0x00998000 0 0x4000>; 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1381 clock-names = "se"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1384 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 power-domains = <&rpmhpd SC7280_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1393 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 uart6: serial@998000 { 1399 compatible = "qcom,geni-uart"; 1400 reg = <0 0x00998000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1402 clock-names = "se"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1405 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1406 power-domains = <&rpmhpd SC7280_CX>; 1407 operating-points-v2 = <&qup_opp_table>; 1408 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1410 interconnect-names = "qup-core", "qup-config"; 1411 status = "disabled"; 1412 }; 1413 1414 i2c7: i2c@99c000 { 1415 compatible = "qcom,geni-i2c"; 1416 reg = <0 0x0099c000 0 0x4000>; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1418 clock-names = "se"; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&qup_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1426 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1427 interconnect-names = "qup-core", "qup-config", 1428 "qup-memory"; 1429 power-domains = <&rpmhpd SC7280_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1432 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1433 dma-names = "tx", "rx"; 1434 status = "disabled"; 1435 }; 1436 1437 spi7: spi@99c000 { 1438 compatible = "qcom,geni-spi"; 1439 reg = <0 0x0099c000 0 0x4000>; 1440 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1441 clock-names = "se"; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1444 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 power-domains = <&rpmhpd SC7280_CX>; 1448 operating-points-v2 = <&qup_opp_table>; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1451 interconnect-names = "qup-core", "qup-config"; 1452 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1453 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1454 dma-names = "tx", "rx"; 1455 status = "disabled"; 1456 }; 1457 1458 uart7: serial@99c000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x0099c000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1465 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SC7280_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 gpi_dma1: dma-controller@a00000 { 1476 #dma-cells = <3>; 1477 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1478 reg = <0 0x00a00000 0 0x60000>; 1479 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1491 dma-channels = <12>; 1492 dma-channel-mask = <0x1e>; 1493 iommus = <&apps_smmu 0x56 0x0>; 1494 status = "disabled"; 1495 }; 1496 1497 qupv3_id_1: geniqup@ac0000 { 1498 compatible = "qcom,geni-se-qup"; 1499 reg = <0 0x00ac0000 0 0x2000>; 1500 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1501 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1502 clock-names = "m-ahb", "s-ahb"; 1503 #address-cells = <2>; 1504 #size-cells = <2>; 1505 ranges; 1506 iommus = <&apps_smmu 0x43 0x0>; 1507 status = "disabled"; 1508 1509 i2c8: i2c@a80000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00a80000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1513 clock-names = "se"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_i2c8_data_clk>; 1516 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1521 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1522 interconnect-names = "qup-core", "qup-config", 1523 "qup-memory"; 1524 power-domains = <&rpmhpd SC7280_CX>; 1525 required-opps = <&rpmhpd_opp_low_svs>; 1526 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi8: spi@a80000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0 0x00a80000 0 0x4000>; 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1536 clock-names = "se"; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1539 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 operating-points-v2 = <&qup_opp_table>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1546 interconnect-names = "qup-core", "qup-config"; 1547 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 uart8: serial@a80000 { 1554 compatible = "qcom,geni-uart"; 1555 reg = <0 0x00a80000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1560 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 status = "disabled"; 1567 }; 1568 1569 i2c9: i2c@a84000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0 0x00a84000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1573 clock-names = "se"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c9_data_clk>; 1576 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", 1583 "qup-memory"; 1584 power-domains = <&rpmhpd SC7280_CX>; 1585 required-opps = <&rpmhpd_opp_low_svs>; 1586 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1587 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1588 dma-names = "tx", "rx"; 1589 status = "disabled"; 1590 }; 1591 1592 spi9: spi@a84000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00a84000 0 0x4000>; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 clock-names = "se"; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1599 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 power-domains = <&rpmhpd SC7280_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1606 interconnect-names = "qup-core", "qup-config"; 1607 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1608 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1609 dma-names = "tx", "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 uart9: serial@a84000 { 1614 compatible = "qcom,geni-uart"; 1615 reg = <0 0x00a84000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1617 clock-names = "se"; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1620 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1621 power-domains = <&rpmhpd SC7280_CX>; 1622 operating-points-v2 = <&qup_opp_table>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1625 interconnect-names = "qup-core", "qup-config"; 1626 status = "disabled"; 1627 }; 1628 1629 i2c10: i2c@a88000 { 1630 compatible = "qcom,geni-i2c"; 1631 reg = <0 0x00a88000 0 0x4000>; 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1633 clock-names = "se"; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_i2c10_data_clk>; 1636 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1640 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1641 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1642 interconnect-names = "qup-core", "qup-config", 1643 "qup-memory"; 1644 power-domains = <&rpmhpd SC7280_CX>; 1645 required-opps = <&rpmhpd_opp_low_svs>; 1646 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1648 dma-names = "tx", "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi10: spi@a88000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0 0x00a88000 0 0x4000>; 1655 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1656 clock-names = "se"; 1657 pinctrl-names = "default"; 1658 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1659 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 power-domains = <&rpmhpd SC7280_CX>; 1663 operating-points-v2 = <&qup_opp_table>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1666 interconnect-names = "qup-core", "qup-config"; 1667 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 status = "disabled"; 1671 }; 1672 1673 uart10: serial@a88000 { 1674 compatible = "qcom,geni-uart"; 1675 reg = <0 0x00a88000 0 0x4000>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1677 clock-names = "se"; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1680 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1681 power-domains = <&rpmhpd SC7280_CX>; 1682 operating-points-v2 = <&qup_opp_table>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1685 interconnect-names = "qup-core", "qup-config"; 1686 status = "disabled"; 1687 }; 1688 1689 i2c11: i2c@a8c000 { 1690 compatible = "qcom,geni-i2c"; 1691 reg = <0 0x00a8c000 0 0x4000>; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1693 clock-names = "se"; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_i2c11_data_clk>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1700 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1701 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1702 interconnect-names = "qup-core", "qup-config", 1703 "qup-memory"; 1704 power-domains = <&rpmhpd SC7280_CX>; 1705 required-opps = <&rpmhpd_opp_low_svs>; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1707 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1708 dma-names = "tx", "rx"; 1709 status = "disabled"; 1710 }; 1711 1712 spi11: spi@a8c000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0 0x00a8c000 0 0x4000>; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1716 clock-names = "se"; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1719 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 power-domains = <&rpmhpd SC7280_CX>; 1723 operating-points-v2 = <&qup_opp_table>; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1725 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1726 interconnect-names = "qup-core", "qup-config"; 1727 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1728 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1729 dma-names = "tx", "rx"; 1730 status = "disabled"; 1731 }; 1732 1733 uart11: serial@a8c000 { 1734 compatible = "qcom,geni-uart"; 1735 reg = <0 0x00a8c000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1740 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1741 power-domains = <&rpmhpd SC7280_CX>; 1742 operating-points-v2 = <&qup_opp_table>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1745 interconnect-names = "qup-core", "qup-config"; 1746 status = "disabled"; 1747 }; 1748 1749 i2c12: i2c@a90000 { 1750 compatible = "qcom,geni-i2c"; 1751 reg = <0 0x00a90000 0 0x4000>; 1752 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1753 clock-names = "se"; 1754 pinctrl-names = "default"; 1755 pinctrl-0 = <&qup_i2c12_data_clk>; 1756 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1760 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1761 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1762 interconnect-names = "qup-core", "qup-config", 1763 "qup-memory"; 1764 power-domains = <&rpmhpd SC7280_CX>; 1765 required-opps = <&rpmhpd_opp_low_svs>; 1766 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1767 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1768 dma-names = "tx", "rx"; 1769 status = "disabled"; 1770 }; 1771 1772 spi12: spi@a90000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a90000 0 0x4000>; 1775 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1776 clock-names = "se"; 1777 pinctrl-names = "default"; 1778 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1779 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 power-domains = <&rpmhpd SC7280_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1785 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1786 interconnect-names = "qup-core", "qup-config"; 1787 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1788 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1789 dma-names = "tx", "rx"; 1790 status = "disabled"; 1791 }; 1792 1793 uart12: serial@a90000 { 1794 compatible = "qcom,geni-uart"; 1795 reg = <0 0x00a90000 0 0x4000>; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1797 clock-names = "se"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1800 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1801 power-domains = <&rpmhpd SC7280_CX>; 1802 operating-points-v2 = <&qup_opp_table>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1805 interconnect-names = "qup-core", "qup-config"; 1806 status = "disabled"; 1807 }; 1808 1809 i2c13: i2c@a94000 { 1810 compatible = "qcom,geni-i2c"; 1811 reg = <0 0x00a94000 0 0x4000>; 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1813 clock-names = "se"; 1814 pinctrl-names = "default"; 1815 pinctrl-0 = <&qup_i2c13_data_clk>; 1816 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1820 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1821 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1822 interconnect-names = "qup-core", "qup-config", 1823 "qup-memory"; 1824 power-domains = <&rpmhpd SC7280_CX>; 1825 required-opps = <&rpmhpd_opp_low_svs>; 1826 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1827 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1828 dma-names = "tx", "rx"; 1829 status = "disabled"; 1830 }; 1831 1832 spi13: spi@a94000 { 1833 compatible = "qcom,geni-spi"; 1834 reg = <0 0x00a94000 0 0x4000>; 1835 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1836 clock-names = "se"; 1837 pinctrl-names = "default"; 1838 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1839 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 power-domains = <&rpmhpd SC7280_CX>; 1843 operating-points-v2 = <&qup_opp_table>; 1844 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1846 interconnect-names = "qup-core", "qup-config"; 1847 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1848 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1849 dma-names = "tx", "rx"; 1850 status = "disabled"; 1851 }; 1852 1853 uart13: serial@a94000 { 1854 compatible = "qcom,geni-uart"; 1855 reg = <0 0x00a94000 0 0x4000>; 1856 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1857 clock-names = "se"; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1860 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1861 power-domains = <&rpmhpd SC7280_CX>; 1862 operating-points-v2 = <&qup_opp_table>; 1863 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1864 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1865 interconnect-names = "qup-core", "qup-config"; 1866 status = "disabled"; 1867 }; 1868 1869 i2c14: i2c@a98000 { 1870 compatible = "qcom,geni-i2c"; 1871 reg = <0 0x00a98000 0 0x4000>; 1872 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1873 clock-names = "se"; 1874 pinctrl-names = "default"; 1875 pinctrl-0 = <&qup_i2c14_data_clk>; 1876 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1881 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1882 interconnect-names = "qup-core", "qup-config", 1883 "qup-memory"; 1884 power-domains = <&rpmhpd SC7280_CX>; 1885 required-opps = <&rpmhpd_opp_low_svs>; 1886 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1887 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1888 dma-names = "tx", "rx"; 1889 status = "disabled"; 1890 }; 1891 1892 spi14: spi@a98000 { 1893 compatible = "qcom,geni-spi"; 1894 reg = <0 0x00a98000 0 0x4000>; 1895 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1896 clock-names = "se"; 1897 pinctrl-names = "default"; 1898 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1899 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 power-domains = <&rpmhpd SC7280_CX>; 1903 operating-points-v2 = <&qup_opp_table>; 1904 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1906 interconnect-names = "qup-core", "qup-config"; 1907 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1908 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1909 dma-names = "tx", "rx"; 1910 status = "disabled"; 1911 }; 1912 1913 uart14: serial@a98000 { 1914 compatible = "qcom,geni-uart"; 1915 reg = <0 0x00a98000 0 0x4000>; 1916 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1917 clock-names = "se"; 1918 pinctrl-names = "default"; 1919 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1920 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1921 power-domains = <&rpmhpd SC7280_CX>; 1922 operating-points-v2 = <&qup_opp_table>; 1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1925 interconnect-names = "qup-core", "qup-config"; 1926 status = "disabled"; 1927 }; 1928 1929 i2c15: i2c@a9c000 { 1930 compatible = "qcom,geni-i2c"; 1931 reg = <0 0x00a9c000 0 0x4000>; 1932 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1933 clock-names = "se"; 1934 pinctrl-names = "default"; 1935 pinctrl-0 = <&qup_i2c15_data_clk>; 1936 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1940 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1941 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1942 interconnect-names = "qup-core", "qup-config", 1943 "qup-memory"; 1944 power-domains = <&rpmhpd SC7280_CX>; 1945 required-opps = <&rpmhpd_opp_low_svs>; 1946 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1947 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1948 dma-names = "tx", "rx"; 1949 status = "disabled"; 1950 }; 1951 1952 spi15: spi@a9c000 { 1953 compatible = "qcom,geni-spi"; 1954 reg = <0 0x00a9c000 0 0x4000>; 1955 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1956 clock-names = "se"; 1957 pinctrl-names = "default"; 1958 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1959 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1960 #address-cells = <1>; 1961 #size-cells = <0>; 1962 power-domains = <&rpmhpd SC7280_CX>; 1963 operating-points-v2 = <&qup_opp_table>; 1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1966 interconnect-names = "qup-core", "qup-config"; 1967 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1968 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1969 dma-names = "tx", "rx"; 1970 status = "disabled"; 1971 }; 1972 1973 uart15: serial@a9c000 { 1974 compatible = "qcom,geni-uart"; 1975 reg = <0 0x00a9c000 0 0x4000>; 1976 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1977 clock-names = "se"; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1980 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1981 power-domains = <&rpmhpd SC7280_CX>; 1982 operating-points-v2 = <&qup_opp_table>; 1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1985 interconnect-names = "qup-core", "qup-config"; 1986 status = "disabled"; 1987 }; 1988 }; 1989 1990 cnoc2: interconnect@1500000 { 1991 reg = <0 0x01500000 0 0x1000>; 1992 compatible = "qcom,sc7280-cnoc2"; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 cnoc3: interconnect@1502000 { 1998 reg = <0 0x01502000 0 0x1000>; 1999 compatible = "qcom,sc7280-cnoc3"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mc_virt: interconnect@1580000 { 2005 reg = <0 0x01580000 0 0x4>; 2006 compatible = "qcom,sc7280-mc-virt"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 system_noc: interconnect@1680000 { 2012 reg = <0 0x01680000 0 0x15480>; 2013 compatible = "qcom,sc7280-system-noc"; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 aggre1_noc: interconnect@16e0000 { 2019 compatible = "qcom,sc7280-aggre1-noc"; 2020 reg = <0 0x016e0000 0 0x1c080>; 2021 #interconnect-cells = <2>; 2022 qcom,bcm-voters = <&apps_bcm_voter>; 2023 }; 2024 2025 aggre2_noc: interconnect@1700000 { 2026 reg = <0 0x01700000 0 0x2b080>; 2027 compatible = "qcom,sc7280-aggre2-noc"; 2028 #interconnect-cells = <2>; 2029 qcom,bcm-voters = <&apps_bcm_voter>; 2030 }; 2031 2032 mmss_noc: interconnect@1740000 { 2033 reg = <0 0x01740000 0 0x1e080>; 2034 compatible = "qcom,sc7280-mmss-noc"; 2035 #interconnect-cells = <2>; 2036 qcom,bcm-voters = <&apps_bcm_voter>; 2037 }; 2038 2039 wifi: wifi@17a10040 { 2040 compatible = "qcom,wcn6750-wifi"; 2041 reg = <0 0x17a10040 0 0x0>; 2042 iommus = <&apps_smmu 0x1c00 0x1>; 2043 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2074 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2075 qcom,rproc = <&remoteproc_wpss>; 2076 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2077 status = "disabled"; 2078 qcom,smem-states = <&wlan_smp2p_out 0>; 2079 qcom,smem-state-names = "wlan-smp2p-out"; 2080 }; 2081 2082 pcie1: pci@1c08000 { 2083 compatible = "qcom,pcie-sc7280"; 2084 reg = <0 0x01c08000 0 0x3000>, 2085 <0 0x40000000 0 0xf1d>, 2086 <0 0x40000f20 0 0xa8>, 2087 <0 0x40001000 0 0x1000>, 2088 <0 0x40100000 0 0x100000>; 2089 2090 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2091 device_type = "pci"; 2092 linux,pci-domain = <1>; 2093 bus-range = <0x00 0xff>; 2094 num-lanes = <2>; 2095 2096 #address-cells = <3>; 2097 #size-cells = <2>; 2098 2099 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2100 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2101 2102 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2110 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2111 "msi4", "msi5", "msi6", "msi7"; 2112 #interrupt-cells = <1>; 2113 interrupt-map-mask = <0 0 0 0x7>; 2114 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2115 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2116 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2117 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2118 2119 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2120 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2121 <&pcie1_lane>, 2122 <&rpmhcc RPMH_CXO_CLK>, 2123 <&gcc GCC_PCIE_1_AUX_CLK>, 2124 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2125 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2126 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2127 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2128 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2129 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2130 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2131 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2132 2133 clock-names = "pipe", 2134 "pipe_mux", 2135 "phy_pipe", 2136 "ref", 2137 "aux", 2138 "cfg", 2139 "bus_master", 2140 "bus_slave", 2141 "slave_q2a", 2142 "tbu", 2143 "ddrss_sf_tbu", 2144 "aggre0", 2145 "aggre1"; 2146 2147 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2148 assigned-clock-rates = <19200000>; 2149 2150 resets = <&gcc GCC_PCIE_1_BCR>; 2151 reset-names = "pci"; 2152 2153 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2154 2155 phys = <&pcie1_lane>; 2156 phy-names = "pciephy"; 2157 2158 pinctrl-names = "default"; 2159 pinctrl-0 = <&pcie1_clkreq_n>; 2160 2161 dma-coherent; 2162 2163 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2164 <0x100 &apps_smmu 0x1c81 0x1>; 2165 2166 status = "disabled"; 2167 }; 2168 2169 pcie1_phy: phy@1c0e000 { 2170 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2171 reg = <0 0x01c0e000 0 0x1c0>; 2172 #address-cells = <2>; 2173 #size-cells = <2>; 2174 ranges; 2175 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2176 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2177 <&gcc GCC_PCIE_CLKREF_EN>, 2178 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2179 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2180 2181 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2182 reset-names = "phy"; 2183 2184 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2185 assigned-clock-rates = <100000000>; 2186 2187 status = "disabled"; 2188 2189 pcie1_lane: phy@1c0e200 { 2190 reg = <0 0x01c0e200 0 0x170>, 2191 <0 0x01c0e400 0 0x200>, 2192 <0 0x01c0ea00 0 0x1f0>, 2193 <0 0x01c0e600 0 0x170>, 2194 <0 0x01c0e800 0 0x200>, 2195 <0 0x01c0ee00 0 0xf4>; 2196 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2197 clock-names = "pipe0"; 2198 2199 #phy-cells = <0>; 2200 #clock-cells = <0>; 2201 clock-output-names = "pcie_1_pipe_clk"; 2202 }; 2203 }; 2204 2205 ipa: ipa@1e40000 { 2206 compatible = "qcom,sc7280-ipa"; 2207 2208 iommus = <&apps_smmu 0x480 0x0>, 2209 <&apps_smmu 0x482 0x0>; 2210 reg = <0 0x01e40000 0 0x8000>, 2211 <0 0x01e50000 0 0x4ad0>, 2212 <0 0x01e04000 0 0x23000>; 2213 reg-names = "ipa-reg", 2214 "ipa-shared", 2215 "gsi"; 2216 2217 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2218 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2219 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2220 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2221 interrupt-names = "ipa", 2222 "gsi", 2223 "ipa-clock-query", 2224 "ipa-setup-ready"; 2225 2226 clocks = <&rpmhcc RPMH_IPA_CLK>; 2227 clock-names = "core"; 2228 2229 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2230 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2231 interconnect-names = "memory", 2232 "config"; 2233 2234 qcom,qmp = <&aoss_qmp>; 2235 2236 qcom,smem-states = <&ipa_smp2p_out 0>, 2237 <&ipa_smp2p_out 1>; 2238 qcom,smem-state-names = "ipa-clock-enabled-valid", 2239 "ipa-clock-enabled"; 2240 2241 status = "disabled"; 2242 }; 2243 2244 tcsr_mutex: hwlock@1f40000 { 2245 compatible = "qcom,tcsr-mutex"; 2246 reg = <0 0x01f40000 0 0x20000>; 2247 #hwlock-cells = <1>; 2248 }; 2249 2250 tcsr_1: syscon@1f60000 { 2251 compatible = "qcom,sc7280-tcsr", "syscon"; 2252 reg = <0 0x01f60000 0 0x20000>; 2253 }; 2254 2255 tcsr_2: syscon@1fc0000 { 2256 compatible = "qcom,sc7280-tcsr", "syscon"; 2257 reg = <0 0x01fc0000 0 0x30000>; 2258 }; 2259 2260 lpasscc: lpasscc@3000000 { 2261 compatible = "qcom,sc7280-lpasscc"; 2262 reg = <0 0x03000000 0 0x40>, 2263 <0 0x03c04000 0 0x4>; 2264 reg-names = "qdsp6ss", "top_cc"; 2265 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2266 clock-names = "iface"; 2267 #clock-cells = <1>; 2268 status = "reserved"; /* Owned by ADSP firmware */ 2269 }; 2270 2271 lpass_rx_macro: codec@3200000 { 2272 compatible = "qcom,sc7280-lpass-rx-macro"; 2273 reg = <0 0x03200000 0 0x1000>; 2274 2275 pinctrl-names = "default"; 2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2277 2278 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2279 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2280 <&lpass_va_macro>; 2281 clock-names = "mclk", "npl", "fsgen"; 2282 2283 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2284 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2285 power-domain-names = "macro", "dcodec"; 2286 2287 #clock-cells = <0>; 2288 #sound-dai-cells = <1>; 2289 2290 status = "disabled"; 2291 }; 2292 2293 swr0: soundwire@3210000 { 2294 compatible = "qcom,soundwire-v1.6.0"; 2295 reg = <0 0x03210000 0 0x2000>; 2296 2297 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2298 clocks = <&lpass_rx_macro>; 2299 clock-names = "iface"; 2300 2301 qcom,din-ports = <0>; 2302 qcom,dout-ports = <5>; 2303 2304 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2305 reset-names = "swr_audio_cgcr"; 2306 2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2316 2317 #sound-dai-cells = <1>; 2318 #address-cells = <2>; 2319 #size-cells = <0>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 lpass_tx_macro: codec@3220000 { 2325 compatible = "qcom,sc7280-lpass-tx-macro"; 2326 reg = <0 0x03220000 0 0x1000>; 2327 2328 pinctrl-names = "default"; 2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2330 2331 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2332 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2333 <&lpass_va_macro>; 2334 clock-names = "mclk", "npl", "fsgen"; 2335 2336 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2337 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2338 power-domain-names = "macro", "dcodec"; 2339 2340 #clock-cells = <0>; 2341 #sound-dai-cells = <1>; 2342 2343 status = "disabled"; 2344 }; 2345 2346 swr1: soundwire@3230000 { 2347 compatible = "qcom,soundwire-v1.6.0"; 2348 reg = <0 0x03230000 0 0x2000>; 2349 2350 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2351 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&lpass_tx_macro>; 2353 clock-names = "iface"; 2354 2355 qcom,din-ports = <3>; 2356 qcom,dout-ports = <0>; 2357 2358 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2359 reset-names = "swr_audio_cgcr"; 2360 2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2370 2371 #sound-dai-cells = <1>; 2372 #address-cells = <2>; 2373 #size-cells = <0>; 2374 2375 status = "disabled"; 2376 }; 2377 2378 lpass_audiocc: clock-controller@3300000 { 2379 compatible = "qcom,sc7280-lpassaudiocc"; 2380 reg = <0 0x03300000 0 0x30000>, 2381 <0 0x032a9000 0 0x1000>; 2382 clocks = <&rpmhcc RPMH_CXO_CLK>, 2383 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2384 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2385 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2386 #clock-cells = <1>; 2387 #power-domain-cells = <1>; 2388 #reset-cells = <1>; 2389 }; 2390 2391 lpass_va_macro: codec@3370000 { 2392 compatible = "qcom,sc7280-lpass-va-macro"; 2393 reg = <0 0x03370000 0 0x1000>; 2394 2395 pinctrl-names = "default"; 2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2397 2398 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2399 clock-names = "mclk"; 2400 2401 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2402 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2403 power-domain-names = "macro", "dcodec"; 2404 2405 #clock-cells = <0>; 2406 #sound-dai-cells = <1>; 2407 2408 status = "disabled"; 2409 }; 2410 2411 lpass_aon: clock-controller@3380000 { 2412 compatible = "qcom,sc7280-lpassaoncc"; 2413 reg = <0 0x03380000 0 0x30000>; 2414 clocks = <&rpmhcc RPMH_CXO_CLK>, 2415 <&rpmhcc RPMH_CXO_CLK_A>, 2416 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2417 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2418 #clock-cells = <1>; 2419 #power-domain-cells = <1>; 2420 status = "reserved"; /* Owned by ADSP firmware */ 2421 }; 2422 2423 lpass_core: clock-controller@3900000 { 2424 compatible = "qcom,sc7280-lpasscorecc"; 2425 reg = <0 0x03900000 0 0x50000>; 2426 clocks = <&rpmhcc RPMH_CXO_CLK>; 2427 clock-names = "bi_tcxo"; 2428 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2429 #clock-cells = <1>; 2430 #power-domain-cells = <1>; 2431 status = "reserved"; /* Owned by ADSP firmware */ 2432 }; 2433 2434 lpass_cpu: audio@3987000 { 2435 compatible = "qcom,sc7280-lpass-cpu"; 2436 2437 reg = <0 0x03987000 0 0x68000>, 2438 <0 0x03b00000 0 0x29000>, 2439 <0 0x03260000 0 0xc000>, 2440 <0 0x03280000 0 0x29000>, 2441 <0 0x03340000 0 0x29000>, 2442 <0 0x0336c000 0 0x3000>; 2443 reg-names = "lpass-hdmiif", 2444 "lpass-lpaif", 2445 "lpass-rxtx-cdc-dma-lpm", 2446 "lpass-rxtx-lpaif", 2447 "lpass-va-lpaif", 2448 "lpass-va-cdc-dma-lpm"; 2449 2450 iommus = <&apps_smmu 0x1820 0>, 2451 <&apps_smmu 0x1821 0>, 2452 <&apps_smmu 0x1832 0>; 2453 2454 power-domains = <&rpmhpd SC7280_LCX>; 2455 power-domain-names = "lcx"; 2456 required-opps = <&rpmhpd_opp_nom>; 2457 2458 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2459 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2460 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2461 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2462 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2463 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2464 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2465 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2466 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2467 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2468 clock-names = "aon_cc_audio_hm_h", 2469 "audio_cc_ext_mclk0", 2470 "core_cc_sysnoc_mport_core", 2471 "core_cc_ext_if0_ibit", 2472 "core_cc_ext_if1_ibit", 2473 "audio_cc_codec_mem", 2474 "audio_cc_codec_mem0", 2475 "audio_cc_codec_mem1", 2476 "audio_cc_codec_mem2", 2477 "aon_cc_va_mem0"; 2478 2479 #sound-dai-cells = <1>; 2480 #address-cells = <1>; 2481 #size-cells = <0>; 2482 2483 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2487 interrupt-names = "lpass-irq-lpaif", 2488 "lpass-irq-hdmi", 2489 "lpass-irq-vaif", 2490 "lpass-irq-rxtxif"; 2491 2492 status = "disabled"; 2493 }; 2494 2495 lpass_hm: clock-controller@3c00000 { 2496 compatible = "qcom,sc7280-lpasshm"; 2497 reg = <0 0x03c00000 0 0x28>; 2498 clocks = <&rpmhcc RPMH_CXO_CLK>; 2499 clock-names = "bi_tcxo"; 2500 #clock-cells = <1>; 2501 #power-domain-cells = <1>; 2502 status = "reserved"; /* Owned by ADSP firmware */ 2503 }; 2504 2505 lpass_ag_noc: interconnect@3c40000 { 2506 reg = <0 0x03c40000 0 0xf080>; 2507 compatible = "qcom,sc7280-lpass-ag-noc"; 2508 #interconnect-cells = <2>; 2509 qcom,bcm-voters = <&apps_bcm_voter>; 2510 }; 2511 2512 lpass_tlmm: pinctrl@33c0000 { 2513 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2514 reg = <0 0x033c0000 0x0 0x20000>, 2515 <0 0x03550000 0x0 0x10000>; 2516 qcom,adsp-bypass-mode; 2517 gpio-controller; 2518 #gpio-cells = <2>; 2519 gpio-ranges = <&lpass_tlmm 0 0 15>; 2520 2521 lpass_dmic01_clk: dmic01-clk-state { 2522 pins = "gpio6"; 2523 function = "dmic1_clk"; 2524 }; 2525 2526 lpass_dmic01_data: dmic01-data-state { 2527 pins = "gpio7"; 2528 function = "dmic1_data"; 2529 }; 2530 2531 lpass_dmic23_clk: dmic23-clk-state { 2532 pins = "gpio8"; 2533 function = "dmic2_clk"; 2534 }; 2535 2536 lpass_dmic23_data: dmic23-data-state { 2537 pins = "gpio9"; 2538 function = "dmic2_data"; 2539 }; 2540 2541 lpass_rx_swr_clk: rx-swr-clk-state { 2542 pins = "gpio3"; 2543 function = "swr_rx_clk"; 2544 }; 2545 2546 lpass_rx_swr_data: rx-swr-data-state { 2547 pins = "gpio4", "gpio5"; 2548 function = "swr_rx_data"; 2549 }; 2550 2551 lpass_tx_swr_clk: tx-swr-clk-state { 2552 pins = "gpio0"; 2553 function = "swr_tx_clk"; 2554 }; 2555 2556 lpass_tx_swr_data: tx-swr-data-state { 2557 pins = "gpio1", "gpio2", "gpio14"; 2558 function = "swr_tx_data"; 2559 }; 2560 }; 2561 2562 gpu: gpu@3d00000 { 2563 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2564 reg = <0 0x03d00000 0 0x40000>, 2565 <0 0x03d9e000 0 0x1000>, 2566 <0 0x03d61000 0 0x800>; 2567 reg-names = "kgsl_3d0_reg_memory", 2568 "cx_mem", 2569 "cx_dbgc"; 2570 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2571 iommus = <&adreno_smmu 0 0x400>, 2572 <&adreno_smmu 1 0x400>; 2573 operating-points-v2 = <&gpu_opp_table>; 2574 qcom,gmu = <&gmu>; 2575 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2576 interconnect-names = "gfx-mem"; 2577 #cooling-cells = <2>; 2578 2579 nvmem-cells = <&gpu_speed_bin>; 2580 nvmem-cell-names = "speed_bin"; 2581 2582 gpu_opp_table: opp-table { 2583 compatible = "operating-points-v2"; 2584 2585 opp-315000000 { 2586 opp-hz = /bits/ 64 <315000000>; 2587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2588 opp-peak-kBps = <1804000>; 2589 opp-supported-hw = <0x03>; 2590 }; 2591 2592 opp-450000000 { 2593 opp-hz = /bits/ 64 <450000000>; 2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2595 opp-peak-kBps = <4068000>; 2596 opp-supported-hw = <0x03>; 2597 }; 2598 2599 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2600 opp-550000000-0 { 2601 opp-hz = /bits/ 64 <550000000>; 2602 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2603 opp-peak-kBps = <8368000>; 2604 opp-supported-hw = <0x01>; 2605 }; 2606 2607 opp-550000000-1 { 2608 opp-hz = /bits/ 64 <550000000>; 2609 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2610 opp-peak-kBps = <6832000>; 2611 opp-supported-hw = <0x02>; 2612 }; 2613 2614 opp-608000000 { 2615 opp-hz = /bits/ 64 <608000000>; 2616 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2617 opp-peak-kBps = <8368000>; 2618 opp-supported-hw = <0x02>; 2619 }; 2620 2621 opp-700000000 { 2622 opp-hz = /bits/ 64 <700000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2624 opp-peak-kBps = <8532000>; 2625 opp-supported-hw = <0x02>; 2626 }; 2627 2628 opp-812000000 { 2629 opp-hz = /bits/ 64 <812000000>; 2630 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2631 opp-peak-kBps = <8532000>; 2632 opp-supported-hw = <0x02>; 2633 }; 2634 2635 opp-840000000 { 2636 opp-hz = /bits/ 64 <840000000>; 2637 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2638 opp-peak-kBps = <8532000>; 2639 opp-supported-hw = <0x02>; 2640 }; 2641 2642 opp-900000000 { 2643 opp-hz = /bits/ 64 <900000000>; 2644 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2645 opp-peak-kBps = <8532000>; 2646 opp-supported-hw = <0x02>; 2647 }; 2648 }; 2649 }; 2650 2651 gmu: gmu@3d6a000 { 2652 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2653 reg = <0 0x03d6a000 0 0x34000>, 2654 <0 0x3de0000 0 0x10000>, 2655 <0 0x0b290000 0 0x10000>; 2656 reg-names = "gmu", "rscc", "gmu_pdc"; 2657 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2658 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2659 interrupt-names = "hfi", "gmu"; 2660 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2661 <&gpucc GPU_CC_CXO_CLK>, 2662 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2663 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2664 <&gpucc GPU_CC_AHB_CLK>, 2665 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2666 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2667 clock-names = "gmu", 2668 "cxo", 2669 "axi", 2670 "memnoc", 2671 "ahb", 2672 "hub", 2673 "smmu_vote"; 2674 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2675 <&gpucc GPU_CC_GX_GDSC>; 2676 power-domain-names = "cx", 2677 "gx"; 2678 iommus = <&adreno_smmu 5 0x400>; 2679 operating-points-v2 = <&gmu_opp_table>; 2680 2681 gmu_opp_table: opp-table { 2682 compatible = "operating-points-v2"; 2683 2684 opp-200000000 { 2685 opp-hz = /bits/ 64 <200000000>; 2686 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2687 }; 2688 }; 2689 }; 2690 2691 gpucc: clock-controller@3d90000 { 2692 compatible = "qcom,sc7280-gpucc"; 2693 reg = <0 0x03d90000 0 0x9000>; 2694 clocks = <&rpmhcc RPMH_CXO_CLK>, 2695 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2696 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2697 clock-names = "bi_tcxo", 2698 "gcc_gpu_gpll0_clk_src", 2699 "gcc_gpu_gpll0_div_clk_src"; 2700 #clock-cells = <1>; 2701 #reset-cells = <1>; 2702 #power-domain-cells = <1>; 2703 }; 2704 2705 dma@117f000 { 2706 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2707 reg = <0x0 0x0117f000 0x0 0x1000>, 2708 <0x0 0x01112000 0x0 0x6000>; 2709 }; 2710 2711 adreno_smmu: iommu@3da0000 { 2712 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2713 "qcom,smmu-500", "arm,mmu-500"; 2714 reg = <0 0x03da0000 0 0x20000>; 2715 #iommu-cells = <2>; 2716 #global-interrupts = <2>; 2717 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2729 2730 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2731 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2732 <&gpucc GPU_CC_AHB_CLK>, 2733 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2734 <&gpucc GPU_CC_CX_GMU_CLK>, 2735 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2736 <&gpucc GPU_CC_HUB_AON_CLK>; 2737 clock-names = "gcc_gpu_memnoc_gfx_clk", 2738 "gcc_gpu_snoc_dvm_gfx_clk", 2739 "gpu_cc_ahb_clk", 2740 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2741 "gpu_cc_cx_gmu_clk", 2742 "gpu_cc_hub_cx_int_clk", 2743 "gpu_cc_hub_aon_clk"; 2744 2745 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2746 dma-coherent; 2747 }; 2748 2749 remoteproc_mpss: remoteproc@4080000 { 2750 compatible = "qcom,sc7280-mpss-pas"; 2751 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2752 reg-names = "qdsp6", "rmb"; 2753 2754 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2755 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2756 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2757 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2758 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2759 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2760 interrupt-names = "wdog", "fatal", "ready", "handover", 2761 "stop-ack", "shutdown-ack"; 2762 2763 clocks = <&rpmhcc RPMH_CXO_CLK>; 2764 clock-names = "xo"; 2765 2766 power-domains = <&rpmhpd SC7280_CX>, 2767 <&rpmhpd SC7280_MSS>; 2768 power-domain-names = "cx", "mss"; 2769 2770 memory-region = <&mpss_mem>; 2771 2772 qcom,qmp = <&aoss_qmp>; 2773 2774 qcom,smem-states = <&modem_smp2p_out 0>; 2775 qcom,smem-state-names = "stop"; 2776 2777 status = "disabled"; 2778 2779 glink-edge { 2780 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2781 IPCC_MPROC_SIGNAL_GLINK_QMP 2782 IRQ_TYPE_EDGE_RISING>; 2783 mboxes = <&ipcc IPCC_CLIENT_MPSS 2784 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2785 label = "modem"; 2786 qcom,remote-pid = <1>; 2787 }; 2788 }; 2789 2790 stm@6002000 { 2791 compatible = "arm,coresight-stm", "arm,primecell"; 2792 reg = <0 0x06002000 0 0x1000>, 2793 <0 0x16280000 0 0x180000>; 2794 reg-names = "stm-base", "stm-stimulus-base"; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 stm_out: endpoint { 2802 remote-endpoint = <&funnel0_in7>; 2803 }; 2804 }; 2805 }; 2806 }; 2807 2808 funnel@6041000 { 2809 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2810 reg = <0 0x06041000 0 0x1000>; 2811 2812 clocks = <&aoss_qmp>; 2813 clock-names = "apb_pclk"; 2814 2815 out-ports { 2816 port { 2817 funnel0_out: endpoint { 2818 remote-endpoint = <&merge_funnel_in0>; 2819 }; 2820 }; 2821 }; 2822 2823 in-ports { 2824 #address-cells = <1>; 2825 #size-cells = <0>; 2826 2827 port@7 { 2828 reg = <7>; 2829 funnel0_in7: endpoint { 2830 remote-endpoint = <&stm_out>; 2831 }; 2832 }; 2833 }; 2834 }; 2835 2836 funnel@6042000 { 2837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2838 reg = <0 0x06042000 0 0x1000>; 2839 2840 clocks = <&aoss_qmp>; 2841 clock-names = "apb_pclk"; 2842 2843 out-ports { 2844 port { 2845 funnel1_out: endpoint { 2846 remote-endpoint = <&merge_funnel_in1>; 2847 }; 2848 }; 2849 }; 2850 2851 in-ports { 2852 #address-cells = <1>; 2853 #size-cells = <0>; 2854 2855 port@4 { 2856 reg = <4>; 2857 funnel1_in4: endpoint { 2858 remote-endpoint = <&apss_merge_funnel_out>; 2859 }; 2860 }; 2861 }; 2862 }; 2863 2864 funnel@6045000 { 2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2866 reg = <0 0x06045000 0 0x1000>; 2867 2868 clocks = <&aoss_qmp>; 2869 clock-names = "apb_pclk"; 2870 2871 out-ports { 2872 port { 2873 merge_funnel_out: endpoint { 2874 remote-endpoint = <&swao_funnel_in>; 2875 }; 2876 }; 2877 }; 2878 2879 in-ports { 2880 #address-cells = <1>; 2881 #size-cells = <0>; 2882 2883 port@0 { 2884 reg = <0>; 2885 merge_funnel_in0: endpoint { 2886 remote-endpoint = <&funnel0_out>; 2887 }; 2888 }; 2889 2890 port@1 { 2891 reg = <1>; 2892 merge_funnel_in1: endpoint { 2893 remote-endpoint = <&funnel1_out>; 2894 }; 2895 }; 2896 }; 2897 }; 2898 2899 replicator@6046000 { 2900 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2901 reg = <0 0x06046000 0 0x1000>; 2902 2903 clocks = <&aoss_qmp>; 2904 clock-names = "apb_pclk"; 2905 2906 out-ports { 2907 port { 2908 replicator_out: endpoint { 2909 remote-endpoint = <&etr_in>; 2910 }; 2911 }; 2912 }; 2913 2914 in-ports { 2915 port { 2916 replicator_in: endpoint { 2917 remote-endpoint = <&swao_replicator_out>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 etr@6048000 { 2924 compatible = "arm,coresight-tmc", "arm,primecell"; 2925 reg = <0 0x06048000 0 0x1000>; 2926 iommus = <&apps_smmu 0x04c0 0>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 arm,scatter-gather; 2931 2932 in-ports { 2933 port { 2934 etr_in: endpoint { 2935 remote-endpoint = <&replicator_out>; 2936 }; 2937 }; 2938 }; 2939 }; 2940 2941 funnel@6b04000 { 2942 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2943 reg = <0 0x06b04000 0 0x1000>; 2944 2945 clocks = <&aoss_qmp>; 2946 clock-names = "apb_pclk"; 2947 2948 out-ports { 2949 port { 2950 swao_funnel_out: endpoint { 2951 remote-endpoint = <&etf_in>; 2952 }; 2953 }; 2954 }; 2955 2956 in-ports { 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 port@7 { 2961 reg = <7>; 2962 swao_funnel_in: endpoint { 2963 remote-endpoint = <&merge_funnel_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 etf@6b05000 { 2970 compatible = "arm,coresight-tmc", "arm,primecell"; 2971 reg = <0 0x06b05000 0 0x1000>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 2976 out-ports { 2977 port { 2978 etf_out: endpoint { 2979 remote-endpoint = <&swao_replicator_in>; 2980 }; 2981 }; 2982 }; 2983 2984 in-ports { 2985 port { 2986 etf_in: endpoint { 2987 remote-endpoint = <&swao_funnel_out>; 2988 }; 2989 }; 2990 }; 2991 }; 2992 2993 replicator@6b06000 { 2994 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2995 reg = <0 0x06b06000 0 0x1000>; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 qcom,replicator-loses-context; 3000 3001 out-ports { 3002 port { 3003 swao_replicator_out: endpoint { 3004 remote-endpoint = <&replicator_in>; 3005 }; 3006 }; 3007 }; 3008 3009 in-ports { 3010 port { 3011 swao_replicator_in: endpoint { 3012 remote-endpoint = <&etf_out>; 3013 }; 3014 }; 3015 }; 3016 }; 3017 3018 etm@7040000 { 3019 compatible = "arm,coresight-etm4x", "arm,primecell"; 3020 reg = <0 0x07040000 0 0x1000>; 3021 3022 cpu = <&CPU0>; 3023 3024 clocks = <&aoss_qmp>; 3025 clock-names = "apb_pclk"; 3026 arm,coresight-loses-context-with-cpu; 3027 qcom,skip-power-up; 3028 3029 out-ports { 3030 port { 3031 etm0_out: endpoint { 3032 remote-endpoint = <&apss_funnel_in0>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 etm@7140000 { 3039 compatible = "arm,coresight-etm4x", "arm,primecell"; 3040 reg = <0 0x07140000 0 0x1000>; 3041 3042 cpu = <&CPU1>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 arm,coresight-loses-context-with-cpu; 3047 qcom,skip-power-up; 3048 3049 out-ports { 3050 port { 3051 etm1_out: endpoint { 3052 remote-endpoint = <&apss_funnel_in1>; 3053 }; 3054 }; 3055 }; 3056 }; 3057 3058 etm@7240000 { 3059 compatible = "arm,coresight-etm4x", "arm,primecell"; 3060 reg = <0 0x07240000 0 0x1000>; 3061 3062 cpu = <&CPU2>; 3063 3064 clocks = <&aoss_qmp>; 3065 clock-names = "apb_pclk"; 3066 arm,coresight-loses-context-with-cpu; 3067 qcom,skip-power-up; 3068 3069 out-ports { 3070 port { 3071 etm2_out: endpoint { 3072 remote-endpoint = <&apss_funnel_in2>; 3073 }; 3074 }; 3075 }; 3076 }; 3077 3078 etm@7340000 { 3079 compatible = "arm,coresight-etm4x", "arm,primecell"; 3080 reg = <0 0x07340000 0 0x1000>; 3081 3082 cpu = <&CPU3>; 3083 3084 clocks = <&aoss_qmp>; 3085 clock-names = "apb_pclk"; 3086 arm,coresight-loses-context-with-cpu; 3087 qcom,skip-power-up; 3088 3089 out-ports { 3090 port { 3091 etm3_out: endpoint { 3092 remote-endpoint = <&apss_funnel_in3>; 3093 }; 3094 }; 3095 }; 3096 }; 3097 3098 etm@7440000 { 3099 compatible = "arm,coresight-etm4x", "arm,primecell"; 3100 reg = <0 0x07440000 0 0x1000>; 3101 3102 cpu = <&CPU4>; 3103 3104 clocks = <&aoss_qmp>; 3105 clock-names = "apb_pclk"; 3106 arm,coresight-loses-context-with-cpu; 3107 qcom,skip-power-up; 3108 3109 out-ports { 3110 port { 3111 etm4_out: endpoint { 3112 remote-endpoint = <&apss_funnel_in4>; 3113 }; 3114 }; 3115 }; 3116 }; 3117 3118 etm@7540000 { 3119 compatible = "arm,coresight-etm4x", "arm,primecell"; 3120 reg = <0 0x07540000 0 0x1000>; 3121 3122 cpu = <&CPU5>; 3123 3124 clocks = <&aoss_qmp>; 3125 clock-names = "apb_pclk"; 3126 arm,coresight-loses-context-with-cpu; 3127 qcom,skip-power-up; 3128 3129 out-ports { 3130 port { 3131 etm5_out: endpoint { 3132 remote-endpoint = <&apss_funnel_in5>; 3133 }; 3134 }; 3135 }; 3136 }; 3137 3138 etm@7640000 { 3139 compatible = "arm,coresight-etm4x", "arm,primecell"; 3140 reg = <0 0x07640000 0 0x1000>; 3141 3142 cpu = <&CPU6>; 3143 3144 clocks = <&aoss_qmp>; 3145 clock-names = "apb_pclk"; 3146 arm,coresight-loses-context-with-cpu; 3147 qcom,skip-power-up; 3148 3149 out-ports { 3150 port { 3151 etm6_out: endpoint { 3152 remote-endpoint = <&apss_funnel_in6>; 3153 }; 3154 }; 3155 }; 3156 }; 3157 3158 etm@7740000 { 3159 compatible = "arm,coresight-etm4x", "arm,primecell"; 3160 reg = <0 0x07740000 0 0x1000>; 3161 3162 cpu = <&CPU7>; 3163 3164 clocks = <&aoss_qmp>; 3165 clock-names = "apb_pclk"; 3166 arm,coresight-loses-context-with-cpu; 3167 qcom,skip-power-up; 3168 3169 out-ports { 3170 port { 3171 etm7_out: endpoint { 3172 remote-endpoint = <&apss_funnel_in7>; 3173 }; 3174 }; 3175 }; 3176 }; 3177 3178 funnel@7800000 { /* APSS Funnel */ 3179 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3180 reg = <0 0x07800000 0 0x1000>; 3181 3182 clocks = <&aoss_qmp>; 3183 clock-names = "apb_pclk"; 3184 3185 out-ports { 3186 port { 3187 apss_funnel_out: endpoint { 3188 remote-endpoint = <&apss_merge_funnel_in>; 3189 }; 3190 }; 3191 }; 3192 3193 in-ports { 3194 #address-cells = <1>; 3195 #size-cells = <0>; 3196 3197 port@0 { 3198 reg = <0>; 3199 apss_funnel_in0: endpoint { 3200 remote-endpoint = <&etm0_out>; 3201 }; 3202 }; 3203 3204 port@1 { 3205 reg = <1>; 3206 apss_funnel_in1: endpoint { 3207 remote-endpoint = <&etm1_out>; 3208 }; 3209 }; 3210 3211 port@2 { 3212 reg = <2>; 3213 apss_funnel_in2: endpoint { 3214 remote-endpoint = <&etm2_out>; 3215 }; 3216 }; 3217 3218 port@3 { 3219 reg = <3>; 3220 apss_funnel_in3: endpoint { 3221 remote-endpoint = <&etm3_out>; 3222 }; 3223 }; 3224 3225 port@4 { 3226 reg = <4>; 3227 apss_funnel_in4: endpoint { 3228 remote-endpoint = <&etm4_out>; 3229 }; 3230 }; 3231 3232 port@5 { 3233 reg = <5>; 3234 apss_funnel_in5: endpoint { 3235 remote-endpoint = <&etm5_out>; 3236 }; 3237 }; 3238 3239 port@6 { 3240 reg = <6>; 3241 apss_funnel_in6: endpoint { 3242 remote-endpoint = <&etm6_out>; 3243 }; 3244 }; 3245 3246 port@7 { 3247 reg = <7>; 3248 apss_funnel_in7: endpoint { 3249 remote-endpoint = <&etm7_out>; 3250 }; 3251 }; 3252 }; 3253 }; 3254 3255 funnel@7810000 { 3256 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3257 reg = <0 0x07810000 0 0x1000>; 3258 3259 clocks = <&aoss_qmp>; 3260 clock-names = "apb_pclk"; 3261 3262 out-ports { 3263 port { 3264 apss_merge_funnel_out: endpoint { 3265 remote-endpoint = <&funnel1_in4>; 3266 }; 3267 }; 3268 }; 3269 3270 in-ports { 3271 port { 3272 apss_merge_funnel_in: endpoint { 3273 remote-endpoint = <&apss_funnel_out>; 3274 }; 3275 }; 3276 }; 3277 }; 3278 3279 sdhc_2: mmc@8804000 { 3280 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3281 pinctrl-names = "default", "sleep"; 3282 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3283 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3284 status = "disabled"; 3285 3286 reg = <0 0x08804000 0 0x1000>; 3287 3288 iommus = <&apps_smmu 0x100 0x0>; 3289 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3291 interrupt-names = "hc_irq", "pwr_irq"; 3292 3293 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3294 <&gcc GCC_SDCC2_APPS_CLK>, 3295 <&rpmhcc RPMH_CXO_CLK>; 3296 clock-names = "iface", "core", "xo"; 3297 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3299 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3300 power-domains = <&rpmhpd SC7280_CX>; 3301 operating-points-v2 = <&sdhc2_opp_table>; 3302 3303 bus-width = <4>; 3304 dma-coherent; 3305 3306 qcom,dll-config = <0x0007642c>; 3307 3308 resets = <&gcc GCC_SDCC2_BCR>; 3309 3310 sdhc2_opp_table: opp-table { 3311 compatible = "operating-points-v2"; 3312 3313 opp-100000000 { 3314 opp-hz = /bits/ 64 <100000000>; 3315 required-opps = <&rpmhpd_opp_low_svs>; 3316 opp-peak-kBps = <1800000 400000>; 3317 opp-avg-kBps = <100000 0>; 3318 }; 3319 3320 opp-202000000 { 3321 opp-hz = /bits/ 64 <202000000>; 3322 required-opps = <&rpmhpd_opp_nom>; 3323 opp-peak-kBps = <5400000 1600000>; 3324 opp-avg-kBps = <200000 0>; 3325 }; 3326 }; 3327 }; 3328 3329 usb_1_hsphy: phy@88e3000 { 3330 compatible = "qcom,sc7280-usb-hs-phy", 3331 "qcom,usb-snps-hs-7nm-phy"; 3332 reg = <0 0x088e3000 0 0x400>; 3333 status = "disabled"; 3334 #phy-cells = <0>; 3335 3336 clocks = <&rpmhcc RPMH_CXO_CLK>; 3337 clock-names = "ref"; 3338 3339 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3340 }; 3341 3342 usb_2_hsphy: phy@88e4000 { 3343 compatible = "qcom,sc7280-usb-hs-phy", 3344 "qcom,usb-snps-hs-7nm-phy"; 3345 reg = <0 0x088e4000 0 0x400>; 3346 status = "disabled"; 3347 #phy-cells = <0>; 3348 3349 clocks = <&rpmhcc RPMH_CXO_CLK>; 3350 clock-names = "ref"; 3351 3352 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3353 }; 3354 3355 usb_1_qmpphy: phy@88e8000 { 3356 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3357 reg = <0 0x088e8000 0 0x3000>; 3358 status = "disabled"; 3359 3360 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3361 <&rpmhcc RPMH_CXO_CLK>, 3362 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3363 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3364 clock-names = "aux", 3365 "ref", 3366 "com_aux", 3367 "usb3_pipe"; 3368 3369 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3370 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3371 reset-names = "phy", "common"; 3372 3373 #clock-cells = <1>; 3374 #phy-cells = <1>; 3375 }; 3376 3377 usb_2: usb@8cf8800 { 3378 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3379 reg = <0 0x08cf8800 0 0x400>; 3380 status = "disabled"; 3381 #address-cells = <2>; 3382 #size-cells = <2>; 3383 ranges; 3384 dma-ranges; 3385 3386 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3387 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3388 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3389 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3390 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3391 clock-names = "cfg_noc", 3392 "core", 3393 "iface", 3394 "sleep", 3395 "mock_utmi"; 3396 3397 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3398 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3399 assigned-clock-rates = <19200000>, <200000000>; 3400 3401 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3402 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3403 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3404 interrupt-names = "hs_phy_irq", 3405 "dp_hs_phy_irq", 3406 "dm_hs_phy_irq"; 3407 3408 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3409 required-opps = <&rpmhpd_opp_nom>; 3410 3411 resets = <&gcc GCC_USB30_SEC_BCR>; 3412 3413 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3415 interconnect-names = "usb-ddr", "apps-usb"; 3416 3417 usb_2_dwc3: usb@8c00000 { 3418 compatible = "snps,dwc3"; 3419 reg = <0 0x08c00000 0 0xe000>; 3420 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3421 iommus = <&apps_smmu 0xa0 0x0>; 3422 snps,dis_u2_susphy_quirk; 3423 snps,dis_enblslpm_quirk; 3424 phys = <&usb_2_hsphy>; 3425 phy-names = "usb2-phy"; 3426 maximum-speed = "high-speed"; 3427 usb-role-switch; 3428 3429 port { 3430 usb2_role_switch: endpoint { 3431 remote-endpoint = <&eud_ep>; 3432 }; 3433 }; 3434 }; 3435 }; 3436 3437 qspi: spi@88dc000 { 3438 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3439 reg = <0 0x088dc000 0 0x1000>; 3440 iommus = <&apps_smmu 0x20 0x0>; 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3444 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3445 <&gcc GCC_QSPI_CORE_CLK>; 3446 clock-names = "iface", "core"; 3447 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3448 &cnoc2 SLAVE_QSPI_0 0>; 3449 interconnect-names = "qspi-config"; 3450 power-domains = <&rpmhpd SC7280_CX>; 3451 operating-points-v2 = <&qspi_opp_table>; 3452 status = "disabled"; 3453 }; 3454 3455 remoteproc_wpss: remoteproc@8a00000 { 3456 compatible = "qcom,sc7280-wpss-pil"; 3457 reg = <0 0x08a00000 0 0x10000>; 3458 3459 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3460 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3461 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3462 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3463 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3464 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3465 interrupt-names = "wdog", "fatal", "ready", "handover", 3466 "stop-ack", "shutdown-ack"; 3467 3468 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3469 <&gcc GCC_WPSS_AHB_CLK>, 3470 <&gcc GCC_WPSS_RSCP_CLK>, 3471 <&rpmhcc RPMH_CXO_CLK>; 3472 clock-names = "ahb_bdg", "ahb", 3473 "rscp", "xo"; 3474 3475 power-domains = <&rpmhpd SC7280_CX>, 3476 <&rpmhpd SC7280_MX>; 3477 power-domain-names = "cx", "mx"; 3478 3479 memory-region = <&wpss_mem>; 3480 3481 qcom,qmp = <&aoss_qmp>; 3482 3483 qcom,smem-states = <&wpss_smp2p_out 0>; 3484 qcom,smem-state-names = "stop"; 3485 3486 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3487 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3488 reset-names = "restart", "pdc_sync"; 3489 3490 qcom,halt-regs = <&tcsr_1 0x17000>; 3491 3492 status = "disabled"; 3493 3494 glink-edge { 3495 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3496 IPCC_MPROC_SIGNAL_GLINK_QMP 3497 IRQ_TYPE_EDGE_RISING>; 3498 mboxes = <&ipcc IPCC_CLIENT_WPSS 3499 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3500 3501 label = "wpss"; 3502 qcom,remote-pid = <13>; 3503 }; 3504 }; 3505 3506 pmu@9091000 { 3507 compatible = "qcom,sc7280-llcc-bwmon"; 3508 reg = <0 0x09091000 0 0x1000>; 3509 3510 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3511 3512 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3513 3514 operating-points-v2 = <&llcc_bwmon_opp_table>; 3515 3516 llcc_bwmon_opp_table: opp-table { 3517 compatible = "operating-points-v2"; 3518 3519 opp-0 { 3520 opp-peak-kBps = <800000>; 3521 }; 3522 opp-1 { 3523 opp-peak-kBps = <1804000>; 3524 }; 3525 opp-2 { 3526 opp-peak-kBps = <2188000>; 3527 }; 3528 opp-3 { 3529 opp-peak-kBps = <3072000>; 3530 }; 3531 opp-4 { 3532 opp-peak-kBps = <4068000>; 3533 }; 3534 opp-5 { 3535 opp-peak-kBps = <6220000>; 3536 }; 3537 opp-6 { 3538 opp-peak-kBps = <6832000>; 3539 }; 3540 opp-7 { 3541 opp-peak-kBps = <8532000>; 3542 }; 3543 }; 3544 }; 3545 3546 pmu@90b6400 { 3547 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3548 reg = <0 0x090b6400 0 0x600>; 3549 3550 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3551 3552 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3553 operating-points-v2 = <&cpu_bwmon_opp_table>; 3554 3555 cpu_bwmon_opp_table: opp-table { 3556 compatible = "operating-points-v2"; 3557 3558 opp-0 { 3559 opp-peak-kBps = <2400000>; 3560 }; 3561 opp-1 { 3562 opp-peak-kBps = <4800000>; 3563 }; 3564 opp-2 { 3565 opp-peak-kBps = <7456000>; 3566 }; 3567 opp-3 { 3568 opp-peak-kBps = <9600000>; 3569 }; 3570 opp-4 { 3571 opp-peak-kBps = <12896000>; 3572 }; 3573 opp-5 { 3574 opp-peak-kBps = <14928000>; 3575 }; 3576 opp-6 { 3577 opp-peak-kBps = <17056000>; 3578 }; 3579 }; 3580 }; 3581 3582 dc_noc: interconnect@90e0000 { 3583 reg = <0 0x090e0000 0 0x5080>; 3584 compatible = "qcom,sc7280-dc-noc"; 3585 #interconnect-cells = <2>; 3586 qcom,bcm-voters = <&apps_bcm_voter>; 3587 }; 3588 3589 gem_noc: interconnect@9100000 { 3590 reg = <0 0x09100000 0 0xe2200>; 3591 compatible = "qcom,sc7280-gem-noc"; 3592 #interconnect-cells = <2>; 3593 qcom,bcm-voters = <&apps_bcm_voter>; 3594 }; 3595 3596 system-cache-controller@9200000 { 3597 compatible = "qcom,sc7280-llcc"; 3598 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3599 <0 0x09600000 0 0x58000>; 3600 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3601 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3602 }; 3603 3604 eud: eud@88e0000 { 3605 compatible = "qcom,sc7280-eud", "qcom,eud"; 3606 reg = <0 0x88e0000 0 0x2000>, 3607 <0 0x88e2000 0 0x1000>; 3608 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3609 3610 status = "disabled"; 3611 3612 ports { 3613 #address-cells = <1>; 3614 #size-cells = <0>; 3615 3616 port@0 { 3617 reg = <0>; 3618 eud_ep: endpoint { 3619 remote-endpoint = <&usb2_role_switch>; 3620 }; 3621 }; 3622 }; 3623 }; 3624 3625 nsp_noc: interconnect@a0c0000 { 3626 reg = <0 0x0a0c0000 0 0x10000>; 3627 compatible = "qcom,sc7280-nsp-noc"; 3628 #interconnect-cells = <2>; 3629 qcom,bcm-voters = <&apps_bcm_voter>; 3630 }; 3631 3632 usb_1: usb@a6f8800 { 3633 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3634 reg = <0 0x0a6f8800 0 0x400>; 3635 status = "disabled"; 3636 #address-cells = <2>; 3637 #size-cells = <2>; 3638 ranges; 3639 dma-ranges; 3640 3641 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3642 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3643 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3644 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3645 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3646 clock-names = "cfg_noc", 3647 "core", 3648 "iface", 3649 "sleep", 3650 "mock_utmi"; 3651 3652 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3653 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3654 assigned-clock-rates = <19200000>, <200000000>; 3655 3656 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3657 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3658 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3659 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3660 interrupt-names = "hs_phy_irq", 3661 "dp_hs_phy_irq", 3662 "dm_hs_phy_irq", 3663 "ss_phy_irq"; 3664 3665 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3666 required-opps = <&rpmhpd_opp_nom>; 3667 3668 resets = <&gcc GCC_USB30_PRIM_BCR>; 3669 3670 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3671 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3672 interconnect-names = "usb-ddr", "apps-usb"; 3673 3674 wakeup-source; 3675 3676 usb_1_dwc3: usb@a600000 { 3677 compatible = "snps,dwc3"; 3678 reg = <0 0x0a600000 0 0xe000>; 3679 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3680 iommus = <&apps_smmu 0xe0 0x0>; 3681 snps,dis_u2_susphy_quirk; 3682 snps,dis_enblslpm_quirk; 3683 snps,parkmode-disable-ss-quirk; 3684 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3685 phy-names = "usb2-phy", "usb3-phy"; 3686 maximum-speed = "super-speed"; 3687 }; 3688 }; 3689 3690 venus: video-codec@aa00000 { 3691 compatible = "qcom,sc7280-venus"; 3692 reg = <0 0x0aa00000 0 0xd0600>; 3693 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3694 3695 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3696 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3697 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3698 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3699 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3700 clock-names = "core", "bus", "iface", 3701 "vcodec_core", "vcodec_bus"; 3702 3703 power-domains = <&videocc MVSC_GDSC>, 3704 <&videocc MVS0_GDSC>, 3705 <&rpmhpd SC7280_CX>; 3706 power-domain-names = "venus", "vcodec0", "cx"; 3707 operating-points-v2 = <&venus_opp_table>; 3708 3709 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3710 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3711 interconnect-names = "cpu-cfg", "video-mem"; 3712 3713 iommus = <&apps_smmu 0x2180 0x20>, 3714 <&apps_smmu 0x2184 0x20>; 3715 memory-region = <&video_mem>; 3716 3717 video-decoder { 3718 compatible = "venus-decoder"; 3719 }; 3720 3721 video-encoder { 3722 compatible = "venus-encoder"; 3723 }; 3724 3725 video-firmware { 3726 iommus = <&apps_smmu 0x21a2 0x0>; 3727 }; 3728 3729 venus_opp_table: opp-table { 3730 compatible = "operating-points-v2"; 3731 3732 opp-133330000 { 3733 opp-hz = /bits/ 64 <133330000>; 3734 required-opps = <&rpmhpd_opp_low_svs>; 3735 }; 3736 3737 opp-240000000 { 3738 opp-hz = /bits/ 64 <240000000>; 3739 required-opps = <&rpmhpd_opp_svs>; 3740 }; 3741 3742 opp-335000000 { 3743 opp-hz = /bits/ 64 <335000000>; 3744 required-opps = <&rpmhpd_opp_svs_l1>; 3745 }; 3746 3747 opp-424000000 { 3748 opp-hz = /bits/ 64 <424000000>; 3749 required-opps = <&rpmhpd_opp_nom>; 3750 }; 3751 3752 opp-460000048 { 3753 opp-hz = /bits/ 64 <460000048>; 3754 required-opps = <&rpmhpd_opp_turbo>; 3755 }; 3756 }; 3757 }; 3758 3759 videocc: clock-controller@aaf0000 { 3760 compatible = "qcom,sc7280-videocc"; 3761 reg = <0 0x0aaf0000 0 0x10000>; 3762 clocks = <&rpmhcc RPMH_CXO_CLK>, 3763 <&rpmhcc RPMH_CXO_CLK_A>; 3764 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3765 #clock-cells = <1>; 3766 #reset-cells = <1>; 3767 #power-domain-cells = <1>; 3768 }; 3769 3770 camcc: clock-controller@ad00000 { 3771 compatible = "qcom,sc7280-camcc"; 3772 reg = <0 0x0ad00000 0 0x10000>; 3773 clocks = <&rpmhcc RPMH_CXO_CLK>, 3774 <&rpmhcc RPMH_CXO_CLK_A>, 3775 <&sleep_clk>; 3776 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3777 #clock-cells = <1>; 3778 #reset-cells = <1>; 3779 #power-domain-cells = <1>; 3780 }; 3781 3782 dispcc: clock-controller@af00000 { 3783 compatible = "qcom,sc7280-dispcc"; 3784 reg = <0 0x0af00000 0 0x20000>; 3785 clocks = <&rpmhcc RPMH_CXO_CLK>, 3786 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3787 <&mdss_dsi_phy 0>, 3788 <&mdss_dsi_phy 1>, 3789 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3790 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3791 <&mdss_edp_phy 0>, 3792 <&mdss_edp_phy 1>; 3793 clock-names = "bi_tcxo", 3794 "gcc_disp_gpll0_clk", 3795 "dsi0_phy_pll_out_byteclk", 3796 "dsi0_phy_pll_out_dsiclk", 3797 "dp_phy_pll_link_clk", 3798 "dp_phy_pll_vco_div_clk", 3799 "edp_phy_pll_link_clk", 3800 "edp_phy_pll_vco_div_clk"; 3801 #clock-cells = <1>; 3802 #reset-cells = <1>; 3803 #power-domain-cells = <1>; 3804 }; 3805 3806 mdss: display-subsystem@ae00000 { 3807 compatible = "qcom,sc7280-mdss"; 3808 reg = <0 0x0ae00000 0 0x1000>; 3809 reg-names = "mdss"; 3810 3811 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3812 3813 clocks = <&gcc GCC_DISP_AHB_CLK>, 3814 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3815 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3816 clock-names = "iface", 3817 "ahb", 3818 "core"; 3819 3820 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3821 interrupt-controller; 3822 #interrupt-cells = <1>; 3823 3824 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3825 interconnect-names = "mdp0-mem"; 3826 3827 iommus = <&apps_smmu 0x900 0x402>; 3828 3829 #address-cells = <2>; 3830 #size-cells = <2>; 3831 ranges; 3832 3833 status = "disabled"; 3834 3835 mdss_mdp: display-controller@ae01000 { 3836 compatible = "qcom,sc7280-dpu"; 3837 reg = <0 0x0ae01000 0 0x8f030>, 3838 <0 0x0aeb0000 0 0x2008>; 3839 reg-names = "mdp", "vbif"; 3840 3841 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3842 <&gcc GCC_DISP_SF_AXI_CLK>, 3843 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3844 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3845 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3846 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3847 clock-names = "bus", 3848 "nrt_bus", 3849 "iface", 3850 "lut", 3851 "core", 3852 "vsync"; 3853 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3854 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3855 assigned-clock-rates = <19200000>, 3856 <19200000>; 3857 operating-points-v2 = <&mdp_opp_table>; 3858 power-domains = <&rpmhpd SC7280_CX>; 3859 3860 interrupt-parent = <&mdss>; 3861 interrupts = <0>; 3862 3863 ports { 3864 #address-cells = <1>; 3865 #size-cells = <0>; 3866 3867 port@0 { 3868 reg = <0>; 3869 dpu_intf1_out: endpoint { 3870 remote-endpoint = <&mdss_dsi0_in>; 3871 }; 3872 }; 3873 3874 port@1 { 3875 reg = <1>; 3876 dpu_intf5_out: endpoint { 3877 remote-endpoint = <&edp_in>; 3878 }; 3879 }; 3880 3881 port@2 { 3882 reg = <2>; 3883 dpu_intf0_out: endpoint { 3884 remote-endpoint = <&dp_in>; 3885 }; 3886 }; 3887 }; 3888 3889 mdp_opp_table: opp-table { 3890 compatible = "operating-points-v2"; 3891 3892 opp-200000000 { 3893 opp-hz = /bits/ 64 <200000000>; 3894 required-opps = <&rpmhpd_opp_low_svs>; 3895 }; 3896 3897 opp-300000000 { 3898 opp-hz = /bits/ 64 <300000000>; 3899 required-opps = <&rpmhpd_opp_svs>; 3900 }; 3901 3902 opp-380000000 { 3903 opp-hz = /bits/ 64 <380000000>; 3904 required-opps = <&rpmhpd_opp_svs_l1>; 3905 }; 3906 3907 opp-506666667 { 3908 opp-hz = /bits/ 64 <506666667>; 3909 required-opps = <&rpmhpd_opp_nom>; 3910 }; 3911 }; 3912 }; 3913 3914 mdss_dsi: dsi@ae94000 { 3915 compatible = "qcom,sc7280-dsi-ctrl", 3916 "qcom,mdss-dsi-ctrl"; 3917 reg = <0 0x0ae94000 0 0x400>; 3918 reg-names = "dsi_ctrl"; 3919 3920 interrupt-parent = <&mdss>; 3921 interrupts = <4>; 3922 3923 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3924 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3925 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3926 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3927 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3928 <&gcc GCC_DISP_HF_AXI_CLK>; 3929 clock-names = "byte", 3930 "byte_intf", 3931 "pixel", 3932 "core", 3933 "iface", 3934 "bus"; 3935 3936 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3937 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3938 3939 operating-points-v2 = <&dsi_opp_table>; 3940 power-domains = <&rpmhpd SC7280_CX>; 3941 3942 phys = <&mdss_dsi_phy>; 3943 3944 #address-cells = <1>; 3945 #size-cells = <0>; 3946 3947 status = "disabled"; 3948 3949 ports { 3950 #address-cells = <1>; 3951 #size-cells = <0>; 3952 3953 port@0 { 3954 reg = <0>; 3955 mdss_dsi0_in: endpoint { 3956 remote-endpoint = <&dpu_intf1_out>; 3957 }; 3958 }; 3959 3960 port@1 { 3961 reg = <1>; 3962 mdss_dsi0_out: endpoint { 3963 }; 3964 }; 3965 }; 3966 3967 dsi_opp_table: opp-table { 3968 compatible = "operating-points-v2"; 3969 3970 opp-187500000 { 3971 opp-hz = /bits/ 64 <187500000>; 3972 required-opps = <&rpmhpd_opp_low_svs>; 3973 }; 3974 3975 opp-300000000 { 3976 opp-hz = /bits/ 64 <300000000>; 3977 required-opps = <&rpmhpd_opp_svs>; 3978 }; 3979 3980 opp-358000000 { 3981 opp-hz = /bits/ 64 <358000000>; 3982 required-opps = <&rpmhpd_opp_svs_l1>; 3983 }; 3984 }; 3985 }; 3986 3987 mdss_dsi_phy: phy@ae94400 { 3988 compatible = "qcom,sc7280-dsi-phy-7nm"; 3989 reg = <0 0x0ae94400 0 0x200>, 3990 <0 0x0ae94600 0 0x280>, 3991 <0 0x0ae94900 0 0x280>; 3992 reg-names = "dsi_phy", 3993 "dsi_phy_lane", 3994 "dsi_pll"; 3995 3996 #clock-cells = <1>; 3997 #phy-cells = <0>; 3998 3999 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4000 <&rpmhcc RPMH_CXO_CLK>; 4001 clock-names = "iface", "ref"; 4002 4003 status = "disabled"; 4004 }; 4005 4006 mdss_edp: edp@aea0000 { 4007 compatible = "qcom,sc7280-edp"; 4008 pinctrl-names = "default"; 4009 pinctrl-0 = <&edp_hot_plug_det>; 4010 4011 reg = <0 0x0aea0000 0 0x200>, 4012 <0 0x0aea0200 0 0x200>, 4013 <0 0x0aea0400 0 0xc00>, 4014 <0 0x0aea1000 0 0x400>; 4015 4016 interrupt-parent = <&mdss>; 4017 interrupts = <14>; 4018 4019 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4020 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4021 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4022 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4023 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4024 clock-names = "core_iface", 4025 "core_aux", 4026 "ctrl_link", 4027 "ctrl_link_iface", 4028 "stream_pixel"; 4029 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4030 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4031 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4032 4033 phys = <&mdss_edp_phy>; 4034 phy-names = "dp"; 4035 4036 operating-points-v2 = <&edp_opp_table>; 4037 power-domains = <&rpmhpd SC7280_CX>; 4038 4039 status = "disabled"; 4040 4041 ports { 4042 #address-cells = <1>; 4043 #size-cells = <0>; 4044 4045 port@0 { 4046 reg = <0>; 4047 edp_in: endpoint { 4048 remote-endpoint = <&dpu_intf5_out>; 4049 }; 4050 }; 4051 4052 port@1 { 4053 reg = <1>; 4054 mdss_edp_out: endpoint { }; 4055 }; 4056 }; 4057 4058 edp_opp_table: opp-table { 4059 compatible = "operating-points-v2"; 4060 4061 opp-160000000 { 4062 opp-hz = /bits/ 64 <160000000>; 4063 required-opps = <&rpmhpd_opp_low_svs>; 4064 }; 4065 4066 opp-270000000 { 4067 opp-hz = /bits/ 64 <270000000>; 4068 required-opps = <&rpmhpd_opp_svs>; 4069 }; 4070 4071 opp-540000000 { 4072 opp-hz = /bits/ 64 <540000000>; 4073 required-opps = <&rpmhpd_opp_nom>; 4074 }; 4075 4076 opp-810000000 { 4077 opp-hz = /bits/ 64 <810000000>; 4078 required-opps = <&rpmhpd_opp_nom>; 4079 }; 4080 }; 4081 }; 4082 4083 mdss_edp_phy: phy@aec2a00 { 4084 compatible = "qcom,sc7280-edp-phy"; 4085 4086 reg = <0 0x0aec2a00 0 0x19c>, 4087 <0 0x0aec2200 0 0xa0>, 4088 <0 0x0aec2600 0 0xa0>, 4089 <0 0x0aec2000 0 0x1c0>; 4090 4091 clocks = <&rpmhcc RPMH_CXO_CLK>, 4092 <&gcc GCC_EDP_CLKREF_EN>; 4093 clock-names = "aux", 4094 "cfg_ahb"; 4095 4096 #clock-cells = <1>; 4097 #phy-cells = <0>; 4098 4099 status = "disabled"; 4100 }; 4101 4102 mdss_dp: displayport-controller@ae90000 { 4103 compatible = "qcom,sc7280-dp"; 4104 4105 reg = <0 0x0ae90000 0 0x200>, 4106 <0 0x0ae90200 0 0x200>, 4107 <0 0x0ae90400 0 0xc00>, 4108 <0 0x0ae91000 0 0x400>, 4109 <0 0x0ae91400 0 0x400>; 4110 4111 interrupt-parent = <&mdss>; 4112 interrupts = <12>; 4113 4114 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4115 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4116 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4117 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4118 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4119 clock-names = "core_iface", 4120 "core_aux", 4121 "ctrl_link", 4122 "ctrl_link_iface", 4123 "stream_pixel"; 4124 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4125 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4126 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4127 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4128 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4129 phy-names = "dp"; 4130 4131 operating-points-v2 = <&dp_opp_table>; 4132 power-domains = <&rpmhpd SC7280_CX>; 4133 4134 #sound-dai-cells = <0>; 4135 4136 status = "disabled"; 4137 4138 ports { 4139 #address-cells = <1>; 4140 #size-cells = <0>; 4141 4142 port@0 { 4143 reg = <0>; 4144 dp_in: endpoint { 4145 remote-endpoint = <&dpu_intf0_out>; 4146 }; 4147 }; 4148 4149 port@1 { 4150 reg = <1>; 4151 mdss_dp_out: endpoint { }; 4152 }; 4153 }; 4154 4155 dp_opp_table: opp-table { 4156 compatible = "operating-points-v2"; 4157 4158 opp-160000000 { 4159 opp-hz = /bits/ 64 <160000000>; 4160 required-opps = <&rpmhpd_opp_low_svs>; 4161 }; 4162 4163 opp-270000000 { 4164 opp-hz = /bits/ 64 <270000000>; 4165 required-opps = <&rpmhpd_opp_svs>; 4166 }; 4167 4168 opp-540000000 { 4169 opp-hz = /bits/ 64 <540000000>; 4170 required-opps = <&rpmhpd_opp_svs_l1>; 4171 }; 4172 4173 opp-810000000 { 4174 opp-hz = /bits/ 64 <810000000>; 4175 required-opps = <&rpmhpd_opp_nom>; 4176 }; 4177 }; 4178 }; 4179 }; 4180 4181 pdc: interrupt-controller@b220000 { 4182 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4183 reg = <0 0x0b220000 0 0x30000>; 4184 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4185 <55 306 4>, <59 312 3>, <62 374 2>, 4186 <64 434 2>, <66 438 3>, <69 86 1>, 4187 <70 520 54>, <124 609 31>, <155 63 1>, 4188 <156 716 12>; 4189 #interrupt-cells = <2>; 4190 interrupt-parent = <&intc>; 4191 interrupt-controller; 4192 }; 4193 4194 pdc_reset: reset-controller@b5e0000 { 4195 compatible = "qcom,sc7280-pdc-global"; 4196 reg = <0 0x0b5e0000 0 0x20000>; 4197 #reset-cells = <1>; 4198 status = "reserved"; /* Owned by firmware */ 4199 }; 4200 4201 tsens0: thermal-sensor@c263000 { 4202 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4203 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4204 <0 0x0c222000 0 0x1ff>; /* SROT */ 4205 #qcom,sensors = <15>; 4206 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4208 interrupt-names = "uplow","critical"; 4209 #thermal-sensor-cells = <1>; 4210 }; 4211 4212 tsens1: thermal-sensor@c265000 { 4213 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4214 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4215 <0 0x0c223000 0 0x1ff>; /* SROT */ 4216 #qcom,sensors = <12>; 4217 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4219 interrupt-names = "uplow","critical"; 4220 #thermal-sensor-cells = <1>; 4221 }; 4222 4223 aoss_reset: reset-controller@c2a0000 { 4224 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4225 reg = <0 0x0c2a0000 0 0x31000>; 4226 #reset-cells = <1>; 4227 }; 4228 4229 aoss_qmp: power-management@c300000 { 4230 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4231 reg = <0 0x0c300000 0 0x400>; 4232 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4233 IPCC_MPROC_SIGNAL_GLINK_QMP 4234 IRQ_TYPE_EDGE_RISING>; 4235 mboxes = <&ipcc IPCC_CLIENT_AOP 4236 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4237 4238 #clock-cells = <0>; 4239 }; 4240 4241 sram@c3f0000 { 4242 compatible = "qcom,rpmh-stats"; 4243 reg = <0 0x0c3f0000 0 0x400>; 4244 }; 4245 4246 spmi_bus: spmi@c440000 { 4247 compatible = "qcom,spmi-pmic-arb"; 4248 reg = <0 0x0c440000 0 0x1100>, 4249 <0 0x0c600000 0 0x2000000>, 4250 <0 0x0e600000 0 0x100000>, 4251 <0 0x0e700000 0 0xa0000>, 4252 <0 0x0c40a000 0 0x26000>; 4253 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4254 interrupt-names = "periph_irq"; 4255 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4256 qcom,ee = <0>; 4257 qcom,channel = <0>; 4258 #address-cells = <2>; 4259 #size-cells = <0>; 4260 interrupt-controller; 4261 #interrupt-cells = <4>; 4262 }; 4263 4264 tlmm: pinctrl@f100000 { 4265 compatible = "qcom,sc7280-pinctrl"; 4266 reg = <0 0x0f100000 0 0x300000>; 4267 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4268 gpio-controller; 4269 #gpio-cells = <2>; 4270 interrupt-controller; 4271 #interrupt-cells = <2>; 4272 gpio-ranges = <&tlmm 0 0 175>; 4273 wakeup-parent = <&pdc>; 4274 4275 dp_hot_plug_det: dp-hot-plug-det-state { 4276 pins = "gpio47"; 4277 function = "dp_hot"; 4278 }; 4279 4280 edp_hot_plug_det: edp-hot-plug-det-state { 4281 pins = "gpio60"; 4282 function = "edp_hot"; 4283 }; 4284 4285 mi2s0_data0: mi2s0-data0-state { 4286 pins = "gpio98"; 4287 function = "mi2s0_data0"; 4288 }; 4289 4290 mi2s0_data1: mi2s0-data1-state { 4291 pins = "gpio99"; 4292 function = "mi2s0_data1"; 4293 }; 4294 4295 mi2s0_mclk: mi2s0-mclk-state { 4296 pins = "gpio96"; 4297 function = "pri_mi2s"; 4298 }; 4299 4300 mi2s0_sclk: mi2s0-sclk-state { 4301 pins = "gpio97"; 4302 function = "mi2s0_sck"; 4303 }; 4304 4305 mi2s0_ws: mi2s0-ws-state { 4306 pins = "gpio100"; 4307 function = "mi2s0_ws"; 4308 }; 4309 4310 mi2s1_data0: mi2s1-data0-state { 4311 pins = "gpio107"; 4312 function = "mi2s1_data0"; 4313 }; 4314 4315 mi2s1_sclk: mi2s1-sclk-state { 4316 pins = "gpio106"; 4317 function = "mi2s1_sck"; 4318 }; 4319 4320 mi2s1_ws: mi2s1-ws-state { 4321 pins = "gpio108"; 4322 function = "mi2s1_ws"; 4323 }; 4324 4325 pcie1_clkreq_n: pcie1-clkreq-n-state { 4326 pins = "gpio79"; 4327 function = "pcie1_clkreqn"; 4328 }; 4329 4330 qspi_clk: qspi-clk-state { 4331 pins = "gpio14"; 4332 function = "qspi_clk"; 4333 }; 4334 4335 qspi_cs0: qspi-cs0-state { 4336 pins = "gpio15"; 4337 function = "qspi_cs"; 4338 }; 4339 4340 qspi_cs1: qspi-cs1-state { 4341 pins = "gpio19"; 4342 function = "qspi_cs"; 4343 }; 4344 4345 qspi_data0: qspi-data0-state { 4346 pins = "gpio12"; 4347 function = "qspi_data"; 4348 }; 4349 4350 qspi_data1: qspi-data1-state { 4351 pins = "gpio13"; 4352 function = "qspi_data"; 4353 }; 4354 4355 qspi_data23: qspi-data23-state { 4356 pins = "gpio16", "gpio17"; 4357 function = "qspi_data"; 4358 }; 4359 4360 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4361 pins = "gpio0", "gpio1"; 4362 function = "qup00"; 4363 }; 4364 4365 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4366 pins = "gpio4", "gpio5"; 4367 function = "qup01"; 4368 }; 4369 4370 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4371 pins = "gpio8", "gpio9"; 4372 function = "qup02"; 4373 }; 4374 4375 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4376 pins = "gpio12", "gpio13"; 4377 function = "qup03"; 4378 }; 4379 4380 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4381 pins = "gpio16", "gpio17"; 4382 function = "qup04"; 4383 }; 4384 4385 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4386 pins = "gpio20", "gpio21"; 4387 function = "qup05"; 4388 }; 4389 4390 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4391 pins = "gpio24", "gpio25"; 4392 function = "qup06"; 4393 }; 4394 4395 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4396 pins = "gpio28", "gpio29"; 4397 function = "qup07"; 4398 }; 4399 4400 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4401 pins = "gpio32", "gpio33"; 4402 function = "qup10"; 4403 }; 4404 4405 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4406 pins = "gpio36", "gpio37"; 4407 function = "qup11"; 4408 }; 4409 4410 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4411 pins = "gpio40", "gpio41"; 4412 function = "qup12"; 4413 }; 4414 4415 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4416 pins = "gpio44", "gpio45"; 4417 function = "qup13"; 4418 }; 4419 4420 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4421 pins = "gpio48", "gpio49"; 4422 function = "qup14"; 4423 }; 4424 4425 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4426 pins = "gpio52", "gpio53"; 4427 function = "qup15"; 4428 }; 4429 4430 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4431 pins = "gpio56", "gpio57"; 4432 function = "qup16"; 4433 }; 4434 4435 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4436 pins = "gpio60", "gpio61"; 4437 function = "qup17"; 4438 }; 4439 4440 qup_spi0_data_clk: qup-spi0-data-clk-state { 4441 pins = "gpio0", "gpio1", "gpio2"; 4442 function = "qup00"; 4443 }; 4444 4445 qup_spi0_cs: qup-spi0-cs-state { 4446 pins = "gpio3"; 4447 function = "qup00"; 4448 }; 4449 4450 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4451 pins = "gpio3"; 4452 function = "gpio"; 4453 }; 4454 4455 qup_spi1_data_clk: qup-spi1-data-clk-state { 4456 pins = "gpio4", "gpio5", "gpio6"; 4457 function = "qup01"; 4458 }; 4459 4460 qup_spi1_cs: qup-spi1-cs-state { 4461 pins = "gpio7"; 4462 function = "qup01"; 4463 }; 4464 4465 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4466 pins = "gpio7"; 4467 function = "gpio"; 4468 }; 4469 4470 qup_spi2_data_clk: qup-spi2-data-clk-state { 4471 pins = "gpio8", "gpio9", "gpio10"; 4472 function = "qup02"; 4473 }; 4474 4475 qup_spi2_cs: qup-spi2-cs-state { 4476 pins = "gpio11"; 4477 function = "qup02"; 4478 }; 4479 4480 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4481 pins = "gpio11"; 4482 function = "gpio"; 4483 }; 4484 4485 qup_spi3_data_clk: qup-spi3-data-clk-state { 4486 pins = "gpio12", "gpio13", "gpio14"; 4487 function = "qup03"; 4488 }; 4489 4490 qup_spi3_cs: qup-spi3-cs-state { 4491 pins = "gpio15"; 4492 function = "qup03"; 4493 }; 4494 4495 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4496 pins = "gpio15"; 4497 function = "gpio"; 4498 }; 4499 4500 qup_spi4_data_clk: qup-spi4-data-clk-state { 4501 pins = "gpio16", "gpio17", "gpio18"; 4502 function = "qup04"; 4503 }; 4504 4505 qup_spi4_cs: qup-spi4-cs-state { 4506 pins = "gpio19"; 4507 function = "qup04"; 4508 }; 4509 4510 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4511 pins = "gpio19"; 4512 function = "gpio"; 4513 }; 4514 4515 qup_spi5_data_clk: qup-spi5-data-clk-state { 4516 pins = "gpio20", "gpio21", "gpio22"; 4517 function = "qup05"; 4518 }; 4519 4520 qup_spi5_cs: qup-spi5-cs-state { 4521 pins = "gpio23"; 4522 function = "qup05"; 4523 }; 4524 4525 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4526 pins = "gpio23"; 4527 function = "gpio"; 4528 }; 4529 4530 qup_spi6_data_clk: qup-spi6-data-clk-state { 4531 pins = "gpio24", "gpio25", "gpio26"; 4532 function = "qup06"; 4533 }; 4534 4535 qup_spi6_cs: qup-spi6-cs-state { 4536 pins = "gpio27"; 4537 function = "qup06"; 4538 }; 4539 4540 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4541 pins = "gpio27"; 4542 function = "gpio"; 4543 }; 4544 4545 qup_spi7_data_clk: qup-spi7-data-clk-state { 4546 pins = "gpio28", "gpio29", "gpio30"; 4547 function = "qup07"; 4548 }; 4549 4550 qup_spi7_cs: qup-spi7-cs-state { 4551 pins = "gpio31"; 4552 function = "qup07"; 4553 }; 4554 4555 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4556 pins = "gpio31"; 4557 function = "gpio"; 4558 }; 4559 4560 qup_spi8_data_clk: qup-spi8-data-clk-state { 4561 pins = "gpio32", "gpio33", "gpio34"; 4562 function = "qup10"; 4563 }; 4564 4565 qup_spi8_cs: qup-spi8-cs-state { 4566 pins = "gpio35"; 4567 function = "qup10"; 4568 }; 4569 4570 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4571 pins = "gpio35"; 4572 function = "gpio"; 4573 }; 4574 4575 qup_spi9_data_clk: qup-spi9-data-clk-state { 4576 pins = "gpio36", "gpio37", "gpio38"; 4577 function = "qup11"; 4578 }; 4579 4580 qup_spi9_cs: qup-spi9-cs-state { 4581 pins = "gpio39"; 4582 function = "qup11"; 4583 }; 4584 4585 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4586 pins = "gpio39"; 4587 function = "gpio"; 4588 }; 4589 4590 qup_spi10_data_clk: qup-spi10-data-clk-state { 4591 pins = "gpio40", "gpio41", "gpio42"; 4592 function = "qup12"; 4593 }; 4594 4595 qup_spi10_cs: qup-spi10-cs-state { 4596 pins = "gpio43"; 4597 function = "qup12"; 4598 }; 4599 4600 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4601 pins = "gpio43"; 4602 function = "gpio"; 4603 }; 4604 4605 qup_spi11_data_clk: qup-spi11-data-clk-state { 4606 pins = "gpio44", "gpio45", "gpio46"; 4607 function = "qup13"; 4608 }; 4609 4610 qup_spi11_cs: qup-spi11-cs-state { 4611 pins = "gpio47"; 4612 function = "qup13"; 4613 }; 4614 4615 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4616 pins = "gpio47"; 4617 function = "gpio"; 4618 }; 4619 4620 qup_spi12_data_clk: qup-spi12-data-clk-state { 4621 pins = "gpio48", "gpio49", "gpio50"; 4622 function = "qup14"; 4623 }; 4624 4625 qup_spi12_cs: qup-spi12-cs-state { 4626 pins = "gpio51"; 4627 function = "qup14"; 4628 }; 4629 4630 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4631 pins = "gpio51"; 4632 function = "gpio"; 4633 }; 4634 4635 qup_spi13_data_clk: qup-spi13-data-clk-state { 4636 pins = "gpio52", "gpio53", "gpio54"; 4637 function = "qup15"; 4638 }; 4639 4640 qup_spi13_cs: qup-spi13-cs-state { 4641 pins = "gpio55"; 4642 function = "qup15"; 4643 }; 4644 4645 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4646 pins = "gpio55"; 4647 function = "gpio"; 4648 }; 4649 4650 qup_spi14_data_clk: qup-spi14-data-clk-state { 4651 pins = "gpio56", "gpio57", "gpio58"; 4652 function = "qup16"; 4653 }; 4654 4655 qup_spi14_cs: qup-spi14-cs-state { 4656 pins = "gpio59"; 4657 function = "qup16"; 4658 }; 4659 4660 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4661 pins = "gpio59"; 4662 function = "gpio"; 4663 }; 4664 4665 qup_spi15_data_clk: qup-spi15-data-clk-state { 4666 pins = "gpio60", "gpio61", "gpio62"; 4667 function = "qup17"; 4668 }; 4669 4670 qup_spi15_cs: qup-spi15-cs-state { 4671 pins = "gpio63"; 4672 function = "qup17"; 4673 }; 4674 4675 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4676 pins = "gpio63"; 4677 function = "gpio"; 4678 }; 4679 4680 qup_uart0_cts: qup-uart0-cts-state { 4681 pins = "gpio0"; 4682 function = "qup00"; 4683 }; 4684 4685 qup_uart0_rts: qup-uart0-rts-state { 4686 pins = "gpio1"; 4687 function = "qup00"; 4688 }; 4689 4690 qup_uart0_tx: qup-uart0-tx-state { 4691 pins = "gpio2"; 4692 function = "qup00"; 4693 }; 4694 4695 qup_uart0_rx: qup-uart0-rx-state { 4696 pins = "gpio3"; 4697 function = "qup00"; 4698 }; 4699 4700 qup_uart1_cts: qup-uart1-cts-state { 4701 pins = "gpio4"; 4702 function = "qup01"; 4703 }; 4704 4705 qup_uart1_rts: qup-uart1-rts-state { 4706 pins = "gpio5"; 4707 function = "qup01"; 4708 }; 4709 4710 qup_uart1_tx: qup-uart1-tx-state { 4711 pins = "gpio6"; 4712 function = "qup01"; 4713 }; 4714 4715 qup_uart1_rx: qup-uart1-rx-state { 4716 pins = "gpio7"; 4717 function = "qup01"; 4718 }; 4719 4720 qup_uart2_cts: qup-uart2-cts-state { 4721 pins = "gpio8"; 4722 function = "qup02"; 4723 }; 4724 4725 qup_uart2_rts: qup-uart2-rts-state { 4726 pins = "gpio9"; 4727 function = "qup02"; 4728 }; 4729 4730 qup_uart2_tx: qup-uart2-tx-state { 4731 pins = "gpio10"; 4732 function = "qup02"; 4733 }; 4734 4735 qup_uart2_rx: qup-uart2-rx-state { 4736 pins = "gpio11"; 4737 function = "qup02"; 4738 }; 4739 4740 qup_uart3_cts: qup-uart3-cts-state { 4741 pins = "gpio12"; 4742 function = "qup03"; 4743 }; 4744 4745 qup_uart3_rts: qup-uart3-rts-state { 4746 pins = "gpio13"; 4747 function = "qup03"; 4748 }; 4749 4750 qup_uart3_tx: qup-uart3-tx-state { 4751 pins = "gpio14"; 4752 function = "qup03"; 4753 }; 4754 4755 qup_uart3_rx: qup-uart3-rx-state { 4756 pins = "gpio15"; 4757 function = "qup03"; 4758 }; 4759 4760 qup_uart4_cts: qup-uart4-cts-state { 4761 pins = "gpio16"; 4762 function = "qup04"; 4763 }; 4764 4765 qup_uart4_rts: qup-uart4-rts-state { 4766 pins = "gpio17"; 4767 function = "qup04"; 4768 }; 4769 4770 qup_uart4_tx: qup-uart4-tx-state { 4771 pins = "gpio18"; 4772 function = "qup04"; 4773 }; 4774 4775 qup_uart4_rx: qup-uart4-rx-state { 4776 pins = "gpio19"; 4777 function = "qup04"; 4778 }; 4779 4780 qup_uart5_cts: qup-uart5-cts-state { 4781 pins = "gpio20"; 4782 function = "qup05"; 4783 }; 4784 4785 qup_uart5_rts: qup-uart5-rts-state { 4786 pins = "gpio21"; 4787 function = "qup05"; 4788 }; 4789 4790 qup_uart5_tx: qup-uart5-tx-state { 4791 pins = "gpio22"; 4792 function = "qup05"; 4793 }; 4794 4795 qup_uart5_rx: qup-uart5-rx-state { 4796 pins = "gpio23"; 4797 function = "qup05"; 4798 }; 4799 4800 qup_uart6_cts: qup-uart6-cts-state { 4801 pins = "gpio24"; 4802 function = "qup06"; 4803 }; 4804 4805 qup_uart6_rts: qup-uart6-rts-state { 4806 pins = "gpio25"; 4807 function = "qup06"; 4808 }; 4809 4810 qup_uart6_tx: qup-uart6-tx-state { 4811 pins = "gpio26"; 4812 function = "qup06"; 4813 }; 4814 4815 qup_uart6_rx: qup-uart6-rx-state { 4816 pins = "gpio27"; 4817 function = "qup06"; 4818 }; 4819 4820 qup_uart7_cts: qup-uart7-cts-state { 4821 pins = "gpio28"; 4822 function = "qup07"; 4823 }; 4824 4825 qup_uart7_rts: qup-uart7-rts-state { 4826 pins = "gpio29"; 4827 function = "qup07"; 4828 }; 4829 4830 qup_uart7_tx: qup-uart7-tx-state { 4831 pins = "gpio30"; 4832 function = "qup07"; 4833 }; 4834 4835 qup_uart7_rx: qup-uart7-rx-state { 4836 pins = "gpio31"; 4837 function = "qup07"; 4838 }; 4839 4840 qup_uart8_cts: qup-uart8-cts-state { 4841 pins = "gpio32"; 4842 function = "qup10"; 4843 }; 4844 4845 qup_uart8_rts: qup-uart8-rts-state { 4846 pins = "gpio33"; 4847 function = "qup10"; 4848 }; 4849 4850 qup_uart8_tx: qup-uart8-tx-state { 4851 pins = "gpio34"; 4852 function = "qup10"; 4853 }; 4854 4855 qup_uart8_rx: qup-uart8-rx-state { 4856 pins = "gpio35"; 4857 function = "qup10"; 4858 }; 4859 4860 qup_uart9_cts: qup-uart9-cts-state { 4861 pins = "gpio36"; 4862 function = "qup11"; 4863 }; 4864 4865 qup_uart9_rts: qup-uart9-rts-state { 4866 pins = "gpio37"; 4867 function = "qup11"; 4868 }; 4869 4870 qup_uart9_tx: qup-uart9-tx-state { 4871 pins = "gpio38"; 4872 function = "qup11"; 4873 }; 4874 4875 qup_uart9_rx: qup-uart9-rx-state { 4876 pins = "gpio39"; 4877 function = "qup11"; 4878 }; 4879 4880 qup_uart10_cts: qup-uart10-cts-state { 4881 pins = "gpio40"; 4882 function = "qup12"; 4883 }; 4884 4885 qup_uart10_rts: qup-uart10-rts-state { 4886 pins = "gpio41"; 4887 function = "qup12"; 4888 }; 4889 4890 qup_uart10_tx: qup-uart10-tx-state { 4891 pins = "gpio42"; 4892 function = "qup12"; 4893 }; 4894 4895 qup_uart10_rx: qup-uart10-rx-state { 4896 pins = "gpio43"; 4897 function = "qup12"; 4898 }; 4899 4900 qup_uart11_cts: qup-uart11-cts-state { 4901 pins = "gpio44"; 4902 function = "qup13"; 4903 }; 4904 4905 qup_uart11_rts: qup-uart11-rts-state { 4906 pins = "gpio45"; 4907 function = "qup13"; 4908 }; 4909 4910 qup_uart11_tx: qup-uart11-tx-state { 4911 pins = "gpio46"; 4912 function = "qup13"; 4913 }; 4914 4915 qup_uart11_rx: qup-uart11-rx-state { 4916 pins = "gpio47"; 4917 function = "qup13"; 4918 }; 4919 4920 qup_uart12_cts: qup-uart12-cts-state { 4921 pins = "gpio48"; 4922 function = "qup14"; 4923 }; 4924 4925 qup_uart12_rts: qup-uart12-rts-state { 4926 pins = "gpio49"; 4927 function = "qup14"; 4928 }; 4929 4930 qup_uart12_tx: qup-uart12-tx-state { 4931 pins = "gpio50"; 4932 function = "qup14"; 4933 }; 4934 4935 qup_uart12_rx: qup-uart12-rx-state { 4936 pins = "gpio51"; 4937 function = "qup14"; 4938 }; 4939 4940 qup_uart13_cts: qup-uart13-cts-state { 4941 pins = "gpio52"; 4942 function = "qup15"; 4943 }; 4944 4945 qup_uart13_rts: qup-uart13-rts-state { 4946 pins = "gpio53"; 4947 function = "qup15"; 4948 }; 4949 4950 qup_uart13_tx: qup-uart13-tx-state { 4951 pins = "gpio54"; 4952 function = "qup15"; 4953 }; 4954 4955 qup_uart13_rx: qup-uart13-rx-state { 4956 pins = "gpio55"; 4957 function = "qup15"; 4958 }; 4959 4960 qup_uart14_cts: qup-uart14-cts-state { 4961 pins = "gpio56"; 4962 function = "qup16"; 4963 }; 4964 4965 qup_uart14_rts: qup-uart14-rts-state { 4966 pins = "gpio57"; 4967 function = "qup16"; 4968 }; 4969 4970 qup_uart14_tx: qup-uart14-tx-state { 4971 pins = "gpio58"; 4972 function = "qup16"; 4973 }; 4974 4975 qup_uart14_rx: qup-uart14-rx-state { 4976 pins = "gpio59"; 4977 function = "qup16"; 4978 }; 4979 4980 qup_uart15_cts: qup-uart15-cts-state { 4981 pins = "gpio60"; 4982 function = "qup17"; 4983 }; 4984 4985 qup_uart15_rts: qup-uart15-rts-state { 4986 pins = "gpio61"; 4987 function = "qup17"; 4988 }; 4989 4990 qup_uart15_tx: qup-uart15-tx-state { 4991 pins = "gpio62"; 4992 function = "qup17"; 4993 }; 4994 4995 qup_uart15_rx: qup-uart15-rx-state { 4996 pins = "gpio63"; 4997 function = "qup17"; 4998 }; 4999 5000 sdc1_clk: sdc1-clk-state { 5001 pins = "sdc1_clk"; 5002 }; 5003 5004 sdc1_cmd: sdc1-cmd-state { 5005 pins = "sdc1_cmd"; 5006 }; 5007 5008 sdc1_data: sdc1-data-state { 5009 pins = "sdc1_data"; 5010 }; 5011 5012 sdc1_rclk: sdc1-rclk-state { 5013 pins = "sdc1_rclk"; 5014 }; 5015 5016 sdc1_clk_sleep: sdc1-clk-sleep-state { 5017 pins = "sdc1_clk"; 5018 drive-strength = <2>; 5019 bias-bus-hold; 5020 }; 5021 5022 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5023 pins = "sdc1_cmd"; 5024 drive-strength = <2>; 5025 bias-bus-hold; 5026 }; 5027 5028 sdc1_data_sleep: sdc1-data-sleep-state { 5029 pins = "sdc1_data"; 5030 drive-strength = <2>; 5031 bias-bus-hold; 5032 }; 5033 5034 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5035 pins = "sdc1_rclk"; 5036 drive-strength = <2>; 5037 bias-bus-hold; 5038 }; 5039 5040 sdc2_clk: sdc2-clk-state { 5041 pins = "sdc2_clk"; 5042 }; 5043 5044 sdc2_cmd: sdc2-cmd-state { 5045 pins = "sdc2_cmd"; 5046 }; 5047 5048 sdc2_data: sdc2-data-state { 5049 pins = "sdc2_data"; 5050 }; 5051 5052 sdc2_clk_sleep: sdc2-clk-sleep-state { 5053 pins = "sdc2_clk"; 5054 drive-strength = <2>; 5055 bias-bus-hold; 5056 }; 5057 5058 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5059 pins = "sdc2_cmd"; 5060 drive-strength = <2>; 5061 bias-bus-hold; 5062 }; 5063 5064 sdc2_data_sleep: sdc2-data-sleep-state { 5065 pins = "sdc2_data"; 5066 drive-strength = <2>; 5067 bias-bus-hold; 5068 }; 5069 }; 5070 5071 sram@146a5000 { 5072 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5073 reg = <0 0x146a5000 0 0x6000>; 5074 5075 #address-cells = <1>; 5076 #size-cells = <1>; 5077 5078 ranges = <0 0 0x146a5000 0x6000>; 5079 5080 pil-reloc@594c { 5081 compatible = "qcom,pil-reloc-info"; 5082 reg = <0x594c 0xc8>; 5083 }; 5084 }; 5085 5086 apps_smmu: iommu@15000000 { 5087 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5088 reg = <0 0x15000000 0 0x100000>; 5089 #iommu-cells = <2>; 5090 #global-interrupts = <1>; 5091 dma-coherent; 5092 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5173 }; 5174 5175 intc: interrupt-controller@17a00000 { 5176 compatible = "arm,gic-v3"; 5177 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5178 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5179 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5180 #interrupt-cells = <3>; 5181 interrupt-controller; 5182 #address-cells = <2>; 5183 #size-cells = <2>; 5184 ranges; 5185 5186 msi-controller@17a40000 { 5187 compatible = "arm,gic-v3-its"; 5188 reg = <0 0x17a40000 0 0x20000>; 5189 msi-controller; 5190 #msi-cells = <1>; 5191 status = "disabled"; 5192 }; 5193 }; 5194 5195 watchdog: watchdog@17c10000 { 5196 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5197 reg = <0 0x17c10000 0 0x1000>; 5198 clocks = <&sleep_clk>; 5199 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5200 status = "reserved"; /* Owned by Gunyah hyp */ 5201 }; 5202 5203 timer@17c20000 { 5204 #address-cells = <1>; 5205 #size-cells = <1>; 5206 ranges = <0 0 0 0x20000000>; 5207 compatible = "arm,armv7-timer-mem"; 5208 reg = <0 0x17c20000 0 0x1000>; 5209 5210 frame@17c21000 { 5211 frame-number = <0>; 5212 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5214 reg = <0x17c21000 0x1000>, 5215 <0x17c22000 0x1000>; 5216 }; 5217 5218 frame@17c23000 { 5219 frame-number = <1>; 5220 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5221 reg = <0x17c23000 0x1000>; 5222 status = "disabled"; 5223 }; 5224 5225 frame@17c25000 { 5226 frame-number = <2>; 5227 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5228 reg = <0x17c25000 0x1000>; 5229 status = "disabled"; 5230 }; 5231 5232 frame@17c27000 { 5233 frame-number = <3>; 5234 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5235 reg = <0x17c27000 0x1000>; 5236 status = "disabled"; 5237 }; 5238 5239 frame@17c29000 { 5240 frame-number = <4>; 5241 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5242 reg = <0x17c29000 0x1000>; 5243 status = "disabled"; 5244 }; 5245 5246 frame@17c2b000 { 5247 frame-number = <5>; 5248 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5249 reg = <0x17c2b000 0x1000>; 5250 status = "disabled"; 5251 }; 5252 5253 frame@17c2d000 { 5254 frame-number = <6>; 5255 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5256 reg = <0x17c2d000 0x1000>; 5257 status = "disabled"; 5258 }; 5259 }; 5260 5261 apps_rsc: rsc@18200000 { 5262 compatible = "qcom,rpmh-rsc"; 5263 reg = <0 0x18200000 0 0x10000>, 5264 <0 0x18210000 0 0x10000>, 5265 <0 0x18220000 0 0x10000>; 5266 reg-names = "drv-0", "drv-1", "drv-2"; 5267 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5270 qcom,tcs-offset = <0xd00>; 5271 qcom,drv-id = <2>; 5272 qcom,tcs-config = <ACTIVE_TCS 2>, 5273 <SLEEP_TCS 3>, 5274 <WAKE_TCS 3>, 5275 <CONTROL_TCS 1>; 5276 5277 apps_bcm_voter: bcm-voter { 5278 compatible = "qcom,bcm-voter"; 5279 }; 5280 5281 rpmhpd: power-controller { 5282 compatible = "qcom,sc7280-rpmhpd"; 5283 #power-domain-cells = <1>; 5284 operating-points-v2 = <&rpmhpd_opp_table>; 5285 5286 rpmhpd_opp_table: opp-table { 5287 compatible = "operating-points-v2"; 5288 5289 rpmhpd_opp_ret: opp1 { 5290 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5291 }; 5292 5293 rpmhpd_opp_low_svs: opp2 { 5294 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5295 }; 5296 5297 rpmhpd_opp_svs: opp3 { 5298 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5299 }; 5300 5301 rpmhpd_opp_svs_l1: opp4 { 5302 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5303 }; 5304 5305 rpmhpd_opp_svs_l2: opp5 { 5306 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5307 }; 5308 5309 rpmhpd_opp_nom: opp6 { 5310 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5311 }; 5312 5313 rpmhpd_opp_nom_l1: opp7 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5315 }; 5316 5317 rpmhpd_opp_turbo: opp8 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5319 }; 5320 5321 rpmhpd_opp_turbo_l1: opp9 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5323 }; 5324 }; 5325 }; 5326 5327 rpmhcc: clock-controller { 5328 compatible = "qcom,sc7280-rpmh-clk"; 5329 clocks = <&xo_board>; 5330 clock-names = "xo"; 5331 #clock-cells = <1>; 5332 }; 5333 }; 5334 5335 epss_l3: interconnect@18590000 { 5336 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5337 reg = <0 0x18590000 0 0x1000>; 5338 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5339 clock-names = "xo", "alternate"; 5340 #interconnect-cells = <1>; 5341 }; 5342 5343 cpufreq_hw: cpufreq@18591000 { 5344 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5345 reg = <0 0x18591000 0 0x1000>, 5346 <0 0x18592000 0 0x1000>, 5347 <0 0x18593000 0 0x1000>; 5348 5349 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5352 interrupt-names = "dcvsh-irq-0", 5353 "dcvsh-irq-1", 5354 "dcvsh-irq-2"; 5355 5356 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5357 clock-names = "xo", "alternate"; 5358 #freq-domain-cells = <1>; 5359 #clock-cells = <1>; 5360 }; 5361 }; 5362 5363 thermal_zones: thermal-zones { 5364 cpu0-thermal { 5365 polling-delay-passive = <250>; 5366 polling-delay = <0>; 5367 5368 thermal-sensors = <&tsens0 1>; 5369 5370 trips { 5371 cpu0_alert0: trip-point0 { 5372 temperature = <90000>; 5373 hysteresis = <2000>; 5374 type = "passive"; 5375 }; 5376 5377 cpu0_alert1: trip-point1 { 5378 temperature = <95000>; 5379 hysteresis = <2000>; 5380 type = "passive"; 5381 }; 5382 5383 cpu0_crit: cpu-crit { 5384 temperature = <110000>; 5385 hysteresis = <0>; 5386 type = "critical"; 5387 }; 5388 }; 5389 5390 cooling-maps { 5391 map0 { 5392 trip = <&cpu0_alert0>; 5393 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5394 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5395 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5396 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5397 }; 5398 map1 { 5399 trip = <&cpu0_alert1>; 5400 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5401 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5404 }; 5405 }; 5406 }; 5407 5408 cpu1-thermal { 5409 polling-delay-passive = <250>; 5410 polling-delay = <0>; 5411 5412 thermal-sensors = <&tsens0 2>; 5413 5414 trips { 5415 cpu1_alert0: trip-point0 { 5416 temperature = <90000>; 5417 hysteresis = <2000>; 5418 type = "passive"; 5419 }; 5420 5421 cpu1_alert1: trip-point1 { 5422 temperature = <95000>; 5423 hysteresis = <2000>; 5424 type = "passive"; 5425 }; 5426 5427 cpu1_crit: cpu-crit { 5428 temperature = <110000>; 5429 hysteresis = <0>; 5430 type = "critical"; 5431 }; 5432 }; 5433 5434 cooling-maps { 5435 map0 { 5436 trip = <&cpu1_alert0>; 5437 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5438 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5439 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5440 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5441 }; 5442 map1 { 5443 trip = <&cpu1_alert1>; 5444 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5445 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5448 }; 5449 }; 5450 }; 5451 5452 cpu2-thermal { 5453 polling-delay-passive = <250>; 5454 polling-delay = <0>; 5455 5456 thermal-sensors = <&tsens0 3>; 5457 5458 trips { 5459 cpu2_alert0: trip-point0 { 5460 temperature = <90000>; 5461 hysteresis = <2000>; 5462 type = "passive"; 5463 }; 5464 5465 cpu2_alert1: trip-point1 { 5466 temperature = <95000>; 5467 hysteresis = <2000>; 5468 type = "passive"; 5469 }; 5470 5471 cpu2_crit: cpu-crit { 5472 temperature = <110000>; 5473 hysteresis = <0>; 5474 type = "critical"; 5475 }; 5476 }; 5477 5478 cooling-maps { 5479 map0 { 5480 trip = <&cpu2_alert0>; 5481 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5482 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5483 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5484 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5485 }; 5486 map1 { 5487 trip = <&cpu2_alert1>; 5488 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5489 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5492 }; 5493 }; 5494 }; 5495 5496 cpu3-thermal { 5497 polling-delay-passive = <250>; 5498 polling-delay = <0>; 5499 5500 thermal-sensors = <&tsens0 4>; 5501 5502 trips { 5503 cpu3_alert0: trip-point0 { 5504 temperature = <90000>; 5505 hysteresis = <2000>; 5506 type = "passive"; 5507 }; 5508 5509 cpu3_alert1: trip-point1 { 5510 temperature = <95000>; 5511 hysteresis = <2000>; 5512 type = "passive"; 5513 }; 5514 5515 cpu3_crit: cpu-crit { 5516 temperature = <110000>; 5517 hysteresis = <0>; 5518 type = "critical"; 5519 }; 5520 }; 5521 5522 cooling-maps { 5523 map0 { 5524 trip = <&cpu3_alert0>; 5525 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5526 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5527 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5528 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5529 }; 5530 map1 { 5531 trip = <&cpu3_alert1>; 5532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5536 }; 5537 }; 5538 }; 5539 5540 cpu4-thermal { 5541 polling-delay-passive = <250>; 5542 polling-delay = <0>; 5543 5544 thermal-sensors = <&tsens0 7>; 5545 5546 trips { 5547 cpu4_alert0: trip-point0 { 5548 temperature = <90000>; 5549 hysteresis = <2000>; 5550 type = "passive"; 5551 }; 5552 5553 cpu4_alert1: trip-point1 { 5554 temperature = <95000>; 5555 hysteresis = <2000>; 5556 type = "passive"; 5557 }; 5558 5559 cpu4_crit: cpu-crit { 5560 temperature = <110000>; 5561 hysteresis = <0>; 5562 type = "critical"; 5563 }; 5564 }; 5565 5566 cooling-maps { 5567 map0 { 5568 trip = <&cpu4_alert0>; 5569 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5570 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5571 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5572 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5573 }; 5574 map1 { 5575 trip = <&cpu4_alert1>; 5576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5580 }; 5581 }; 5582 }; 5583 5584 cpu5-thermal { 5585 polling-delay-passive = <250>; 5586 polling-delay = <0>; 5587 5588 thermal-sensors = <&tsens0 8>; 5589 5590 trips { 5591 cpu5_alert0: trip-point0 { 5592 temperature = <90000>; 5593 hysteresis = <2000>; 5594 type = "passive"; 5595 }; 5596 5597 cpu5_alert1: trip-point1 { 5598 temperature = <95000>; 5599 hysteresis = <2000>; 5600 type = "passive"; 5601 }; 5602 5603 cpu5_crit: cpu-crit { 5604 temperature = <110000>; 5605 hysteresis = <0>; 5606 type = "critical"; 5607 }; 5608 }; 5609 5610 cooling-maps { 5611 map0 { 5612 trip = <&cpu5_alert0>; 5613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5614 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5615 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5616 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5617 }; 5618 map1 { 5619 trip = <&cpu5_alert1>; 5620 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5621 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5624 }; 5625 }; 5626 }; 5627 5628 cpu6-thermal { 5629 polling-delay-passive = <250>; 5630 polling-delay = <0>; 5631 5632 thermal-sensors = <&tsens0 9>; 5633 5634 trips { 5635 cpu6_alert0: trip-point0 { 5636 temperature = <90000>; 5637 hysteresis = <2000>; 5638 type = "passive"; 5639 }; 5640 5641 cpu6_alert1: trip-point1 { 5642 temperature = <95000>; 5643 hysteresis = <2000>; 5644 type = "passive"; 5645 }; 5646 5647 cpu6_crit: cpu-crit { 5648 temperature = <110000>; 5649 hysteresis = <0>; 5650 type = "critical"; 5651 }; 5652 }; 5653 5654 cooling-maps { 5655 map0 { 5656 trip = <&cpu6_alert0>; 5657 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5659 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5660 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5661 }; 5662 map1 { 5663 trip = <&cpu6_alert1>; 5664 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5665 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5668 }; 5669 }; 5670 }; 5671 5672 cpu7-thermal { 5673 polling-delay-passive = <250>; 5674 polling-delay = <0>; 5675 5676 thermal-sensors = <&tsens0 10>; 5677 5678 trips { 5679 cpu7_alert0: trip-point0 { 5680 temperature = <90000>; 5681 hysteresis = <2000>; 5682 type = "passive"; 5683 }; 5684 5685 cpu7_alert1: trip-point1 { 5686 temperature = <95000>; 5687 hysteresis = <2000>; 5688 type = "passive"; 5689 }; 5690 5691 cpu7_crit: cpu-crit { 5692 temperature = <110000>; 5693 hysteresis = <0>; 5694 type = "critical"; 5695 }; 5696 }; 5697 5698 cooling-maps { 5699 map0 { 5700 trip = <&cpu7_alert0>; 5701 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5702 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5703 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5704 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5705 }; 5706 map1 { 5707 trip = <&cpu7_alert1>; 5708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5712 }; 5713 }; 5714 }; 5715 5716 cpu8-thermal { 5717 polling-delay-passive = <250>; 5718 polling-delay = <0>; 5719 5720 thermal-sensors = <&tsens0 11>; 5721 5722 trips { 5723 cpu8_alert0: trip-point0 { 5724 temperature = <90000>; 5725 hysteresis = <2000>; 5726 type = "passive"; 5727 }; 5728 5729 cpu8_alert1: trip-point1 { 5730 temperature = <95000>; 5731 hysteresis = <2000>; 5732 type = "passive"; 5733 }; 5734 5735 cpu8_crit: cpu-crit { 5736 temperature = <110000>; 5737 hysteresis = <0>; 5738 type = "critical"; 5739 }; 5740 }; 5741 5742 cooling-maps { 5743 map0 { 5744 trip = <&cpu8_alert0>; 5745 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5746 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5747 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5748 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5749 }; 5750 map1 { 5751 trip = <&cpu8_alert1>; 5752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5756 }; 5757 }; 5758 }; 5759 5760 cpu9-thermal { 5761 polling-delay-passive = <250>; 5762 polling-delay = <0>; 5763 5764 thermal-sensors = <&tsens0 12>; 5765 5766 trips { 5767 cpu9_alert0: trip-point0 { 5768 temperature = <90000>; 5769 hysteresis = <2000>; 5770 type = "passive"; 5771 }; 5772 5773 cpu9_alert1: trip-point1 { 5774 temperature = <95000>; 5775 hysteresis = <2000>; 5776 type = "passive"; 5777 }; 5778 5779 cpu9_crit: cpu-crit { 5780 temperature = <110000>; 5781 hysteresis = <0>; 5782 type = "critical"; 5783 }; 5784 }; 5785 5786 cooling-maps { 5787 map0 { 5788 trip = <&cpu9_alert0>; 5789 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5790 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5791 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5792 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5793 }; 5794 map1 { 5795 trip = <&cpu9_alert1>; 5796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5800 }; 5801 }; 5802 }; 5803 5804 cpu10-thermal { 5805 polling-delay-passive = <250>; 5806 polling-delay = <0>; 5807 5808 thermal-sensors = <&tsens0 13>; 5809 5810 trips { 5811 cpu10_alert0: trip-point0 { 5812 temperature = <90000>; 5813 hysteresis = <2000>; 5814 type = "passive"; 5815 }; 5816 5817 cpu10_alert1: trip-point1 { 5818 temperature = <95000>; 5819 hysteresis = <2000>; 5820 type = "passive"; 5821 }; 5822 5823 cpu10_crit: cpu-crit { 5824 temperature = <110000>; 5825 hysteresis = <0>; 5826 type = "critical"; 5827 }; 5828 }; 5829 5830 cooling-maps { 5831 map0 { 5832 trip = <&cpu10_alert0>; 5833 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5834 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5835 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5836 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5837 }; 5838 map1 { 5839 trip = <&cpu10_alert1>; 5840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5841 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5844 }; 5845 }; 5846 }; 5847 5848 cpu11-thermal { 5849 polling-delay-passive = <250>; 5850 polling-delay = <0>; 5851 5852 thermal-sensors = <&tsens0 14>; 5853 5854 trips { 5855 cpu11_alert0: trip-point0 { 5856 temperature = <90000>; 5857 hysteresis = <2000>; 5858 type = "passive"; 5859 }; 5860 5861 cpu11_alert1: trip-point1 { 5862 temperature = <95000>; 5863 hysteresis = <2000>; 5864 type = "passive"; 5865 }; 5866 5867 cpu11_crit: cpu-crit { 5868 temperature = <110000>; 5869 hysteresis = <0>; 5870 type = "critical"; 5871 }; 5872 }; 5873 5874 cooling-maps { 5875 map0 { 5876 trip = <&cpu11_alert0>; 5877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5878 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5879 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5880 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5881 }; 5882 map1 { 5883 trip = <&cpu11_alert1>; 5884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5886 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5888 }; 5889 }; 5890 }; 5891 5892 aoss0-thermal { 5893 polling-delay-passive = <0>; 5894 polling-delay = <0>; 5895 5896 thermal-sensors = <&tsens0 0>; 5897 5898 trips { 5899 aoss0_alert0: trip-point0 { 5900 temperature = <90000>; 5901 hysteresis = <2000>; 5902 type = "hot"; 5903 }; 5904 5905 aoss0_crit: aoss0-crit { 5906 temperature = <110000>; 5907 hysteresis = <0>; 5908 type = "critical"; 5909 }; 5910 }; 5911 }; 5912 5913 aoss1-thermal { 5914 polling-delay-passive = <0>; 5915 polling-delay = <0>; 5916 5917 thermal-sensors = <&tsens1 0>; 5918 5919 trips { 5920 aoss1_alert0: trip-point0 { 5921 temperature = <90000>; 5922 hysteresis = <2000>; 5923 type = "hot"; 5924 }; 5925 5926 aoss1_crit: aoss1-crit { 5927 temperature = <110000>; 5928 hysteresis = <0>; 5929 type = "critical"; 5930 }; 5931 }; 5932 }; 5933 5934 cpuss0-thermal { 5935 polling-delay-passive = <0>; 5936 polling-delay = <0>; 5937 5938 thermal-sensors = <&tsens0 5>; 5939 5940 trips { 5941 cpuss0_alert0: trip-point0 { 5942 temperature = <90000>; 5943 hysteresis = <2000>; 5944 type = "hot"; 5945 }; 5946 cpuss0_crit: cluster0-crit { 5947 temperature = <110000>; 5948 hysteresis = <0>; 5949 type = "critical"; 5950 }; 5951 }; 5952 }; 5953 5954 cpuss1-thermal { 5955 polling-delay-passive = <0>; 5956 polling-delay = <0>; 5957 5958 thermal-sensors = <&tsens0 6>; 5959 5960 trips { 5961 cpuss1_alert0: trip-point0 { 5962 temperature = <90000>; 5963 hysteresis = <2000>; 5964 type = "hot"; 5965 }; 5966 cpuss1_crit: cluster0-crit { 5967 temperature = <110000>; 5968 hysteresis = <0>; 5969 type = "critical"; 5970 }; 5971 }; 5972 }; 5973 5974 gpuss0-thermal { 5975 polling-delay-passive = <100>; 5976 polling-delay = <0>; 5977 5978 thermal-sensors = <&tsens1 1>; 5979 5980 trips { 5981 gpuss0_alert0: trip-point0 { 5982 temperature = <95000>; 5983 hysteresis = <2000>; 5984 type = "passive"; 5985 }; 5986 5987 gpuss0_crit: gpuss0-crit { 5988 temperature = <110000>; 5989 hysteresis = <0>; 5990 type = "critical"; 5991 }; 5992 }; 5993 5994 cooling-maps { 5995 map0 { 5996 trip = <&gpuss0_alert0>; 5997 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5998 }; 5999 }; 6000 }; 6001 6002 gpuss1-thermal { 6003 polling-delay-passive = <100>; 6004 polling-delay = <0>; 6005 6006 thermal-sensors = <&tsens1 2>; 6007 6008 trips { 6009 gpuss1_alert0: trip-point0 { 6010 temperature = <95000>; 6011 hysteresis = <2000>; 6012 type = "passive"; 6013 }; 6014 6015 gpuss1_crit: gpuss1-crit { 6016 temperature = <110000>; 6017 hysteresis = <0>; 6018 type = "critical"; 6019 }; 6020 }; 6021 6022 cooling-maps { 6023 map0 { 6024 trip = <&gpuss1_alert0>; 6025 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6026 }; 6027 }; 6028 }; 6029 6030 nspss0-thermal { 6031 polling-delay-passive = <0>; 6032 polling-delay = <0>; 6033 6034 thermal-sensors = <&tsens1 3>; 6035 6036 trips { 6037 nspss0_alert0: trip-point0 { 6038 temperature = <90000>; 6039 hysteresis = <2000>; 6040 type = "hot"; 6041 }; 6042 6043 nspss0_crit: nspss0-crit { 6044 temperature = <110000>; 6045 hysteresis = <0>; 6046 type = "critical"; 6047 }; 6048 }; 6049 }; 6050 6051 nspss1-thermal { 6052 polling-delay-passive = <0>; 6053 polling-delay = <0>; 6054 6055 thermal-sensors = <&tsens1 4>; 6056 6057 trips { 6058 nspss1_alert0: trip-point0 { 6059 temperature = <90000>; 6060 hysteresis = <2000>; 6061 type = "hot"; 6062 }; 6063 6064 nspss1_crit: nspss1-crit { 6065 temperature = <110000>; 6066 hysteresis = <0>; 6067 type = "critical"; 6068 }; 6069 }; 6070 }; 6071 6072 video-thermal { 6073 polling-delay-passive = <0>; 6074 polling-delay = <0>; 6075 6076 thermal-sensors = <&tsens1 5>; 6077 6078 trips { 6079 video_alert0: trip-point0 { 6080 temperature = <90000>; 6081 hysteresis = <2000>; 6082 type = "hot"; 6083 }; 6084 6085 video_crit: video-crit { 6086 temperature = <110000>; 6087 hysteresis = <0>; 6088 type = "critical"; 6089 }; 6090 }; 6091 }; 6092 6093 ddr-thermal { 6094 polling-delay-passive = <0>; 6095 polling-delay = <0>; 6096 6097 thermal-sensors = <&tsens1 6>; 6098 6099 trips { 6100 ddr_alert0: trip-point0 { 6101 temperature = <90000>; 6102 hysteresis = <2000>; 6103 type = "hot"; 6104 }; 6105 6106 ddr_crit: ddr-crit { 6107 temperature = <110000>; 6108 hysteresis = <0>; 6109 type = "critical"; 6110 }; 6111 }; 6112 }; 6113 6114 mdmss0-thermal { 6115 polling-delay-passive = <0>; 6116 polling-delay = <0>; 6117 6118 thermal-sensors = <&tsens1 7>; 6119 6120 trips { 6121 mdmss0_alert0: trip-point0 { 6122 temperature = <90000>; 6123 hysteresis = <2000>; 6124 type = "hot"; 6125 }; 6126 6127 mdmss0_crit: mdmss0-crit { 6128 temperature = <110000>; 6129 hysteresis = <0>; 6130 type = "critical"; 6131 }; 6132 }; 6133 }; 6134 6135 mdmss1-thermal { 6136 polling-delay-passive = <0>; 6137 polling-delay = <0>; 6138 6139 thermal-sensors = <&tsens1 8>; 6140 6141 trips { 6142 mdmss1_alert0: trip-point0 { 6143 temperature = <90000>; 6144 hysteresis = <2000>; 6145 type = "hot"; 6146 }; 6147 6148 mdmss1_crit: mdmss1-crit { 6149 temperature = <110000>; 6150 hysteresis = <0>; 6151 type = "critical"; 6152 }; 6153 }; 6154 }; 6155 6156 mdmss2-thermal { 6157 polling-delay-passive = <0>; 6158 polling-delay = <0>; 6159 6160 thermal-sensors = <&tsens1 9>; 6161 6162 trips { 6163 mdmss2_alert0: trip-point0 { 6164 temperature = <90000>; 6165 hysteresis = <2000>; 6166 type = "hot"; 6167 }; 6168 6169 mdmss2_crit: mdmss2-crit { 6170 temperature = <110000>; 6171 hysteresis = <0>; 6172 type = "critical"; 6173 }; 6174 }; 6175 }; 6176 6177 mdmss3-thermal { 6178 polling-delay-passive = <0>; 6179 polling-delay = <0>; 6180 6181 thermal-sensors = <&tsens1 10>; 6182 6183 trips { 6184 mdmss3_alert0: trip-point0 { 6185 temperature = <90000>; 6186 hysteresis = <2000>; 6187 type = "hot"; 6188 }; 6189 6190 mdmss3_crit: mdmss3-crit { 6191 temperature = <110000>; 6192 hysteresis = <0>; 6193 type = "critical"; 6194 }; 6195 }; 6196 }; 6197 6198 camera0-thermal { 6199 polling-delay-passive = <0>; 6200 polling-delay = <0>; 6201 6202 thermal-sensors = <&tsens1 11>; 6203 6204 trips { 6205 camera0_alert0: trip-point0 { 6206 temperature = <90000>; 6207 hysteresis = <2000>; 6208 type = "hot"; 6209 }; 6210 6211 camera0_crit: camera0-crit { 6212 temperature = <110000>; 6213 hysteresis = <0>; 6214 type = "critical"; 6215 }; 6216 }; 6217 }; 6218 }; 6219 6220 timer { 6221 compatible = "arm,armv8-timer"; 6222 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6223 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6224 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6225 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6226 }; 6227}; 6228