1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sc7280.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 i2c12 = &i2c12; 45 i2c13 = &i2c13; 46 i2c14 = &i2c14; 47 i2c15 = &i2c15; 48 mmc1 = &sdhc_1; 49 mmc2 = &sdhc_2; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 clocks { 69 xo_board: xo-board { 70 compatible = "fixed-clock"; 71 clock-frequency = <76800000>; 72 #clock-cells = <0>; 73 }; 74 75 sleep_clk: sleep-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 reserved-memory { 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges; 86 87 hyp_mem: memory@80000000 { 88 reg = <0x0 0x80000000 0x0 0x600000>; 89 no-map; 90 }; 91 92 xbl_mem: memory@80600000 { 93 reg = <0x0 0x80600000 0x0 0x200000>; 94 no-map; 95 }; 96 97 aop_mem: memory@80800000 { 98 reg = <0x0 0x80800000 0x0 0x60000>; 99 no-map; 100 }; 101 102 aop_cmd_db_mem: memory@80860000 { 103 reg = <0x0 0x80860000 0x0 0x20000>; 104 compatible = "qcom,cmd-db"; 105 no-map; 106 }; 107 108 reserved_xbl_uefi_log: memory@80880000 { 109 reg = <0x0 0x80884000 0x0 0x10000>; 110 no-map; 111 }; 112 113 sec_apps_mem: memory@808ff000 { 114 reg = <0x0 0x808ff000 0x0 0x1000>; 115 no-map; 116 }; 117 118 smem_mem: memory@80900000 { 119 reg = <0x0 0x80900000 0x0 0x200000>; 120 no-map; 121 }; 122 123 cpucp_mem: memory@80b00000 { 124 no-map; 125 reg = <0x0 0x80b00000 0x0 0x100000>; 126 }; 127 128 wlan_fw_mem: memory@80c00000 { 129 reg = <0x0 0x80c00000 0x0 0xc00000>; 130 no-map; 131 }; 132 133 video_mem: memory@8b200000 { 134 reg = <0x0 0x8b200000 0x0 0x500000>; 135 no-map; 136 }; 137 138 ipa_fw_mem: memory@8b700000 { 139 reg = <0 0x8b700000 0 0x10000>; 140 no-map; 141 }; 142 143 rmtfs_mem: memory@9c900000 { 144 compatible = "qcom,rmtfs-mem"; 145 reg = <0x0 0x9c900000 0x0 0x280000>; 146 no-map; 147 148 qcom,client-id = <1>; 149 qcom,vmid = <15>; 150 }; 151 }; 152 153 cpus { 154 #address-cells = <2>; 155 #size-cells = <0>; 156 157 CPU0: cpu@0 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x0>; 161 enable-method = "psci"; 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 163 &LITTLE_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_0>; 166 qcom,freq-domain = <&cpufreq_hw 0>; 167 #cooling-cells = <2>; 168 L2_0: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 L3_0: l3-cache { 172 compatible = "cache"; 173 }; 174 }; 175 }; 176 177 CPU1: cpu@100 { 178 device_type = "cpu"; 179 compatible = "arm,kryo"; 180 reg = <0x0 0x100>; 181 enable-method = "psci"; 182 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 183 &LITTLE_CPU_SLEEP_1 184 &CLUSTER_SLEEP_0>; 185 next-level-cache = <&L2_100>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 #cooling-cells = <2>; 188 L2_100: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU2: cpu@200 { 195 device_type = "cpu"; 196 compatible = "arm,kryo"; 197 reg = <0x0 0x200>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_200>; 203 qcom,freq-domain = <&cpufreq_hw 0>; 204 #cooling-cells = <2>; 205 L2_200: l2-cache { 206 compatible = "cache"; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU3: cpu@300 { 212 device_type = "cpu"; 213 compatible = "arm,kryo"; 214 reg = <0x0 0x300>; 215 enable-method = "psci"; 216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 217 &LITTLE_CPU_SLEEP_1 218 &CLUSTER_SLEEP_0>; 219 next-level-cache = <&L2_300>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_300: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU4: cpu@400 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x400>; 232 enable-method = "psci"; 233 cpu-idle-states = <&BIG_CPU_SLEEP_0 234 &BIG_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_400>; 237 qcom,freq-domain = <&cpufreq_hw 1>; 238 #cooling-cells = <2>; 239 L2_400: l2-cache { 240 compatible = "cache"; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 CPU5: cpu@500 { 246 device_type = "cpu"; 247 compatible = "arm,kryo"; 248 reg = <0x0 0x500>; 249 enable-method = "psci"; 250 cpu-idle-states = <&BIG_CPU_SLEEP_0 251 &BIG_CPU_SLEEP_1 252 &CLUSTER_SLEEP_0>; 253 next-level-cache = <&L2_500>; 254 qcom,freq-domain = <&cpufreq_hw 1>; 255 #cooling-cells = <2>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "arm,kryo"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 next-level-cache = <&L2_600>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 #cooling-cells = <2>; 273 L2_600: l2-cache { 274 compatible = "cache"; 275 next-level-cache = <&L3_0>; 276 }; 277 }; 278 279 CPU7: cpu@700 { 280 device_type = "cpu"; 281 compatible = "arm,kryo"; 282 reg = <0x0 0x700>; 283 enable-method = "psci"; 284 cpu-idle-states = <&BIG_CPU_SLEEP_0 285 &BIG_CPU_SLEEP_1 286 &CLUSTER_SLEEP_0>; 287 next-level-cache = <&L2_700>; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 #cooling-cells = <2>; 290 L2_700: l2-cache { 291 compatible = "cache"; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 cpu-map { 297 cluster0 { 298 core0 { 299 cpu = <&CPU0>; 300 }; 301 302 core1 { 303 cpu = <&CPU1>; 304 }; 305 306 core2 { 307 cpu = <&CPU2>; 308 }; 309 310 core3 { 311 cpu = <&CPU3>; 312 }; 313 314 core4 { 315 cpu = <&CPU4>; 316 }; 317 318 core5 { 319 cpu = <&CPU5>; 320 }; 321 322 core6 { 323 cpu = <&CPU6>; 324 }; 325 326 core7 { 327 cpu = <&CPU7>; 328 }; 329 }; 330 }; 331 332 idle-states { 333 entry-method = "psci"; 334 335 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "little-power-down"; 338 arm,psci-suspend-param = <0x40000003>; 339 entry-latency-us = <549>; 340 exit-latency-us = <901>; 341 min-residency-us = <1774>; 342 local-timer-stop; 343 }; 344 345 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-rail-power-down"; 348 arm,psci-suspend-param = <0x40000004>; 349 entry-latency-us = <702>; 350 exit-latency-us = <915>; 351 min-residency-us = <4001>; 352 local-timer-stop; 353 }; 354 355 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "big-power-down"; 358 arm,psci-suspend-param = <0x40000003>; 359 entry-latency-us = <523>; 360 exit-latency-us = <1244>; 361 min-residency-us = <2207>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-rail-power-down"; 368 arm,psci-suspend-param = <0x40000004>; 369 entry-latency-us = <526>; 370 exit-latency-us = <1854>; 371 min-residency-us = <5555>; 372 local-timer-stop; 373 }; 374 375 CLUSTER_SLEEP_0: cluster-sleep-0 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "cluster-power-down"; 378 arm,psci-suspend-param = <0x40003444>; 379 entry-latency-us = <3263>; 380 exit-latency-us = <6562>; 381 min-residency-us = <9926>; 382 local-timer-stop; 383 }; 384 }; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0 0x80000000 0 0>; 391 }; 392 393 firmware { 394 scm { 395 compatible = "qcom,scm-sc7280", "qcom,scm"; 396 }; 397 }; 398 399 clk_virt: interconnect { 400 compatible = "qcom,sc7280-clk-virt"; 401 #interconnect-cells = <2>; 402 qcom,bcm-voters = <&apps_bcm_voter>; 403 }; 404 405 smem { 406 compatible = "qcom,smem"; 407 memory-region = <&smem_mem>; 408 hwlocks = <&tcsr_mutex 3>; 409 }; 410 411 smp2p-adsp { 412 compatible = "qcom,smp2p"; 413 qcom,smem = <443>, <429>; 414 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 415 IPCC_MPROC_SIGNAL_SMP2P 416 IRQ_TYPE_EDGE_RISING>; 417 mboxes = <&ipcc IPCC_CLIENT_LPASS 418 IPCC_MPROC_SIGNAL_SMP2P>; 419 420 qcom,local-pid = <0>; 421 qcom,remote-pid = <2>; 422 423 adsp_smp2p_out: master-kernel { 424 qcom,entry-name = "master-kernel"; 425 #qcom,smem-state-cells = <1>; 426 }; 427 428 adsp_smp2p_in: slave-kernel { 429 qcom,entry-name = "slave-kernel"; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 }; 433 }; 434 435 smp2p-cdsp { 436 compatible = "qcom,smp2p"; 437 qcom,smem = <94>, <432>; 438 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 439 IPCC_MPROC_SIGNAL_SMP2P 440 IRQ_TYPE_EDGE_RISING>; 441 mboxes = <&ipcc IPCC_CLIENT_CDSP 442 IPCC_MPROC_SIGNAL_SMP2P>; 443 444 qcom,local-pid = <0>; 445 qcom,remote-pid = <5>; 446 447 cdsp_smp2p_out: master-kernel { 448 qcom,entry-name = "master-kernel"; 449 #qcom,smem-state-cells = <1>; 450 }; 451 452 cdsp_smp2p_in: slave-kernel { 453 qcom,entry-name = "slave-kernel"; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smp2p-mpss { 460 compatible = "qcom,smp2p"; 461 qcom,smem = <435>, <428>; 462 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 463 IPCC_MPROC_SIGNAL_SMP2P 464 IRQ_TYPE_EDGE_RISING>; 465 mboxes = <&ipcc IPCC_CLIENT_MPSS 466 IPCC_MPROC_SIGNAL_SMP2P>; 467 468 qcom,local-pid = <0>; 469 qcom,remote-pid = <1>; 470 471 modem_smp2p_out: master-kernel { 472 qcom,entry-name = "master-kernel"; 473 #qcom,smem-state-cells = <1>; 474 }; 475 476 modem_smp2p_in: slave-kernel { 477 qcom,entry-name = "slave-kernel"; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 }; 481 482 ipa_smp2p_out: ipa-ap-to-modem { 483 qcom,entry-name = "ipa"; 484 #qcom,smem-state-cells = <1>; 485 }; 486 487 ipa_smp2p_in: ipa-modem-to-ap { 488 qcom,entry-name = "ipa"; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 }; 492 }; 493 494 smp2p-wpss { 495 compatible = "qcom,smp2p"; 496 qcom,smem = <617>, <616>; 497 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 498 IPCC_MPROC_SIGNAL_SMP2P 499 IRQ_TYPE_EDGE_RISING>; 500 mboxes = <&ipcc IPCC_CLIENT_WPSS 501 IPCC_MPROC_SIGNAL_SMP2P>; 502 503 qcom,local-pid = <0>; 504 qcom,remote-pid = <13>; 505 506 wpss_smp2p_out: master-kernel { 507 qcom,entry-name = "master-kernel"; 508 #qcom,smem-state-cells = <1>; 509 }; 510 511 wpss_smp2p_in: slave-kernel { 512 qcom,entry-name = "slave-kernel"; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 }; 517 518 pmu { 519 compatible = "arm,armv8-pmuv3"; 520 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 521 }; 522 523 psci { 524 compatible = "arm,psci-1.0"; 525 method = "smc"; 526 }; 527 528 qspi_opp_table: qspi-opp-table { 529 compatible = "operating-points-v2"; 530 531 opp-75000000 { 532 opp-hz = /bits/ 64 <75000000>; 533 required-opps = <&rpmhpd_opp_low_svs>; 534 }; 535 536 opp-150000000 { 537 opp-hz = /bits/ 64 <150000000>; 538 required-opps = <&rpmhpd_opp_svs>; 539 }; 540 541 opp-200000000 { 542 opp-hz = /bits/ 64 <200000000>; 543 required-opps = <&rpmhpd_opp_svs_l1>; 544 }; 545 546 opp-300000000 { 547 opp-hz = /bits/ 64 <300000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 }; 550 }; 551 552 qup_opp_table: qup-opp-table { 553 compatible = "operating-points-v2"; 554 555 opp-75000000 { 556 opp-hz = /bits/ 64 <75000000>; 557 required-opps = <&rpmhpd_opp_low_svs>; 558 }; 559 560 opp-100000000 { 561 opp-hz = /bits/ 64 <100000000>; 562 required-opps = <&rpmhpd_opp_svs>; 563 }; 564 565 opp-128000000 { 566 opp-hz = /bits/ 64 <128000000>; 567 required-opps = <&rpmhpd_opp_nom>; 568 }; 569 }; 570 571 soc: soc@0 { 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges = <0 0 0 0 0x10 0>; 575 dma-ranges = <0 0 0 0 0x10 0>; 576 compatible = "simple-bus"; 577 578 gcc: clock-controller@100000 { 579 compatible = "qcom,gcc-sc7280"; 580 reg = <0 0x00100000 0 0x1f0000>; 581 clocks = <&rpmhcc RPMH_CXO_CLK>, 582 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 583 <0>, <&pcie1_lane 0>, 584 <0>, <0>, <0>, <0>; 585 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 586 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 587 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 588 "ufs_phy_tx_symbol_0_clk", 589 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 590 #clock-cells = <1>; 591 #reset-cells = <1>; 592 #power-domain-cells = <1>; 593 }; 594 595 ipcc: mailbox@408000 { 596 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 597 reg = <0 0x00408000 0 0x1000>; 598 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-controller; 600 #interrupt-cells = <3>; 601 #mbox-cells = <2>; 602 }; 603 604 qfprom: efuse@784000 { 605 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 606 reg = <0 0x00784000 0 0xa20>, 607 <0 0x00780000 0 0xa20>, 608 <0 0x00782000 0 0x120>, 609 <0 0x00786000 0 0x1fff>; 610 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 611 clock-names = "core"; 612 power-domains = <&rpmhpd SC7280_MX>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 }; 616 617 sdhc_1: sdhci@7c4000 { 618 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 619 status = "disabled"; 620 621 reg = <0 0x007c4000 0 0x1000>, 622 <0 0x007c5000 0 0x1000>; 623 reg-names = "hc", "cqhci"; 624 625 iommus = <&apps_smmu 0xc0 0x0>; 626 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "hc_irq", "pwr_irq"; 629 630 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 631 <&gcc GCC_SDCC1_AHB_CLK>, 632 <&rpmhcc RPMH_CXO_CLK>; 633 clock-names = "core", "iface", "xo"; 634 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 635 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 636 interconnect-names = "sdhc-ddr","cpu-sdhc"; 637 power-domains = <&rpmhpd SC7280_CX>; 638 operating-points-v2 = <&sdhc1_opp_table>; 639 640 bus-width = <8>; 641 supports-cqe; 642 643 qcom,dll-config = <0x0007642c>; 644 qcom,ddr-config = <0x80040868>; 645 646 mmc-ddr-1_8v; 647 mmc-hs200-1_8v; 648 mmc-hs400-1_8v; 649 mmc-hs400-enhanced-strobe; 650 651 sdhc1_opp_table: opp-table { 652 compatible = "operating-points-v2"; 653 654 opp-100000000 { 655 opp-hz = /bits/ 64 <100000000>; 656 required-opps = <&rpmhpd_opp_low_svs>; 657 opp-peak-kBps = <1800000 400000>; 658 opp-avg-kBps = <100000 0>; 659 }; 660 661 opp-384000000 { 662 opp-hz = /bits/ 64 <384000000>; 663 required-opps = <&rpmhpd_opp_nom>; 664 opp-peak-kBps = <5400000 1600000>; 665 opp-avg-kBps = <390000 0>; 666 }; 667 }; 668 669 }; 670 671 qupv3_id_0: geniqup@9c0000 { 672 compatible = "qcom,geni-se-qup"; 673 reg = <0 0x009c0000 0 0x2000>; 674 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 675 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 676 clock-names = "m-ahb", "s-ahb"; 677 #address-cells = <2>; 678 #size-cells = <2>; 679 ranges; 680 iommus = <&apps_smmu 0x123 0x0>; 681 status = "disabled"; 682 683 i2c0: i2c@980000 { 684 compatible = "qcom,geni-i2c"; 685 reg = <0 0x00980000 0 0x4000>; 686 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 687 clock-names = "se"; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&qup_i2c0_data_clk>; 690 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 694 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 695 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 696 interconnect-names = "qup-core", "qup-config", 697 "qup-memory"; 698 status = "disabled"; 699 }; 700 701 spi0: spi@980000 { 702 compatible = "qcom,geni-spi"; 703 reg = <0 0x00980000 0 0x4000>; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 705 clock-names = "se"; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 708 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 power-domains = <&rpmhpd SC7280_CX>; 712 operating-points-v2 = <&qup_opp_table>; 713 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 715 interconnect-names = "qup-core", "qup-config"; 716 status = "disabled"; 717 }; 718 719 uart0: serial@980000 { 720 compatible = "qcom,geni-uart"; 721 reg = <0 0x00980000 0 0x4000>; 722 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 723 clock-names = "se"; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 726 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 727 power-domains = <&rpmhpd SC7280_CX>; 728 operating-points-v2 = <&qup_opp_table>; 729 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 730 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 731 interconnect-names = "qup-core", "qup-config"; 732 status = "disabled"; 733 }; 734 735 i2c1: i2c@984000 { 736 compatible = "qcom,geni-i2c"; 737 reg = <0 0x00984000 0 0x4000>; 738 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 739 clock-names = "se"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&qup_i2c1_data_clk>; 742 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 747 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 748 interconnect-names = "qup-core", "qup-config", 749 "qup-memory"; 750 status = "disabled"; 751 }; 752 753 spi1: spi@984000 { 754 compatible = "qcom,geni-spi"; 755 reg = <0 0x00984000 0 0x4000>; 756 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 757 clock-names = "se"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 760 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 power-domains = <&rpmhpd SC7280_CX>; 764 operating-points-v2 = <&qup_opp_table>; 765 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 766 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 767 interconnect-names = "qup-core", "qup-config"; 768 status = "disabled"; 769 }; 770 771 uart1: serial@984000 { 772 compatible = "qcom,geni-uart"; 773 reg = <0 0x00984000 0 0x4000>; 774 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 775 clock-names = "se"; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 778 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 779 power-domains = <&rpmhpd SC7280_CX>; 780 operating-points-v2 = <&qup_opp_table>; 781 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 782 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 783 interconnect-names = "qup-core", "qup-config"; 784 status = "disabled"; 785 }; 786 787 i2c2: i2c@988000 { 788 compatible = "qcom,geni-i2c"; 789 reg = <0 0x00988000 0 0x4000>; 790 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 791 clock-names = "se"; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_i2c2_data_clk>; 794 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 799 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 800 interconnect-names = "qup-core", "qup-config", 801 "qup-memory"; 802 status = "disabled"; 803 }; 804 805 spi2: spi@988000 { 806 compatible = "qcom,geni-spi"; 807 reg = <0 0x00988000 0 0x4000>; 808 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 809 clock-names = "se"; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 812 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 power-domains = <&rpmhpd SC7280_CX>; 816 operating-points-v2 = <&qup_opp_table>; 817 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 819 interconnect-names = "qup-core", "qup-config"; 820 status = "disabled"; 821 }; 822 823 uart2: serial@988000 { 824 compatible = "qcom,geni-uart"; 825 reg = <0 0x00988000 0 0x4000>; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 827 clock-names = "se"; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 830 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 831 power-domains = <&rpmhpd SC7280_CX>; 832 operating-points-v2 = <&qup_opp_table>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 status = "disabled"; 837 }; 838 839 i2c3: i2c@98c000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0 0x0098c000 0 0x4000>; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 843 clock-names = "se"; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&qup_i2c3_data_clk>; 846 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 850 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 851 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 852 interconnect-names = "qup-core", "qup-config", 853 "qup-memory"; 854 status = "disabled"; 855 }; 856 857 spi3: spi@98c000 { 858 compatible = "qcom,geni-spi"; 859 reg = <0 0x0098c000 0 0x4000>; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 861 clock-names = "se"; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 864 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 power-domains = <&rpmhpd SC7280_CX>; 868 operating-points-v2 = <&qup_opp_table>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 870 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 871 interconnect-names = "qup-core", "qup-config"; 872 status = "disabled"; 873 }; 874 875 uart3: serial@98c000 { 876 compatible = "qcom,geni-uart"; 877 reg = <0 0x0098c000 0 0x4000>; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 879 clock-names = "se"; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 882 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmhpd SC7280_CX>; 884 operating-points-v2 = <&qup_opp_table>; 885 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 886 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 887 interconnect-names = "qup-core", "qup-config"; 888 status = "disabled"; 889 }; 890 891 i2c4: i2c@990000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0 0x00990000 0 0x4000>; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 895 clock-names = "se"; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&qup_i2c4_data_clk>; 898 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 902 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 903 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 904 interconnect-names = "qup-core", "qup-config", 905 "qup-memory"; 906 status = "disabled"; 907 }; 908 909 spi4: spi@990000 { 910 compatible = "qcom,geni-spi"; 911 reg = <0 0x00990000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 913 clock-names = "se"; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 916 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 power-domains = <&rpmhpd SC7280_CX>; 920 operating-points-v2 = <&qup_opp_table>; 921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 923 interconnect-names = "qup-core", "qup-config"; 924 status = "disabled"; 925 }; 926 927 uart4: serial@990000 { 928 compatible = "qcom,geni-uart"; 929 reg = <0 0x00990000 0 0x4000>; 930 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 931 clock-names = "se"; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 934 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 935 power-domains = <&rpmhpd SC7280_CX>; 936 operating-points-v2 = <&qup_opp_table>; 937 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 939 interconnect-names = "qup-core", "qup-config"; 940 status = "disabled"; 941 }; 942 943 i2c5: i2c@994000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00994000 0 0x4000>; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 947 clock-names = "se"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_i2c5_data_clk>; 950 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 955 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 956 interconnect-names = "qup-core", "qup-config", 957 "qup-memory"; 958 status = "disabled"; 959 }; 960 961 spi5: spi@994000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0 0x00994000 0 0x4000>; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 965 clock-names = "se"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 968 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 power-domains = <&rpmhpd SC7280_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 uart5: serial@994000 { 980 compatible = "qcom,geni-uart"; 981 reg = <0 0x00994000 0 0x4000>; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 983 clock-names = "se"; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 986 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmhpd SC7280_CX>; 988 operating-points-v2 = <&qup_opp_table>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 status = "disabled"; 993 }; 994 995 i2c6: i2c@998000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00998000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c6_data_clk>; 1002 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", 1009 "qup-memory"; 1010 status = "disabled"; 1011 }; 1012 1013 spi6: spi@998000 { 1014 compatible = "qcom,geni-spi"; 1015 reg = <0 0x00998000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1017 clock-names = "se"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1020 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 power-domains = <&rpmhpd SC7280_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 1031 uart6: serial@998000 { 1032 compatible = "qcom,geni-uart"; 1033 reg = <0 0x00998000 0 0x4000>; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1035 clock-names = "se"; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1038 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1039 power-domains = <&rpmhpd SC7280_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1042 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1043 interconnect-names = "qup-core", "qup-config"; 1044 status = "disabled"; 1045 }; 1046 1047 i2c7: i2c@99c000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x0099c000 0 0x4000>; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1051 clock-names = "se"; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c7_data_clk>; 1054 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1059 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1060 interconnect-names = "qup-core", "qup-config", 1061 "qup-memory"; 1062 status = "disabled"; 1063 }; 1064 1065 spi7: spi@99c000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0 0x0099c000 0 0x4000>; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1069 clock-names = "se"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1072 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 power-domains = <&rpmhpd SC7280_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 status = "disabled"; 1081 }; 1082 1083 uart7: serial@99c000 { 1084 compatible = "qcom,geni-uart"; 1085 reg = <0 0x0099c000 0 0x4000>; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1087 clock-names = "se"; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1090 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SC7280_CX>; 1092 operating-points-v2 = <&qup_opp_table>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1095 interconnect-names = "qup-core", "qup-config"; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 qupv3_id_1: geniqup@ac0000 { 1101 compatible = "qcom,geni-se-qup"; 1102 reg = <0 0x00ac0000 0 0x2000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1104 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1105 clock-names = "m-ahb", "s-ahb"; 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 iommus = <&apps_smmu 0x43 0x0>; 1110 status = "disabled"; 1111 1112 i2c8: i2c@a80000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00a80000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c8_data_clk>; 1119 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1124 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", 1126 "qup-memory"; 1127 status = "disabled"; 1128 }; 1129 1130 spi8: spi@a80000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00a80000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1137 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SC7280_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 status = "disabled"; 1146 }; 1147 1148 uart8: serial@a80000 { 1149 compatible = "qcom,geni-uart"; 1150 reg = <0 0x00a80000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1152 clock-names = "se"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1155 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&rpmhpd SC7280_CX>; 1157 operating-points-v2 = <&qup_opp_table>; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c9: i2c@a84000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a84000 0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1168 clock-names = "se"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c9_data_clk>; 1171 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1176 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1177 interconnect-names = "qup-core", "qup-config", 1178 "qup-memory"; 1179 status = "disabled"; 1180 }; 1181 1182 spi9: spi@a84000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0 0x00a84000 0 0x4000>; 1185 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1186 clock-names = "se"; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1189 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 power-domains = <&rpmhpd SC7280_CX>; 1193 operating-points-v2 = <&qup_opp_table>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 uart9: serial@a84000 { 1201 compatible = "qcom,geni-uart"; 1202 reg = <0 0x00a84000 0 0x4000>; 1203 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1204 clock-names = "se"; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1208 power-domains = <&rpmhpd SC7280_CX>; 1209 operating-points-v2 = <&qup_opp_table>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1212 interconnect-names = "qup-core", "qup-config"; 1213 status = "disabled"; 1214 }; 1215 1216 i2c10: i2c@a88000 { 1217 compatible = "qcom,geni-i2c"; 1218 reg = <0 0x00a88000 0 0x4000>; 1219 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1220 clock-names = "se"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_i2c10_data_clk>; 1223 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1228 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1229 interconnect-names = "qup-core", "qup-config", 1230 "qup-memory"; 1231 status = "disabled"; 1232 }; 1233 1234 spi10: spi@a88000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0 0x00a88000 0 0x4000>; 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1238 clock-names = "se"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1241 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 power-domains = <&rpmhpd SC7280_CX>; 1245 operating-points-v2 = <&qup_opp_table>; 1246 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1247 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1248 interconnect-names = "qup-core", "qup-config"; 1249 status = "disabled"; 1250 }; 1251 1252 uart10: serial@a88000 { 1253 compatible = "qcom,geni-uart"; 1254 reg = <0 0x00a88000 0 0x4000>; 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1256 clock-names = "se"; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1259 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1260 power-domains = <&rpmhpd SC7280_CX>; 1261 operating-points-v2 = <&qup_opp_table>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 status = "disabled"; 1266 }; 1267 1268 i2c11: i2c@a8c000 { 1269 compatible = "qcom,geni-i2c"; 1270 reg = <0 0x00a8c000 0 0x4000>; 1271 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1272 clock-names = "se"; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_i2c11_data_clk>; 1275 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1280 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1281 interconnect-names = "qup-core", "qup-config", 1282 "qup-memory"; 1283 status = "disabled"; 1284 }; 1285 1286 spi11: spi@a8c000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00a8c000 0 0x4000>; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1290 clock-names = "se"; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1293 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 power-domains = <&rpmhpd SC7280_CX>; 1297 operating-points-v2 = <&qup_opp_table>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1300 interconnect-names = "qup-core", "qup-config"; 1301 status = "disabled"; 1302 }; 1303 1304 uart11: serial@a8c000 { 1305 compatible = "qcom,geni-uart"; 1306 reg = <0 0x00a8c000 0 0x4000>; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1308 clock-names = "se"; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1311 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd SC7280_CX>; 1313 operating-points-v2 = <&qup_opp_table>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1316 interconnect-names = "qup-core", "qup-config"; 1317 status = "disabled"; 1318 }; 1319 1320 i2c12: i2c@a90000 { 1321 compatible = "qcom,geni-i2c"; 1322 reg = <0 0x00a90000 0 0x4000>; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1324 clock-names = "se"; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_i2c12_data_clk>; 1327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1332 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", 1334 "qup-memory"; 1335 status = "disabled"; 1336 }; 1337 1338 spi12: spi@a90000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00a90000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1345 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 power-domains = <&rpmhpd SC7280_CX>; 1349 operating-points-v2 = <&qup_opp_table>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1351 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1352 interconnect-names = "qup-core", "qup-config"; 1353 status = "disabled"; 1354 }; 1355 1356 uart12: serial@a90000 { 1357 compatible = "qcom,geni-uart"; 1358 reg = <0 0x00a90000 0 0x4000>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1360 clock-names = "se"; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1363 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1364 power-domains = <&rpmhpd SC7280_CX>; 1365 operating-points-v2 = <&qup_opp_table>; 1366 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1367 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 status = "disabled"; 1370 }; 1371 1372 i2c13: i2c@a94000 { 1373 compatible = "qcom,geni-i2c"; 1374 reg = <0 0x00a94000 0 0x4000>; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1376 clock-names = "se"; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&qup_i2c13_data_clk>; 1379 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1384 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1385 interconnect-names = "qup-core", "qup-config", 1386 "qup-memory"; 1387 status = "disabled"; 1388 }; 1389 1390 spi13: spi@a94000 { 1391 compatible = "qcom,geni-spi"; 1392 reg = <0 0x00a94000 0 0x4000>; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1394 clock-names = "se"; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1397 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 power-domains = <&rpmhpd SC7280_CX>; 1401 operating-points-v2 = <&qup_opp_table>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1404 interconnect-names = "qup-core", "qup-config"; 1405 status = "disabled"; 1406 }; 1407 1408 uart13: serial@a94000 { 1409 compatible = "qcom,geni-uart"; 1410 reg = <0 0x00a94000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1415 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1416 power-domains = <&rpmhpd SC7280_CX>; 1417 operating-points-v2 = <&qup_opp_table>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1420 interconnect-names = "qup-core", "qup-config"; 1421 status = "disabled"; 1422 }; 1423 1424 i2c14: i2c@a98000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0 0x00a98000 0 0x4000>; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1428 clock-names = "se"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_i2c14_data_clk>; 1431 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1435 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1436 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1437 interconnect-names = "qup-core", "qup-config", 1438 "qup-memory"; 1439 status = "disabled"; 1440 }; 1441 1442 spi14: spi@a98000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a98000 0 0x4000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1446 clock-names = "se"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1449 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 power-domains = <&rpmhpd SC7280_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 uart14: serial@a98000 { 1461 compatible = "qcom,geni-uart"; 1462 reg = <0 0x00a98000 0 0x4000>; 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1464 clock-names = "se"; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1467 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&rpmhpd SC7280_CX>; 1469 operating-points-v2 = <&qup_opp_table>; 1470 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 status = "disabled"; 1474 }; 1475 1476 i2c15: i2c@a9c000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0 0x00a9c000 0 0x4000>; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1480 clock-names = "se"; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_i2c15_data_clk>; 1483 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1488 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", 1490 "qup-memory"; 1491 status = "disabled"; 1492 }; 1493 1494 spi15: spi@a9c000 { 1495 compatible = "qcom,geni-spi"; 1496 reg = <0 0x00a9c000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1501 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 power-domains = <&rpmhpd SC7280_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1508 interconnect-names = "qup-core", "qup-config"; 1509 status = "disabled"; 1510 }; 1511 1512 uart15: serial@a9c000 { 1513 compatible = "qcom,geni-uart"; 1514 reg = <0 0x00a9c000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1519 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC7280_CX>; 1521 operating-points-v2 = <&qup_opp_table>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 }; 1528 1529 cnoc2: interconnect@1500000 { 1530 reg = <0 0x01500000 0 0x1000>; 1531 compatible = "qcom,sc7280-cnoc2"; 1532 #interconnect-cells = <2>; 1533 qcom,bcm-voters = <&apps_bcm_voter>; 1534 }; 1535 1536 cnoc3: interconnect@1502000 { 1537 reg = <0 0x01502000 0 0x1000>; 1538 compatible = "qcom,sc7280-cnoc3"; 1539 #interconnect-cells = <2>; 1540 qcom,bcm-voters = <&apps_bcm_voter>; 1541 }; 1542 1543 mc_virt: interconnect@1580000 { 1544 reg = <0 0x01580000 0 0x4>; 1545 compatible = "qcom,sc7280-mc-virt"; 1546 #interconnect-cells = <2>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 system_noc: interconnect@1680000 { 1551 reg = <0 0x01680000 0 0x15480>; 1552 compatible = "qcom,sc7280-system-noc"; 1553 #interconnect-cells = <2>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 aggre1_noc: interconnect@16e0000 { 1558 compatible = "qcom,sc7280-aggre1-noc"; 1559 reg = <0 0x016e0000 0 0x1c080>; 1560 #interconnect-cells = <2>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 aggre2_noc: interconnect@1700000 { 1565 reg = <0 0x01700000 0 0x2b080>; 1566 compatible = "qcom,sc7280-aggre2-noc"; 1567 #interconnect-cells = <2>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 mmss_noc: interconnect@1740000 { 1572 reg = <0 0x01740000 0 0x1e080>; 1573 compatible = "qcom,sc7280-mmss-noc"; 1574 #interconnect-cells = <2>; 1575 qcom,bcm-voters = <&apps_bcm_voter>; 1576 }; 1577 1578 pcie1: pci@1c08000 { 1579 compatible = "qcom,pcie-sc7280"; 1580 reg = <0 0x01c08000 0 0x3000>, 1581 <0 0x40000000 0 0xf1d>, 1582 <0 0x40000f20 0 0xa8>, 1583 <0 0x40001000 0 0x1000>, 1584 <0 0x40100000 0 0x100000>; 1585 1586 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1587 device_type = "pci"; 1588 linux,pci-domain = <1>; 1589 bus-range = <0x00 0xff>; 1590 num-lanes = <2>; 1591 1592 #address-cells = <3>; 1593 #size-cells = <2>; 1594 1595 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1596 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1597 1598 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1599 interrupt-names = "msi"; 1600 #interrupt-cells = <1>; 1601 interrupt-map-mask = <0 0 0 0x7>; 1602 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1604 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1605 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1606 1607 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1608 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1609 <&pcie1_lane 0>, 1610 <&rpmhcc RPMH_CXO_CLK>, 1611 <&gcc GCC_PCIE_1_AUX_CLK>, 1612 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1613 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1615 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1616 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1617 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1618 1619 clock-names = "pipe", 1620 "pipe_mux", 1621 "phy_pipe", 1622 "ref", 1623 "aux", 1624 "cfg", 1625 "bus_master", 1626 "bus_slave", 1627 "slave_q2a", 1628 "tbu", 1629 "ddrss_sf_tbu"; 1630 1631 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1632 assigned-clock-rates = <19200000>; 1633 1634 resets = <&gcc GCC_PCIE_1_BCR>; 1635 reset-names = "pci"; 1636 1637 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1638 1639 phys = <&pcie1_lane>; 1640 phy-names = "pciephy"; 1641 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&pcie1_clkreq_n>; 1644 1645 iommus = <&apps_smmu 0x1c80 0x1>; 1646 1647 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1648 <0x100 &apps_smmu 0x1c81 0x1>; 1649 1650 status = "disabled"; 1651 }; 1652 1653 pcie1_phy: phy@1c0e000 { 1654 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1655 reg = <0 0x01c0e000 0 0x1c0>; 1656 #address-cells = <2>; 1657 #size-cells = <2>; 1658 ranges; 1659 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1660 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1661 <&gcc GCC_PCIE_CLKREF_EN>, 1662 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1663 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1664 1665 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1666 reset-names = "phy"; 1667 1668 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1669 assigned-clock-rates = <100000000>; 1670 1671 status = "disabled"; 1672 1673 pcie1_lane: lanes@1c0e200 { 1674 reg = <0 0x01c0e200 0 0x170>, 1675 <0 0x01c0e400 0 0x200>, 1676 <0 0x01c0ea00 0 0x1f0>, 1677 <0 0x01c0e600 0 0x170>, 1678 <0 0x01c0e800 0 0x200>, 1679 <0 0x01c0ee00 0 0xf4>; 1680 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1681 clock-names = "pipe0"; 1682 1683 #phy-cells = <0>; 1684 #clock-cells = <1>; 1685 clock-output-names = "pcie_1_pipe_clk"; 1686 }; 1687 }; 1688 1689 ipa: ipa@1e40000 { 1690 compatible = "qcom,sc7280-ipa"; 1691 1692 iommus = <&apps_smmu 0x480 0x0>, 1693 <&apps_smmu 0x482 0x0>; 1694 reg = <0 0x1e40000 0 0x8000>, 1695 <0 0x1e50000 0 0x4ad0>, 1696 <0 0x1e04000 0 0x23000>; 1697 reg-names = "ipa-reg", 1698 "ipa-shared", 1699 "gsi"; 1700 1701 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1702 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1703 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1704 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1705 interrupt-names = "ipa", 1706 "gsi", 1707 "ipa-clock-query", 1708 "ipa-setup-ready"; 1709 1710 clocks = <&rpmhcc RPMH_IPA_CLK>; 1711 clock-names = "core"; 1712 1713 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1715 interconnect-names = "memory", 1716 "config"; 1717 1718 qcom,qmp = <&aoss_qmp>; 1719 1720 qcom,smem-states = <&ipa_smp2p_out 0>, 1721 <&ipa_smp2p_out 1>; 1722 qcom,smem-state-names = "ipa-clock-enabled-valid", 1723 "ipa-clock-enabled"; 1724 1725 status = "disabled"; 1726 }; 1727 1728 tcsr_mutex: hwlock@1f40000 { 1729 compatible = "qcom,tcsr-mutex", "syscon"; 1730 reg = <0 0x01f40000 0 0x40000>; 1731 #hwlock-cells = <1>; 1732 }; 1733 1734 tcsr: syscon@1fc0000 { 1735 compatible = "qcom,sc7280-tcsr", "syscon"; 1736 reg = <0 0x01fc0000 0 0x30000>; 1737 }; 1738 1739 lpasscc: lpasscc@3000000 { 1740 compatible = "qcom,sc7280-lpasscc"; 1741 reg = <0 0x03000000 0 0x40>, 1742 <0 0x03c04000 0 0x4>, 1743 <0 0x03389000 0 0x24>; 1744 reg-names = "qdsp6ss", "top_cc", "cc"; 1745 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1746 clock-names = "iface"; 1747 #clock-cells = <1>; 1748 }; 1749 1750 lpass_ag_noc: interconnect@3c40000 { 1751 reg = <0 0x03c40000 0 0xf080>; 1752 compatible = "qcom,sc7280-lpass-ag-noc"; 1753 #interconnect-cells = <2>; 1754 qcom,bcm-voters = <&apps_bcm_voter>; 1755 }; 1756 1757 gpu: gpu@3d00000 { 1758 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1759 reg = <0 0x03d00000 0 0x40000>, 1760 <0 0x03d9e000 0 0x1000>, 1761 <0 0x03d61000 0 0x800>; 1762 reg-names = "kgsl_3d0_reg_memory", 1763 "cx_mem", 1764 "cx_dbgc"; 1765 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1766 iommus = <&adreno_smmu 0 0x401>; 1767 operating-points-v2 = <&gpu_opp_table>; 1768 qcom,gmu = <&gmu>; 1769 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1770 interconnect-names = "gfx-mem"; 1771 #cooling-cells = <2>; 1772 1773 gpu_opp_table: opp-table { 1774 compatible = "operating-points-v2"; 1775 1776 opp-315000000 { 1777 opp-hz = /bits/ 64 <315000000>; 1778 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1779 opp-peak-kBps = <1804000>; 1780 }; 1781 1782 opp-450000000 { 1783 opp-hz = /bits/ 64 <450000000>; 1784 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1785 opp-peak-kBps = <4068000>; 1786 }; 1787 1788 opp-550000000 { 1789 opp-hz = /bits/ 64 <550000000>; 1790 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1791 opp-peak-kBps = <6832000>; 1792 }; 1793 }; 1794 }; 1795 1796 gmu: gmu@3d6a000 { 1797 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1798 reg = <0 0x03d6a000 0 0x34000>, 1799 <0 0x3de0000 0 0x10000>, 1800 <0 0x0b290000 0 0x10000>; 1801 reg-names = "gmu", "rscc", "gmu_pdc"; 1802 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1804 interrupt-names = "hfi", "gmu"; 1805 clocks = <&gpucc 5>, 1806 <&gpucc 8>, 1807 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1808 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1809 <&gpucc 2>, 1810 <&gpucc 15>, 1811 <&gpucc 11>; 1812 clock-names = "gmu", 1813 "cxo", 1814 "axi", 1815 "memnoc", 1816 "ahb", 1817 "hub", 1818 "smmu_vote"; 1819 power-domains = <&gpucc 0>, 1820 <&gpucc 1>; 1821 power-domain-names = "cx", 1822 "gx"; 1823 iommus = <&adreno_smmu 5 0x400>; 1824 operating-points-v2 = <&gmu_opp_table>; 1825 1826 gmu_opp_table: opp-table { 1827 compatible = "operating-points-v2"; 1828 1829 opp-200000000 { 1830 opp-hz = /bits/ 64 <200000000>; 1831 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1832 }; 1833 }; 1834 }; 1835 1836 gpucc: clock-controller@3d90000 { 1837 compatible = "qcom,sc7280-gpucc"; 1838 reg = <0 0x03d90000 0 0x9000>; 1839 clocks = <&rpmhcc RPMH_CXO_CLK>, 1840 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1841 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1842 clock-names = "bi_tcxo", 1843 "gcc_gpu_gpll0_clk_src", 1844 "gcc_gpu_gpll0_div_clk_src"; 1845 #clock-cells = <1>; 1846 #reset-cells = <1>; 1847 #power-domain-cells = <1>; 1848 }; 1849 1850 adreno_smmu: iommu@3da0000 { 1851 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1852 reg = <0 0x03da0000 0 0x20000>; 1853 #iommu-cells = <2>; 1854 #global-interrupts = <2>; 1855 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1867 1868 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1869 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1870 <&gpucc 2>, 1871 <&gpucc 11>, 1872 <&gpucc 5>, 1873 <&gpucc 15>, 1874 <&gpucc 13>; 1875 clock-names = "gcc_gpu_memnoc_gfx_clk", 1876 "gcc_gpu_snoc_dvm_gfx_clk", 1877 "gpu_cc_ahb_clk", 1878 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1879 "gpu_cc_cx_gmu_clk", 1880 "gpu_cc_hub_cx_int_clk", 1881 "gpu_cc_hub_aon_clk"; 1882 1883 power-domains = <&gpucc 0>; 1884 }; 1885 1886 remoteproc_mpss: remoteproc@4080000 { 1887 compatible = "qcom,sc7280-mpss-pas"; 1888 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1889 reg-names = "qdsp6", "rmb"; 1890 1891 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1894 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1895 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1896 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1897 interrupt-names = "wdog", "fatal", "ready", "handover", 1898 "stop-ack", "shutdown-ack"; 1899 1900 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1901 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1902 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1903 <&rpmhcc RPMH_PKA_CLK>, 1904 <&rpmhcc RPMH_CXO_CLK>; 1905 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1906 1907 power-domains = <&rpmhpd SC7280_CX>, 1908 <&rpmhpd SC7280_MSS>; 1909 power-domain-names = "cx", "mss"; 1910 1911 memory-region = <&mpss_mem>; 1912 1913 qcom,qmp = <&aoss_qmp>; 1914 1915 qcom,smem-states = <&modem_smp2p_out 0>; 1916 qcom,smem-state-names = "stop"; 1917 1918 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1919 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1920 reset-names = "mss_restart", "pdc_reset"; 1921 1922 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1923 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1924 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1925 1926 status = "disabled"; 1927 1928 glink-edge { 1929 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1930 IPCC_MPROC_SIGNAL_GLINK_QMP 1931 IRQ_TYPE_EDGE_RISING>; 1932 mboxes = <&ipcc IPCC_CLIENT_MPSS 1933 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1934 label = "modem"; 1935 qcom,remote-pid = <1>; 1936 }; 1937 }; 1938 1939 stm@6002000 { 1940 compatible = "arm,coresight-stm", "arm,primecell"; 1941 reg = <0 0x06002000 0 0x1000>, 1942 <0 0x16280000 0 0x180000>; 1943 reg-names = "stm-base", "stm-stimulus-base"; 1944 1945 clocks = <&aoss_qmp>; 1946 clock-names = "apb_pclk"; 1947 1948 out-ports { 1949 port { 1950 stm_out: endpoint { 1951 remote-endpoint = <&funnel0_in7>; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 funnel@6041000 { 1958 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1959 reg = <0 0x06041000 0 0x1000>; 1960 1961 clocks = <&aoss_qmp>; 1962 clock-names = "apb_pclk"; 1963 1964 out-ports { 1965 port { 1966 funnel0_out: endpoint { 1967 remote-endpoint = <&merge_funnel_in0>; 1968 }; 1969 }; 1970 }; 1971 1972 in-ports { 1973 #address-cells = <1>; 1974 #size-cells = <0>; 1975 1976 port@7 { 1977 reg = <7>; 1978 funnel0_in7: endpoint { 1979 remote-endpoint = <&stm_out>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 funnel@6042000 { 1986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1987 reg = <0 0x06042000 0 0x1000>; 1988 1989 clocks = <&aoss_qmp>; 1990 clock-names = "apb_pclk"; 1991 1992 out-ports { 1993 port { 1994 funnel1_out: endpoint { 1995 remote-endpoint = <&merge_funnel_in1>; 1996 }; 1997 }; 1998 }; 1999 2000 in-ports { 2001 #address-cells = <1>; 2002 #size-cells = <0>; 2003 2004 port@4 { 2005 reg = <4>; 2006 funnel1_in4: endpoint { 2007 remote-endpoint = <&apss_merge_funnel_out>; 2008 }; 2009 }; 2010 }; 2011 }; 2012 2013 funnel@6045000 { 2014 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2015 reg = <0 0x06045000 0 0x1000>; 2016 2017 clocks = <&aoss_qmp>; 2018 clock-names = "apb_pclk"; 2019 2020 out-ports { 2021 port { 2022 merge_funnel_out: endpoint { 2023 remote-endpoint = <&swao_funnel_in>; 2024 }; 2025 }; 2026 }; 2027 2028 in-ports { 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 2032 port@0 { 2033 reg = <0>; 2034 merge_funnel_in0: endpoint { 2035 remote-endpoint = <&funnel0_out>; 2036 }; 2037 }; 2038 2039 port@1 { 2040 reg = <1>; 2041 merge_funnel_in1: endpoint { 2042 remote-endpoint = <&funnel1_out>; 2043 }; 2044 }; 2045 }; 2046 }; 2047 2048 replicator@6046000 { 2049 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2050 reg = <0 0x06046000 0 0x1000>; 2051 2052 clocks = <&aoss_qmp>; 2053 clock-names = "apb_pclk"; 2054 2055 out-ports { 2056 port { 2057 replicator_out: endpoint { 2058 remote-endpoint = <&etr_in>; 2059 }; 2060 }; 2061 }; 2062 2063 in-ports { 2064 port { 2065 replicator_in: endpoint { 2066 remote-endpoint = <&swao_replicator_out>; 2067 }; 2068 }; 2069 }; 2070 }; 2071 2072 etr@6048000 { 2073 compatible = "arm,coresight-tmc", "arm,primecell"; 2074 reg = <0 0x06048000 0 0x1000>; 2075 iommus = <&apps_smmu 0x04c0 0>; 2076 2077 clocks = <&aoss_qmp>; 2078 clock-names = "apb_pclk"; 2079 arm,scatter-gather; 2080 2081 in-ports { 2082 port { 2083 etr_in: endpoint { 2084 remote-endpoint = <&replicator_out>; 2085 }; 2086 }; 2087 }; 2088 }; 2089 2090 funnel@6b04000 { 2091 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2092 reg = <0 0x06b04000 0 0x1000>; 2093 2094 clocks = <&aoss_qmp>; 2095 clock-names = "apb_pclk"; 2096 2097 out-ports { 2098 port { 2099 swao_funnel_out: endpoint { 2100 remote-endpoint = <&etf_in>; 2101 }; 2102 }; 2103 }; 2104 2105 in-ports { 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 2109 port@7 { 2110 reg = <7>; 2111 swao_funnel_in: endpoint { 2112 remote-endpoint = <&merge_funnel_out>; 2113 }; 2114 }; 2115 }; 2116 }; 2117 2118 etf@6b05000 { 2119 compatible = "arm,coresight-tmc", "arm,primecell"; 2120 reg = <0 0x06b05000 0 0x1000>; 2121 2122 clocks = <&aoss_qmp>; 2123 clock-names = "apb_pclk"; 2124 2125 out-ports { 2126 port { 2127 etf_out: endpoint { 2128 remote-endpoint = <&swao_replicator_in>; 2129 }; 2130 }; 2131 }; 2132 2133 in-ports { 2134 port { 2135 etf_in: endpoint { 2136 remote-endpoint = <&swao_funnel_out>; 2137 }; 2138 }; 2139 }; 2140 }; 2141 2142 replicator@6b06000 { 2143 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2144 reg = <0 0x06b06000 0 0x1000>; 2145 2146 clocks = <&aoss_qmp>; 2147 clock-names = "apb_pclk"; 2148 qcom,replicator-loses-context; 2149 2150 out-ports { 2151 port { 2152 swao_replicator_out: endpoint { 2153 remote-endpoint = <&replicator_in>; 2154 }; 2155 }; 2156 }; 2157 2158 in-ports { 2159 port { 2160 swao_replicator_in: endpoint { 2161 remote-endpoint = <&etf_out>; 2162 }; 2163 }; 2164 }; 2165 }; 2166 2167 etm@7040000 { 2168 compatible = "arm,coresight-etm4x", "arm,primecell"; 2169 reg = <0 0x07040000 0 0x1000>; 2170 2171 cpu = <&CPU0>; 2172 2173 clocks = <&aoss_qmp>; 2174 clock-names = "apb_pclk"; 2175 arm,coresight-loses-context-with-cpu; 2176 qcom,skip-power-up; 2177 2178 out-ports { 2179 port { 2180 etm0_out: endpoint { 2181 remote-endpoint = <&apss_funnel_in0>; 2182 }; 2183 }; 2184 }; 2185 }; 2186 2187 etm@7140000 { 2188 compatible = "arm,coresight-etm4x", "arm,primecell"; 2189 reg = <0 0x07140000 0 0x1000>; 2190 2191 cpu = <&CPU1>; 2192 2193 clocks = <&aoss_qmp>; 2194 clock-names = "apb_pclk"; 2195 arm,coresight-loses-context-with-cpu; 2196 qcom,skip-power-up; 2197 2198 out-ports { 2199 port { 2200 etm1_out: endpoint { 2201 remote-endpoint = <&apss_funnel_in1>; 2202 }; 2203 }; 2204 }; 2205 }; 2206 2207 etm@7240000 { 2208 compatible = "arm,coresight-etm4x", "arm,primecell"; 2209 reg = <0 0x07240000 0 0x1000>; 2210 2211 cpu = <&CPU2>; 2212 2213 clocks = <&aoss_qmp>; 2214 clock-names = "apb_pclk"; 2215 arm,coresight-loses-context-with-cpu; 2216 qcom,skip-power-up; 2217 2218 out-ports { 2219 port { 2220 etm2_out: endpoint { 2221 remote-endpoint = <&apss_funnel_in2>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 etm@7340000 { 2228 compatible = "arm,coresight-etm4x", "arm,primecell"; 2229 reg = <0 0x07340000 0 0x1000>; 2230 2231 cpu = <&CPU3>; 2232 2233 clocks = <&aoss_qmp>; 2234 clock-names = "apb_pclk"; 2235 arm,coresight-loses-context-with-cpu; 2236 qcom,skip-power-up; 2237 2238 out-ports { 2239 port { 2240 etm3_out: endpoint { 2241 remote-endpoint = <&apss_funnel_in3>; 2242 }; 2243 }; 2244 }; 2245 }; 2246 2247 etm@7440000 { 2248 compatible = "arm,coresight-etm4x", "arm,primecell"; 2249 reg = <0 0x07440000 0 0x1000>; 2250 2251 cpu = <&CPU4>; 2252 2253 clocks = <&aoss_qmp>; 2254 clock-names = "apb_pclk"; 2255 arm,coresight-loses-context-with-cpu; 2256 qcom,skip-power-up; 2257 2258 out-ports { 2259 port { 2260 etm4_out: endpoint { 2261 remote-endpoint = <&apss_funnel_in4>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 etm@7540000 { 2268 compatible = "arm,coresight-etm4x", "arm,primecell"; 2269 reg = <0 0x07540000 0 0x1000>; 2270 2271 cpu = <&CPU5>; 2272 2273 clocks = <&aoss_qmp>; 2274 clock-names = "apb_pclk"; 2275 arm,coresight-loses-context-with-cpu; 2276 qcom,skip-power-up; 2277 2278 out-ports { 2279 port { 2280 etm5_out: endpoint { 2281 remote-endpoint = <&apss_funnel_in5>; 2282 }; 2283 }; 2284 }; 2285 }; 2286 2287 etm@7640000 { 2288 compatible = "arm,coresight-etm4x", "arm,primecell"; 2289 reg = <0 0x07640000 0 0x1000>; 2290 2291 cpu = <&CPU6>; 2292 2293 clocks = <&aoss_qmp>; 2294 clock-names = "apb_pclk"; 2295 arm,coresight-loses-context-with-cpu; 2296 qcom,skip-power-up; 2297 2298 out-ports { 2299 port { 2300 etm6_out: endpoint { 2301 remote-endpoint = <&apss_funnel_in6>; 2302 }; 2303 }; 2304 }; 2305 }; 2306 2307 etm@7740000 { 2308 compatible = "arm,coresight-etm4x", "arm,primecell"; 2309 reg = <0 0x07740000 0 0x1000>; 2310 2311 cpu = <&CPU7>; 2312 2313 clocks = <&aoss_qmp>; 2314 clock-names = "apb_pclk"; 2315 arm,coresight-loses-context-with-cpu; 2316 qcom,skip-power-up; 2317 2318 out-ports { 2319 port { 2320 etm7_out: endpoint { 2321 remote-endpoint = <&apss_funnel_in7>; 2322 }; 2323 }; 2324 }; 2325 }; 2326 2327 funnel@7800000 { /* APSS Funnel */ 2328 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2329 reg = <0 0x07800000 0 0x1000>; 2330 2331 clocks = <&aoss_qmp>; 2332 clock-names = "apb_pclk"; 2333 2334 out-ports { 2335 port { 2336 apss_funnel_out: endpoint { 2337 remote-endpoint = <&apss_merge_funnel_in>; 2338 }; 2339 }; 2340 }; 2341 2342 in-ports { 2343 #address-cells = <1>; 2344 #size-cells = <0>; 2345 2346 port@0 { 2347 reg = <0>; 2348 apss_funnel_in0: endpoint { 2349 remote-endpoint = <&etm0_out>; 2350 }; 2351 }; 2352 2353 port@1 { 2354 reg = <1>; 2355 apss_funnel_in1: endpoint { 2356 remote-endpoint = <&etm1_out>; 2357 }; 2358 }; 2359 2360 port@2 { 2361 reg = <2>; 2362 apss_funnel_in2: endpoint { 2363 remote-endpoint = <&etm2_out>; 2364 }; 2365 }; 2366 2367 port@3 { 2368 reg = <3>; 2369 apss_funnel_in3: endpoint { 2370 remote-endpoint = <&etm3_out>; 2371 }; 2372 }; 2373 2374 port@4 { 2375 reg = <4>; 2376 apss_funnel_in4: endpoint { 2377 remote-endpoint = <&etm4_out>; 2378 }; 2379 }; 2380 2381 port@5 { 2382 reg = <5>; 2383 apss_funnel_in5: endpoint { 2384 remote-endpoint = <&etm5_out>; 2385 }; 2386 }; 2387 2388 port@6 { 2389 reg = <6>; 2390 apss_funnel_in6: endpoint { 2391 remote-endpoint = <&etm6_out>; 2392 }; 2393 }; 2394 2395 port@7 { 2396 reg = <7>; 2397 apss_funnel_in7: endpoint { 2398 remote-endpoint = <&etm7_out>; 2399 }; 2400 }; 2401 }; 2402 }; 2403 2404 funnel@7810000 { 2405 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2406 reg = <0 0x07810000 0 0x1000>; 2407 2408 clocks = <&aoss_qmp>; 2409 clock-names = "apb_pclk"; 2410 2411 out-ports { 2412 port { 2413 apss_merge_funnel_out: endpoint { 2414 remote-endpoint = <&funnel1_in4>; 2415 }; 2416 }; 2417 }; 2418 2419 in-ports { 2420 port { 2421 apss_merge_funnel_in: endpoint { 2422 remote-endpoint = <&apss_funnel_out>; 2423 }; 2424 }; 2425 }; 2426 }; 2427 2428 sdhc_2: sdhci@8804000 { 2429 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2430 status = "disabled"; 2431 2432 reg = <0 0x08804000 0 0x1000>; 2433 2434 iommus = <&apps_smmu 0x100 0x0>; 2435 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2437 interrupt-names = "hc_irq", "pwr_irq"; 2438 2439 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2440 <&gcc GCC_SDCC2_AHB_CLK>, 2441 <&rpmhcc RPMH_CXO_CLK>; 2442 clock-names = "core", "iface", "xo"; 2443 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2444 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2445 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2446 power-domains = <&rpmhpd SC7280_CX>; 2447 operating-points-v2 = <&sdhc2_opp_table>; 2448 2449 bus-width = <4>; 2450 2451 qcom,dll-config = <0x0007642c>; 2452 2453 sdhc2_opp_table: opp-table { 2454 compatible = "operating-points-v2"; 2455 2456 opp-100000000 { 2457 opp-hz = /bits/ 64 <100000000>; 2458 required-opps = <&rpmhpd_opp_low_svs>; 2459 opp-peak-kBps = <1800000 400000>; 2460 opp-avg-kBps = <100000 0>; 2461 }; 2462 2463 opp-202000000 { 2464 opp-hz = /bits/ 64 <202000000>; 2465 required-opps = <&rpmhpd_opp_nom>; 2466 opp-peak-kBps = <5400000 1600000>; 2467 opp-avg-kBps = <200000 0>; 2468 }; 2469 }; 2470 2471 }; 2472 2473 usb_1_hsphy: phy@88e3000 { 2474 compatible = "qcom,sc7280-usb-hs-phy", 2475 "qcom,usb-snps-hs-7nm-phy"; 2476 reg = <0 0x088e3000 0 0x400>; 2477 status = "disabled"; 2478 #phy-cells = <0>; 2479 2480 clocks = <&rpmhcc RPMH_CXO_CLK>; 2481 clock-names = "ref"; 2482 2483 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2484 }; 2485 2486 usb_2_hsphy: phy@88e4000 { 2487 compatible = "qcom,sc7280-usb-hs-phy", 2488 "qcom,usb-snps-hs-7nm-phy"; 2489 reg = <0 0x088e4000 0 0x400>; 2490 status = "disabled"; 2491 #phy-cells = <0>; 2492 2493 clocks = <&rpmhcc RPMH_CXO_CLK>; 2494 clock-names = "ref"; 2495 2496 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2497 }; 2498 2499 usb_1_qmpphy: phy-wrapper@88e9000 { 2500 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2501 "qcom,sm8250-qmp-usb3-dp-phy"; 2502 reg = <0 0x088e9000 0 0x200>, 2503 <0 0x088e8000 0 0x40>, 2504 <0 0x088ea000 0 0x200>; 2505 status = "disabled"; 2506 #address-cells = <2>; 2507 #size-cells = <2>; 2508 ranges; 2509 2510 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2511 <&rpmhcc RPMH_CXO_CLK>, 2512 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2513 clock-names = "aux", "ref_clk_src", "com_aux"; 2514 2515 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2516 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2517 reset-names = "phy", "common"; 2518 2519 usb_1_ssphy: usb3-phy@88e9200 { 2520 reg = <0 0x088e9200 0 0x200>, 2521 <0 0x088e9400 0 0x200>, 2522 <0 0x088e9c00 0 0x400>, 2523 <0 0x088e9600 0 0x200>, 2524 <0 0x088e9800 0 0x200>, 2525 <0 0x088e9a00 0 0x100>; 2526 #clock-cells = <0>; 2527 #phy-cells = <0>; 2528 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2529 clock-names = "pipe0"; 2530 clock-output-names = "usb3_phy_pipe_clk_src"; 2531 }; 2532 2533 dp_phy: dp-phy@88ea200 { 2534 reg = <0 0x088ea200 0 0x200>, 2535 <0 0x088ea400 0 0x200>, 2536 <0 0x088eaa00 0 0x200>, 2537 <0 0x088ea600 0 0x200>, 2538 <0 0x088ea800 0 0x200>; 2539 #phy-cells = <0>; 2540 #clock-cells = <1>; 2541 }; 2542 }; 2543 2544 usb_2: usb@8cf8800 { 2545 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2546 reg = <0 0x08cf8800 0 0x400>; 2547 status = "disabled"; 2548 #address-cells = <2>; 2549 #size-cells = <2>; 2550 ranges; 2551 dma-ranges; 2552 2553 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2554 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2555 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2556 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2557 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2558 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2559 "sleep"; 2560 2561 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2562 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2563 assigned-clock-rates = <19200000>, <200000000>; 2564 2565 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2566 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2567 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2568 interrupt-names = "hs_phy_irq", 2569 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2570 2571 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2572 2573 resets = <&gcc GCC_USB30_SEC_BCR>; 2574 2575 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2576 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2577 interconnect-names = "usb-ddr", "apps-usb"; 2578 2579 usb_2_dwc3: usb@8c00000 { 2580 compatible = "snps,dwc3"; 2581 reg = <0 0x08c00000 0 0xe000>; 2582 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2583 iommus = <&apps_smmu 0xa0 0x0>; 2584 snps,dis_u2_susphy_quirk; 2585 snps,dis_enblslpm_quirk; 2586 phys = <&usb_2_hsphy>; 2587 phy-names = "usb2-phy"; 2588 maximum-speed = "high-speed"; 2589 }; 2590 }; 2591 2592 qspi: spi@88dc000 { 2593 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2594 reg = <0 0x088dc000 0 0x1000>; 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2598 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2599 <&gcc GCC_QSPI_CORE_CLK>; 2600 clock-names = "iface", "core"; 2601 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2602 &cnoc2 SLAVE_QSPI_0 0>; 2603 interconnect-names = "qspi-config"; 2604 power-domains = <&rpmhpd SC7280_CX>; 2605 operating-points-v2 = <&qspi_opp_table>; 2606 status = "disabled"; 2607 }; 2608 2609 dc_noc: interconnect@90e0000 { 2610 reg = <0 0x090e0000 0 0x5080>; 2611 compatible = "qcom,sc7280-dc-noc"; 2612 #interconnect-cells = <2>; 2613 qcom,bcm-voters = <&apps_bcm_voter>; 2614 }; 2615 2616 gem_noc: interconnect@9100000 { 2617 reg = <0 0x9100000 0 0xe2200>; 2618 compatible = "qcom,sc7280-gem-noc"; 2619 #interconnect-cells = <2>; 2620 qcom,bcm-voters = <&apps_bcm_voter>; 2621 }; 2622 2623 system-cache-controller@9200000 { 2624 compatible = "qcom,sc7280-llcc"; 2625 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2626 reg-names = "llcc_base", "llcc_broadcast_base"; 2627 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2628 }; 2629 2630 nsp_noc: interconnect@a0c0000 { 2631 reg = <0 0x0a0c0000 0 0x10000>; 2632 compatible = "qcom,sc7280-nsp-noc"; 2633 #interconnect-cells = <2>; 2634 qcom,bcm-voters = <&apps_bcm_voter>; 2635 }; 2636 2637 usb_1: usb@a6f8800 { 2638 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2639 reg = <0 0x0a6f8800 0 0x400>; 2640 status = "disabled"; 2641 #address-cells = <2>; 2642 #size-cells = <2>; 2643 ranges; 2644 dma-ranges; 2645 2646 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2647 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2648 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2649 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2650 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2651 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2652 "sleep"; 2653 2654 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2655 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2656 assigned-clock-rates = <19200000>, <200000000>; 2657 2658 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2659 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2660 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2661 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2662 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2663 "dm_hs_phy_irq", "ss_phy_irq"; 2664 2665 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2666 2667 resets = <&gcc GCC_USB30_PRIM_BCR>; 2668 2669 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2670 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2671 interconnect-names = "usb-ddr", "apps-usb"; 2672 2673 usb_1_dwc3: usb@a600000 { 2674 compatible = "snps,dwc3"; 2675 reg = <0 0x0a600000 0 0xe000>; 2676 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2677 iommus = <&apps_smmu 0xe0 0x0>; 2678 snps,dis_u2_susphy_quirk; 2679 snps,dis_enblslpm_quirk; 2680 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2681 phy-names = "usb2-phy", "usb3-phy"; 2682 maximum-speed = "super-speed"; 2683 }; 2684 }; 2685 2686 venus: video-codec@aa00000 { 2687 compatible = "qcom,sc7280-venus"; 2688 reg = <0 0x0aa00000 0 0xd0600>; 2689 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2690 2691 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2692 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2693 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2694 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2695 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2696 clock-names = "core", "bus", "iface", 2697 "vcodec_core", "vcodec_bus"; 2698 2699 power-domains = <&videocc MVSC_GDSC>, 2700 <&videocc MVS0_GDSC>, 2701 <&rpmhpd SC7280_CX>; 2702 power-domain-names = "venus", "vcodec0", "cx"; 2703 operating-points-v2 = <&venus_opp_table>; 2704 2705 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2706 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2707 interconnect-names = "cpu-cfg", "video-mem"; 2708 2709 iommus = <&apps_smmu 0x2180 0x20>, 2710 <&apps_smmu 0x2184 0x20>; 2711 memory-region = <&video_mem>; 2712 2713 video-decoder { 2714 compatible = "venus-decoder"; 2715 }; 2716 2717 video-encoder { 2718 compatible = "venus-encoder"; 2719 }; 2720 2721 video-firmware { 2722 iommus = <&apps_smmu 0x21a2 0x0>; 2723 }; 2724 2725 venus_opp_table: venus-opp-table { 2726 compatible = "operating-points-v2"; 2727 2728 opp-133330000 { 2729 opp-hz = /bits/ 64 <133330000>; 2730 required-opps = <&rpmhpd_opp_low_svs>; 2731 }; 2732 2733 opp-240000000 { 2734 opp-hz = /bits/ 64 <240000000>; 2735 required-opps = <&rpmhpd_opp_svs>; 2736 }; 2737 2738 opp-335000000 { 2739 opp-hz = /bits/ 64 <335000000>; 2740 required-opps = <&rpmhpd_opp_svs_l1>; 2741 }; 2742 2743 opp-424000000 { 2744 opp-hz = /bits/ 64 <424000000>; 2745 required-opps = <&rpmhpd_opp_nom>; 2746 }; 2747 2748 opp-460000048 { 2749 opp-hz = /bits/ 64 <460000048>; 2750 required-opps = <&rpmhpd_opp_turbo>; 2751 }; 2752 }; 2753 2754 }; 2755 2756 videocc: clock-controller@aaf0000 { 2757 compatible = "qcom,sc7280-videocc"; 2758 reg = <0 0xaaf0000 0 0x10000>; 2759 clocks = <&rpmhcc RPMH_CXO_CLK>, 2760 <&rpmhcc RPMH_CXO_CLK_A>; 2761 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2762 #clock-cells = <1>; 2763 #reset-cells = <1>; 2764 #power-domain-cells = <1>; 2765 }; 2766 2767 camcc: clock-controller@ad00000 { 2768 compatible = "qcom,sc7280-camcc"; 2769 reg = <0 0x0ad00000 0 0x10000>; 2770 clocks = <&rpmhcc RPMH_CXO_CLK>, 2771 <&rpmhcc RPMH_CXO_CLK_A>, 2772 <&sleep_clk>; 2773 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 2774 #clock-cells = <1>; 2775 #reset-cells = <1>; 2776 #power-domain-cells = <1>; 2777 }; 2778 2779 dispcc: clock-controller@af00000 { 2780 compatible = "qcom,sc7280-dispcc"; 2781 reg = <0 0xaf00000 0 0x20000>; 2782 clocks = <&rpmhcc RPMH_CXO_CLK>, 2783 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2784 <&mdss_dsi_phy 0>, 2785 <&mdss_dsi_phy 1>, 2786 <&dp_phy 0>, 2787 <&dp_phy 1>, 2788 <&mdss_edp_phy 0>, 2789 <&mdss_edp_phy 1>; 2790 clock-names = "bi_tcxo", 2791 "gcc_disp_gpll0_clk", 2792 "dsi0_phy_pll_out_byteclk", 2793 "dsi0_phy_pll_out_dsiclk", 2794 "dp_phy_pll_link_clk", 2795 "dp_phy_pll_vco_div_clk", 2796 "edp_phy_pll_link_clk", 2797 "edp_phy_pll_vco_div_clk"; 2798 #clock-cells = <1>; 2799 #reset-cells = <1>; 2800 #power-domain-cells = <1>; 2801 }; 2802 2803 mdss: display-subsystem@ae00000 { 2804 compatible = "qcom,sc7280-mdss"; 2805 reg = <0 0x0ae00000 0 0x1000>; 2806 reg-names = "mdss"; 2807 2808 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 2809 2810 clocks = <&gcc GCC_DISP_AHB_CLK>, 2811 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2812 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2813 clock-names = "iface", 2814 "ahb", 2815 "core"; 2816 2817 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2818 assigned-clock-rates = <300000000>; 2819 2820 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2821 interrupt-controller; 2822 #interrupt-cells = <1>; 2823 2824 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2825 interconnect-names = "mdp0-mem"; 2826 2827 iommus = <&apps_smmu 0x900 0x402>; 2828 2829 #address-cells = <2>; 2830 #size-cells = <2>; 2831 ranges; 2832 2833 status = "disabled"; 2834 2835 mdss_mdp: display-controller@ae01000 { 2836 compatible = "qcom,sc7280-dpu"; 2837 reg = <0 0x0ae01000 0 0x8f030>, 2838 <0 0x0aeb0000 0 0x2008>; 2839 reg-names = "mdp", "vbif"; 2840 2841 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2842 <&gcc GCC_DISP_SF_AXI_CLK>, 2843 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2844 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2845 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2846 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2847 clock-names = "bus", 2848 "nrt_bus", 2849 "iface", 2850 "lut", 2851 "core", 2852 "vsync"; 2853 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2854 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2855 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2856 assigned-clock-rates = <300000000>, 2857 <19200000>, 2858 <19200000>; 2859 operating-points-v2 = <&mdp_opp_table>; 2860 power-domains = <&rpmhpd SC7280_CX>; 2861 2862 interrupt-parent = <&mdss>; 2863 interrupts = <0>; 2864 2865 status = "disabled"; 2866 2867 ports { 2868 #address-cells = <1>; 2869 #size-cells = <0>; 2870 2871 port@0 { 2872 reg = <0>; 2873 dpu_intf1_out: endpoint { 2874 remote-endpoint = <&dsi0_in>; 2875 }; 2876 }; 2877 2878 port@1 { 2879 reg = <1>; 2880 dpu_intf5_out: endpoint { 2881 remote-endpoint = <&edp_in>; 2882 }; 2883 }; 2884 2885 port@2 { 2886 reg = <2>; 2887 dpu_intf0_out: endpoint { 2888 remote-endpoint = <&dp_in>; 2889 }; 2890 }; 2891 }; 2892 2893 mdp_opp_table: opp-table { 2894 compatible = "operating-points-v2"; 2895 2896 opp-200000000 { 2897 opp-hz = /bits/ 64 <200000000>; 2898 required-opps = <&rpmhpd_opp_low_svs>; 2899 }; 2900 2901 opp-300000000 { 2902 opp-hz = /bits/ 64 <300000000>; 2903 required-opps = <&rpmhpd_opp_svs>; 2904 }; 2905 2906 opp-380000000 { 2907 opp-hz = /bits/ 64 <380000000>; 2908 required-opps = <&rpmhpd_opp_svs_l1>; 2909 }; 2910 2911 opp-506666667 { 2912 opp-hz = /bits/ 64 <506666667>; 2913 required-opps = <&rpmhpd_opp_nom>; 2914 }; 2915 }; 2916 }; 2917 2918 mdss_dsi: dsi@ae94000 { 2919 compatible = "qcom,mdss-dsi-ctrl"; 2920 reg = <0 0x0ae94000 0 0x400>; 2921 reg-names = "dsi_ctrl"; 2922 2923 interrupt-parent = <&mdss>; 2924 interrupts = <4>; 2925 2926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2929 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2931 <&gcc GCC_DISP_HF_AXI_CLK>; 2932 clock-names = "byte", 2933 "byte_intf", 2934 "pixel", 2935 "core", 2936 "iface", 2937 "bus"; 2938 2939 operating-points-v2 = <&dsi_opp_table>; 2940 power-domains = <&rpmhpd SC7280_CX>; 2941 2942 phys = <&mdss_dsi_phy>; 2943 phy-names = "dsi"; 2944 2945 #address-cells = <1>; 2946 #size-cells = <0>; 2947 2948 status = "disabled"; 2949 2950 ports { 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 port@0 { 2955 reg = <0>; 2956 dsi0_in: endpoint { 2957 remote-endpoint = <&dpu_intf1_out>; 2958 }; 2959 }; 2960 2961 port@1 { 2962 reg = <1>; 2963 dsi0_out: endpoint { 2964 }; 2965 }; 2966 }; 2967 2968 dsi_opp_table: opp-table { 2969 compatible = "operating-points-v2"; 2970 2971 opp-187500000 { 2972 opp-hz = /bits/ 64 <187500000>; 2973 required-opps = <&rpmhpd_opp_low_svs>; 2974 }; 2975 2976 opp-300000000 { 2977 opp-hz = /bits/ 64 <300000000>; 2978 required-opps = <&rpmhpd_opp_svs>; 2979 }; 2980 2981 opp-358000000 { 2982 opp-hz = /bits/ 64 <358000000>; 2983 required-opps = <&rpmhpd_opp_svs_l1>; 2984 }; 2985 }; 2986 }; 2987 2988 mdss_dsi_phy: phy@ae94400 { 2989 compatible = "qcom,sc7280-dsi-phy-7nm"; 2990 reg = <0 0x0ae94400 0 0x200>, 2991 <0 0x0ae94600 0 0x280>, 2992 <0 0x0ae94900 0 0x280>; 2993 reg-names = "dsi_phy", 2994 "dsi_phy_lane", 2995 "dsi_pll"; 2996 2997 #clock-cells = <1>; 2998 #phy-cells = <0>; 2999 3000 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3001 <&rpmhcc RPMH_CXO_CLK>; 3002 clock-names = "iface", "ref"; 3003 3004 status = "disabled"; 3005 }; 3006 3007 mdss_edp: edp@aea0000 { 3008 compatible = "qcom,sc7280-edp"; 3009 3010 reg = <0 0xaea0000 0 0x200>, 3011 <0 0xaea0200 0 0x200>, 3012 <0 0xaea0400 0 0xc00>, 3013 <0 0xaea1000 0 0x400>; 3014 3015 interrupt-parent = <&mdss>; 3016 interrupts = <14>; 3017 3018 clocks = <&rpmhcc RPMH_CXO_CLK>, 3019 <&gcc GCC_EDP_CLKREF_EN>, 3020 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3021 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3022 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3023 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3024 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3025 clock-names = "core_xo", 3026 "core_ref", 3027 "core_iface", 3028 "core_aux", 3029 "ctrl_link", 3030 "ctrl_link_iface", 3031 "stream_pixel"; 3032 #clock-cells = <1>; 3033 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3034 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3035 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3036 3037 phys = <&mdss_edp_phy>; 3038 phy-names = "dp"; 3039 3040 operating-points-v2 = <&edp_opp_table>; 3041 power-domains = <&rpmhpd SC7280_CX>; 3042 3043 #address-cells = <1>; 3044 #size-cells = <0>; 3045 3046 status = "disabled"; 3047 3048 ports { 3049 #address-cells = <1>; 3050 #size-cells = <0>; 3051 port@0 { 3052 reg = <0>; 3053 edp_in: endpoint { 3054 remote-endpoint = <&dpu_intf5_out>; 3055 }; 3056 }; 3057 }; 3058 3059 edp_opp_table: opp-table { 3060 compatible = "operating-points-v2"; 3061 3062 opp-160000000 { 3063 opp-hz = /bits/ 64 <160000000>; 3064 required-opps = <&rpmhpd_opp_low_svs>; 3065 }; 3066 3067 opp-270000000 { 3068 opp-hz = /bits/ 64 <270000000>; 3069 required-opps = <&rpmhpd_opp_svs>; 3070 }; 3071 3072 opp-540000000 { 3073 opp-hz = /bits/ 64 <540000000>; 3074 required-opps = <&rpmhpd_opp_nom>; 3075 }; 3076 3077 opp-810000000 { 3078 opp-hz = /bits/ 64 <810000000>; 3079 required-opps = <&rpmhpd_opp_nom>; 3080 }; 3081 }; 3082 }; 3083 3084 mdss_edp_phy: phy@aec2a00 { 3085 compatible = "qcom,sc7280-edp-phy"; 3086 3087 reg = <0 0xaec2a00 0 0x19c>, 3088 <0 0xaec2200 0 0xa0>, 3089 <0 0xaec2600 0 0xa0>, 3090 <0 0xaec2000 0 0x1c0>; 3091 3092 clocks = <&rpmhcc RPMH_CXO_CLK>, 3093 <&gcc GCC_EDP_CLKREF_EN>; 3094 clock-names = "aux", 3095 "cfg_ahb"; 3096 3097 #clock-cells = <1>; 3098 #phy-cells = <0>; 3099 3100 status = "disabled"; 3101 }; 3102 3103 mdss_dp: displayport-controller@ae90000 { 3104 compatible = "qcom,sc7280-dp"; 3105 3106 reg = <0 0x0ae90000 0 0x1400>; 3107 3108 interrupt-parent = <&mdss>; 3109 interrupts = <12>; 3110 3111 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3112 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3113 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3114 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3115 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3116 clock-names = "core_iface", 3117 "core_aux", 3118 "ctrl_link", 3119 "ctrl_link_iface", 3120 "stream_pixel"; 3121 #clock-cells = <1>; 3122 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3123 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3124 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3125 phys = <&dp_phy>; 3126 phy-names = "dp"; 3127 3128 operating-points-v2 = <&dp_opp_table>; 3129 power-domains = <&rpmhpd SC7280_CX>; 3130 3131 #sound-dai-cells = <0>; 3132 3133 status = "disabled"; 3134 3135 ports { 3136 #address-cells = <1>; 3137 #size-cells = <0>; 3138 port@0 { 3139 reg = <0>; 3140 dp_in: endpoint { 3141 remote-endpoint = <&dpu_intf0_out>; 3142 }; 3143 }; 3144 3145 port@1 { 3146 reg = <1>; 3147 dp_out: endpoint { }; 3148 }; 3149 }; 3150 3151 dp_opp_table: opp-table { 3152 compatible = "operating-points-v2"; 3153 3154 opp-160000000 { 3155 opp-hz = /bits/ 64 <160000000>; 3156 required-opps = <&rpmhpd_opp_low_svs>; 3157 }; 3158 3159 opp-270000000 { 3160 opp-hz = /bits/ 64 <270000000>; 3161 required-opps = <&rpmhpd_opp_svs>; 3162 }; 3163 3164 opp-540000000 { 3165 opp-hz = /bits/ 64 <540000000>; 3166 required-opps = <&rpmhpd_opp_svs_l1>; 3167 }; 3168 3169 opp-810000000 { 3170 opp-hz = /bits/ 64 <810000000>; 3171 required-opps = <&rpmhpd_opp_nom>; 3172 }; 3173 }; 3174 }; 3175 }; 3176 3177 pdc: interrupt-controller@b220000 { 3178 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3179 reg = <0 0x0b220000 0 0x30000>; 3180 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3181 <55 306 4>, <59 312 3>, <62 374 2>, 3182 <64 434 2>, <66 438 3>, <69 86 1>, 3183 <70 520 54>, <124 609 31>, <155 63 1>, 3184 <156 716 12>; 3185 #interrupt-cells = <2>; 3186 interrupt-parent = <&intc>; 3187 interrupt-controller; 3188 }; 3189 3190 pdc_reset: reset-controller@b5e0000 { 3191 compatible = "qcom,sc7280-pdc-global"; 3192 reg = <0 0x0b5e0000 0 0x20000>; 3193 #reset-cells = <1>; 3194 }; 3195 3196 tsens0: thermal-sensor@c263000 { 3197 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3198 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3199 <0 0x0c222000 0 0x1ff>; /* SROT */ 3200 #qcom,sensors = <15>; 3201 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3203 interrupt-names = "uplow","critical"; 3204 #thermal-sensor-cells = <1>; 3205 }; 3206 3207 tsens1: thermal-sensor@c265000 { 3208 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3209 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3210 <0 0x0c223000 0 0x1ff>; /* SROT */ 3211 #qcom,sensors = <12>; 3212 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3214 interrupt-names = "uplow","critical"; 3215 #thermal-sensor-cells = <1>; 3216 }; 3217 3218 aoss_reset: reset-controller@c2a0000 { 3219 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3220 reg = <0 0x0c2a0000 0 0x31000>; 3221 #reset-cells = <1>; 3222 }; 3223 3224 aoss_qmp: power-controller@c300000 { 3225 compatible = "qcom,sc7280-aoss-qmp"; 3226 reg = <0 0x0c300000 0 0x400>; 3227 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3228 IPCC_MPROC_SIGNAL_GLINK_QMP 3229 IRQ_TYPE_EDGE_RISING>; 3230 mboxes = <&ipcc IPCC_CLIENT_AOP 3231 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3232 3233 #clock-cells = <0>; 3234 }; 3235 3236 sram@c3f0000 { 3237 compatible = "qcom,rpmh-stats"; 3238 reg = <0 0x0c3f0000 0 0x400>; 3239 }; 3240 3241 spmi_bus: spmi@c440000 { 3242 compatible = "qcom,spmi-pmic-arb"; 3243 reg = <0 0x0c440000 0 0x1100>, 3244 <0 0x0c600000 0 0x2000000>, 3245 <0 0x0e600000 0 0x100000>, 3246 <0 0x0e700000 0 0xa0000>, 3247 <0 0x0c40a000 0 0x26000>; 3248 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3249 interrupt-names = "periph_irq"; 3250 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3251 qcom,ee = <0>; 3252 qcom,channel = <0>; 3253 #address-cells = <1>; 3254 #size-cells = <1>; 3255 interrupt-controller; 3256 #interrupt-cells = <4>; 3257 }; 3258 3259 tlmm: pinctrl@f100000 { 3260 compatible = "qcom,sc7280-pinctrl"; 3261 reg = <0 0x0f100000 0 0x300000>; 3262 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3263 gpio-controller; 3264 #gpio-cells = <2>; 3265 interrupt-controller; 3266 #interrupt-cells = <2>; 3267 gpio-ranges = <&tlmm 0 0 175>; 3268 wakeup-parent = <&pdc>; 3269 3270 pcie1_clkreq_n: pcie1-clkreq-n { 3271 pins = "gpio79"; 3272 function = "pcie1_clkreqn"; 3273 drive-strength = <2>; 3274 bias-pull-up; 3275 }; 3276 3277 dp_hot_plug_det: dp-hot-plug-det { 3278 pins = "gpio47"; 3279 function = "dp_hot"; 3280 bias-disable; 3281 }; 3282 3283 qspi_clk: qspi-clk { 3284 pins = "gpio14"; 3285 function = "qspi_clk"; 3286 }; 3287 3288 qspi_cs0: qspi-cs0 { 3289 pins = "gpio15"; 3290 function = "qspi_cs"; 3291 }; 3292 3293 qspi_cs1: qspi-cs1 { 3294 pins = "gpio19"; 3295 function = "qspi_cs"; 3296 }; 3297 3298 qspi_data01: qspi-data01 { 3299 pins = "gpio12", "gpio13"; 3300 function = "qspi_data"; 3301 }; 3302 3303 qspi_data12: qspi-data12 { 3304 pins = "gpio16", "gpio17"; 3305 function = "qspi_data"; 3306 }; 3307 3308 qup_i2c0_data_clk: qup-i2c0-data-clk { 3309 pins = "gpio0", "gpio1"; 3310 function = "qup00"; 3311 }; 3312 3313 qup_i2c1_data_clk: qup-i2c1-data-clk { 3314 pins = "gpio4", "gpio5"; 3315 function = "qup01"; 3316 }; 3317 3318 qup_i2c2_data_clk: qup-i2c2-data-clk { 3319 pins = "gpio8", "gpio9"; 3320 function = "qup02"; 3321 }; 3322 3323 qup_i2c3_data_clk: qup-i2c3-data-clk { 3324 pins = "gpio12", "gpio13"; 3325 function = "qup03"; 3326 }; 3327 3328 qup_i2c4_data_clk: qup-i2c4-data-clk { 3329 pins = "gpio16", "gpio17"; 3330 function = "qup04"; 3331 }; 3332 3333 qup_i2c5_data_clk: qup-i2c5-data-clk { 3334 pins = "gpio20", "gpio21"; 3335 function = "qup05"; 3336 }; 3337 3338 qup_i2c6_data_clk: qup-i2c6-data-clk { 3339 pins = "gpio24", "gpio25"; 3340 function = "qup06"; 3341 }; 3342 3343 qup_i2c7_data_clk: qup-i2c7-data-clk { 3344 pins = "gpio28", "gpio29"; 3345 function = "qup07"; 3346 }; 3347 3348 qup_i2c8_data_clk: qup-i2c8-data-clk { 3349 pins = "gpio32", "gpio33"; 3350 function = "qup10"; 3351 }; 3352 3353 qup_i2c9_data_clk: qup-i2c9-data-clk { 3354 pins = "gpio36", "gpio37"; 3355 function = "qup11"; 3356 }; 3357 3358 qup_i2c10_data_clk: qup-i2c10-data-clk { 3359 pins = "gpio40", "gpio41"; 3360 function = "qup12"; 3361 }; 3362 3363 qup_i2c11_data_clk: qup-i2c11-data-clk { 3364 pins = "gpio44", "gpio45"; 3365 function = "qup13"; 3366 }; 3367 3368 qup_i2c12_data_clk: qup-i2c12-data-clk { 3369 pins = "gpio48", "gpio49"; 3370 function = "qup14"; 3371 }; 3372 3373 qup_i2c13_data_clk: qup-i2c13-data-clk { 3374 pins = "gpio52", "gpio53"; 3375 function = "qup15"; 3376 }; 3377 3378 qup_i2c14_data_clk: qup-i2c14-data-clk { 3379 pins = "gpio56", "gpio57"; 3380 function = "qup16"; 3381 }; 3382 3383 qup_i2c15_data_clk: qup-i2c15-data-clk { 3384 pins = "gpio60", "gpio61"; 3385 function = "qup17"; 3386 }; 3387 3388 qup_spi0_data_clk: qup-spi0-data-clk { 3389 pins = "gpio0", "gpio1", "gpio2"; 3390 function = "qup00"; 3391 }; 3392 3393 qup_spi0_cs: qup-spi0-cs { 3394 pins = "gpio3"; 3395 function = "qup00"; 3396 }; 3397 3398 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3399 pins = "gpio3"; 3400 function = "gpio"; 3401 }; 3402 3403 qup_spi1_data_clk: qup-spi1-data-clk { 3404 pins = "gpio4", "gpio5", "gpio6"; 3405 function = "qup01"; 3406 }; 3407 3408 qup_spi1_cs: qup-spi1-cs { 3409 pins = "gpio7"; 3410 function = "qup01"; 3411 }; 3412 3413 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3414 pins = "gpio7"; 3415 function = "gpio"; 3416 }; 3417 3418 qup_spi2_data_clk: qup-spi2-data-clk { 3419 pins = "gpio8", "gpio9", "gpio10"; 3420 function = "qup02"; 3421 }; 3422 3423 qup_spi2_cs: qup-spi2-cs { 3424 pins = "gpio11"; 3425 function = "qup02"; 3426 }; 3427 3428 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3429 pins = "gpio11"; 3430 function = "gpio"; 3431 }; 3432 3433 qup_spi3_data_clk: qup-spi3-data-clk { 3434 pins = "gpio12", "gpio13", "gpio14"; 3435 function = "qup03"; 3436 }; 3437 3438 qup_spi3_cs: qup-spi3-cs { 3439 pins = "gpio15"; 3440 function = "qup03"; 3441 }; 3442 3443 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3444 pins = "gpio15"; 3445 function = "gpio"; 3446 }; 3447 3448 qup_spi4_data_clk: qup-spi4-data-clk { 3449 pins = "gpio16", "gpio17", "gpio18"; 3450 function = "qup04"; 3451 }; 3452 3453 qup_spi4_cs: qup-spi4-cs { 3454 pins = "gpio19"; 3455 function = "qup04"; 3456 }; 3457 3458 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3459 pins = "gpio19"; 3460 function = "gpio"; 3461 }; 3462 3463 qup_spi5_data_clk: qup-spi5-data-clk { 3464 pins = "gpio20", "gpio21", "gpio22"; 3465 function = "qup05"; 3466 }; 3467 3468 qup_spi5_cs: qup-spi5-cs { 3469 pins = "gpio23"; 3470 function = "qup05"; 3471 }; 3472 3473 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3474 pins = "gpio23"; 3475 function = "gpio"; 3476 }; 3477 3478 qup_spi6_data_clk: qup-spi6-data-clk { 3479 pins = "gpio24", "gpio25", "gpio26"; 3480 function = "qup06"; 3481 }; 3482 3483 qup_spi6_cs: qup-spi6-cs { 3484 pins = "gpio27"; 3485 function = "qup06"; 3486 }; 3487 3488 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3489 pins = "gpio27"; 3490 function = "gpio"; 3491 }; 3492 3493 qup_spi7_data_clk: qup-spi7-data-clk { 3494 pins = "gpio28", "gpio29", "gpio30"; 3495 function = "qup07"; 3496 }; 3497 3498 qup_spi7_cs: qup-spi7-cs { 3499 pins = "gpio31"; 3500 function = "qup07"; 3501 }; 3502 3503 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3504 pins = "gpio31"; 3505 function = "gpio"; 3506 }; 3507 3508 qup_spi8_data_clk: qup-spi8-data-clk { 3509 pins = "gpio32", "gpio33", "gpio34"; 3510 function = "qup10"; 3511 }; 3512 3513 qup_spi8_cs: qup-spi8-cs { 3514 pins = "gpio35"; 3515 function = "qup10"; 3516 }; 3517 3518 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3519 pins = "gpio35"; 3520 function = "gpio"; 3521 }; 3522 3523 qup_spi9_data_clk: qup-spi9-data-clk { 3524 pins = "gpio36", "gpio37", "gpio38"; 3525 function = "qup11"; 3526 }; 3527 3528 qup_spi9_cs: qup-spi9-cs { 3529 pins = "gpio39"; 3530 function = "qup11"; 3531 }; 3532 3533 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3534 pins = "gpio39"; 3535 function = "gpio"; 3536 }; 3537 3538 qup_spi10_data_clk: qup-spi10-data-clk { 3539 pins = "gpio40", "gpio41", "gpio42"; 3540 function = "qup12"; 3541 }; 3542 3543 qup_spi10_cs: qup-spi10-cs { 3544 pins = "gpio43"; 3545 function = "qup12"; 3546 }; 3547 3548 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3549 pins = "gpio43"; 3550 function = "gpio"; 3551 }; 3552 3553 qup_spi11_data_clk: qup-spi11-data-clk { 3554 pins = "gpio44", "gpio45", "gpio46"; 3555 function = "qup13"; 3556 }; 3557 3558 qup_spi11_cs: qup-spi11-cs { 3559 pins = "gpio47"; 3560 function = "qup13"; 3561 }; 3562 3563 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3564 pins = "gpio47"; 3565 function = "gpio"; 3566 }; 3567 3568 qup_spi12_data_clk: qup-spi12-data-clk { 3569 pins = "gpio48", "gpio49", "gpio50"; 3570 function = "qup14"; 3571 }; 3572 3573 qup_spi12_cs: qup-spi12-cs { 3574 pins = "gpio51"; 3575 function = "qup14"; 3576 }; 3577 3578 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3579 pins = "gpio51"; 3580 function = "gpio"; 3581 }; 3582 3583 qup_spi13_data_clk: qup-spi13-data-clk { 3584 pins = "gpio52", "gpio53", "gpio54"; 3585 function = "qup15"; 3586 }; 3587 3588 qup_spi13_cs: qup-spi13-cs { 3589 pins = "gpio55"; 3590 function = "qup15"; 3591 }; 3592 3593 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3594 pins = "gpio55"; 3595 function = "gpio"; 3596 }; 3597 3598 qup_spi14_data_clk: qup-spi14-data-clk { 3599 pins = "gpio56", "gpio57", "gpio58"; 3600 function = "qup16"; 3601 }; 3602 3603 qup_spi14_cs: qup-spi14-cs { 3604 pins = "gpio59"; 3605 function = "qup16"; 3606 }; 3607 3608 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3609 pins = "gpio59"; 3610 function = "gpio"; 3611 }; 3612 3613 qup_spi15_data_clk: qup-spi15-data-clk { 3614 pins = "gpio60", "gpio61", "gpio62"; 3615 function = "qup17"; 3616 }; 3617 3618 qup_spi15_cs: qup-spi15-cs { 3619 pins = "gpio63"; 3620 function = "qup17"; 3621 }; 3622 3623 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3624 pins = "gpio63"; 3625 function = "gpio"; 3626 }; 3627 3628 qup_uart0_cts: qup-uart0-cts { 3629 pins = "gpio0"; 3630 function = "qup00"; 3631 }; 3632 3633 qup_uart0_rts: qup-uart0-rts { 3634 pins = "gpio1"; 3635 function = "qup00"; 3636 }; 3637 3638 qup_uart0_tx: qup-uart0-tx { 3639 pins = "gpio2"; 3640 function = "qup00"; 3641 }; 3642 3643 qup_uart0_rx: qup-uart0-rx { 3644 pins = "gpio3"; 3645 function = "qup00"; 3646 }; 3647 3648 qup_uart1_cts: qup-uart1-cts { 3649 pins = "gpio4"; 3650 function = "qup01"; 3651 }; 3652 3653 qup_uart1_rts: qup-uart1-rts { 3654 pins = "gpio5"; 3655 function = "qup01"; 3656 }; 3657 3658 qup_uart1_tx: qup-uart1-tx { 3659 pins = "gpio6"; 3660 function = "qup01"; 3661 }; 3662 3663 qup_uart1_rx: qup-uart1-rx { 3664 pins = "gpio7"; 3665 function = "qup01"; 3666 }; 3667 3668 qup_uart2_cts: qup-uart2-cts { 3669 pins = "gpio8"; 3670 function = "qup02"; 3671 }; 3672 3673 qup_uart2_rts: qup-uart2-rts { 3674 pins = "gpio9"; 3675 function = "qup02"; 3676 }; 3677 3678 qup_uart2_tx: qup-uart2-tx { 3679 pins = "gpio10"; 3680 function = "qup02"; 3681 }; 3682 3683 qup_uart2_rx: qup-uart2-rx { 3684 pins = "gpio11"; 3685 function = "qup02"; 3686 }; 3687 3688 qup_uart3_cts: qup-uart3-cts { 3689 pins = "gpio12"; 3690 function = "qup03"; 3691 }; 3692 3693 qup_uart3_rts: qup-uart3-rts { 3694 pins = "gpio13"; 3695 function = "qup03"; 3696 }; 3697 3698 qup_uart3_tx: qup-uart3-tx { 3699 pins = "gpio14"; 3700 function = "qup03"; 3701 }; 3702 3703 qup_uart3_rx: qup-uart3-rx { 3704 pins = "gpio15"; 3705 function = "qup03"; 3706 }; 3707 3708 qup_uart4_cts: qup-uart4-cts { 3709 pins = "gpio16"; 3710 function = "qup04"; 3711 }; 3712 3713 qup_uart4_rts: qup-uart4-rts { 3714 pins = "gpio17"; 3715 function = "qup04"; 3716 }; 3717 3718 qup_uart4_tx: qup-uart4-tx { 3719 pins = "gpio18"; 3720 function = "qup04"; 3721 }; 3722 3723 qup_uart4_rx: qup-uart4-rx { 3724 pins = "gpio19"; 3725 function = "qup04"; 3726 }; 3727 3728 qup_uart5_cts: qup-uart5-cts { 3729 pins = "gpio20"; 3730 function = "qup05"; 3731 }; 3732 3733 qup_uart5_rts: qup-uart5-rts { 3734 pins = "gpio21"; 3735 function = "qup05"; 3736 }; 3737 3738 qup_uart5_tx: qup-uart5-tx { 3739 pins = "gpio22"; 3740 function = "qup05"; 3741 }; 3742 3743 qup_uart5_rx: qup-uart5-rx { 3744 pins = "gpio23"; 3745 function = "qup05"; 3746 }; 3747 3748 qup_uart6_cts: qup-uart6-cts { 3749 pins = "gpio24"; 3750 function = "qup06"; 3751 }; 3752 3753 qup_uart6_rts: qup-uart6-rts { 3754 pins = "gpio25"; 3755 function = "qup06"; 3756 }; 3757 3758 qup_uart6_tx: qup-uart6-tx { 3759 pins = "gpio26"; 3760 function = "qup06"; 3761 }; 3762 3763 qup_uart6_rx: qup-uart6-rx { 3764 pins = "gpio27"; 3765 function = "qup06"; 3766 }; 3767 3768 qup_uart7_cts: qup-uart7-cts { 3769 pins = "gpio28"; 3770 function = "qup07"; 3771 }; 3772 3773 qup_uart7_rts: qup-uart7-rts { 3774 pins = "gpio29"; 3775 function = "qup07"; 3776 }; 3777 3778 qup_uart7_tx: qup-uart7-tx { 3779 pins = "gpio30"; 3780 function = "qup07"; 3781 }; 3782 3783 qup_uart7_rx: qup-uart7-rx { 3784 pins = "gpio31"; 3785 function = "qup07"; 3786 }; 3787 3788 sdc1_on: sdc1-on { 3789 clk { 3790 pins = "sdc1_clk"; 3791 }; 3792 3793 cmd { 3794 pins = "sdc1_cmd"; 3795 }; 3796 3797 data { 3798 pins = "sdc1_data"; 3799 }; 3800 3801 rclk { 3802 pins = "sdc1_rclk"; 3803 }; 3804 }; 3805 3806 sdc1_off: sdc1-off { 3807 clk { 3808 pins = "sdc1_clk"; 3809 drive-strength = <2>; 3810 bias-bus-hold; 3811 }; 3812 3813 cmd { 3814 pins = "sdc1_cmd"; 3815 drive-strength = <2>; 3816 bias-bus-hold; 3817 }; 3818 3819 data { 3820 pins = "sdc1_data"; 3821 drive-strength = <2>; 3822 bias-bus-hold; 3823 }; 3824 3825 rclk { 3826 pins = "sdc1_rclk"; 3827 bias-bus-hold; 3828 }; 3829 }; 3830 3831 sdc2_on: sdc2-on { 3832 clk { 3833 pins = "sdc2_clk"; 3834 }; 3835 3836 cmd { 3837 pins = "sdc2_cmd"; 3838 }; 3839 3840 data { 3841 pins = "sdc2_data"; 3842 }; 3843 }; 3844 3845 sdc2_off: sdc2-off { 3846 clk { 3847 pins = "sdc2_clk"; 3848 drive-strength = <2>; 3849 bias-bus-hold; 3850 }; 3851 3852 cmd { 3853 pins ="sdc2_cmd"; 3854 drive-strength = <2>; 3855 bias-bus-hold; 3856 }; 3857 3858 data { 3859 pins ="sdc2_data"; 3860 drive-strength = <2>; 3861 bias-bus-hold; 3862 }; 3863 }; 3864 3865 qup_uart8_cts: qup-uart8-cts { 3866 pins = "gpio32"; 3867 function = "qup10"; 3868 }; 3869 3870 qup_uart8_rts: qup-uart8-rts { 3871 pins = "gpio33"; 3872 function = "qup10"; 3873 }; 3874 3875 qup_uart8_tx: qup-uart8-tx { 3876 pins = "gpio34"; 3877 function = "qup10"; 3878 }; 3879 3880 qup_uart8_rx: qup-uart8-rx { 3881 pins = "gpio35"; 3882 function = "qup10"; 3883 }; 3884 3885 qup_uart9_cts: qup-uart9-cts { 3886 pins = "gpio36"; 3887 function = "qup11"; 3888 }; 3889 3890 qup_uart9_rts: qup-uart9-rts { 3891 pins = "gpio37"; 3892 function = "qup11"; 3893 }; 3894 3895 qup_uart9_tx: qup-uart9-tx { 3896 pins = "gpio38"; 3897 function = "qup11"; 3898 }; 3899 3900 qup_uart9_rx: qup-uart9-rx { 3901 pins = "gpio39"; 3902 function = "qup11"; 3903 }; 3904 3905 qup_uart10_cts: qup-uart10-cts { 3906 pins = "gpio40"; 3907 function = "qup12"; 3908 }; 3909 3910 qup_uart10_rts: qup-uart10-rts { 3911 pins = "gpio41"; 3912 function = "qup12"; 3913 }; 3914 3915 qup_uart10_tx: qup-uart10-tx { 3916 pins = "gpio42"; 3917 function = "qup12"; 3918 }; 3919 3920 qup_uart10_rx: qup-uart10-rx { 3921 pins = "gpio43"; 3922 function = "qup12"; 3923 }; 3924 3925 qup_uart11_cts: qup-uart11-cts { 3926 pins = "gpio44"; 3927 function = "qup13"; 3928 }; 3929 3930 qup_uart11_rts: qup-uart11-rts { 3931 pins = "gpio45"; 3932 function = "qup13"; 3933 }; 3934 3935 qup_uart11_tx: qup-uart11-tx { 3936 pins = "gpio46"; 3937 function = "qup13"; 3938 }; 3939 3940 qup_uart11_rx: qup-uart11-rx { 3941 pins = "gpio47"; 3942 function = "qup13"; 3943 }; 3944 3945 qup_uart12_cts: qup-uart12-cts { 3946 pins = "gpio48"; 3947 function = "qup14"; 3948 }; 3949 3950 qup_uart12_rts: qup-uart12-rts { 3951 pins = "gpio49"; 3952 function = "qup14"; 3953 }; 3954 3955 qup_uart12_tx: qup-uart12-tx { 3956 pins = "gpio50"; 3957 function = "qup14"; 3958 }; 3959 3960 qup_uart12_rx: qup-uart12-rx { 3961 pins = "gpio51"; 3962 function = "qup14"; 3963 }; 3964 3965 qup_uart13_cts: qup-uart13-cts { 3966 pins = "gpio52"; 3967 function = "qup15"; 3968 }; 3969 3970 qup_uart13_rts: qup-uart13-rts { 3971 pins = "gpio53"; 3972 function = "qup15"; 3973 }; 3974 3975 qup_uart13_tx: qup-uart13-tx { 3976 pins = "gpio54"; 3977 function = "qup15"; 3978 }; 3979 3980 qup_uart13_rx: qup-uart13-rx { 3981 pins = "gpio55"; 3982 function = "qup15"; 3983 }; 3984 3985 qup_uart14_cts: qup-uart14-cts { 3986 pins = "gpio56"; 3987 function = "qup16"; 3988 }; 3989 3990 qup_uart14_rts: qup-uart14-rts { 3991 pins = "gpio57"; 3992 function = "qup16"; 3993 }; 3994 3995 qup_uart14_tx: qup-uart14-tx { 3996 pins = "gpio58"; 3997 function = "qup16"; 3998 }; 3999 4000 qup_uart14_rx: qup-uart14-rx { 4001 pins = "gpio59"; 4002 function = "qup16"; 4003 }; 4004 4005 qup_uart15_cts: qup-uart15-cts { 4006 pins = "gpio60"; 4007 function = "qup17"; 4008 }; 4009 4010 qup_uart15_rts: qup-uart15-rts { 4011 pins = "gpio61"; 4012 function = "qup17"; 4013 }; 4014 4015 qup_uart15_tx: qup-uart15-tx { 4016 pins = "gpio62"; 4017 function = "qup17"; 4018 }; 4019 4020 qup_uart15_rx: qup-uart15-rx { 4021 pins = "gpio63"; 4022 function = "qup17"; 4023 }; 4024 }; 4025 4026 imem@146a5000 { 4027 compatible = "qcom,sc7280-imem", "syscon"; 4028 reg = <0 0x146a5000 0 0x6000>; 4029 4030 #address-cells = <1>; 4031 #size-cells = <1>; 4032 4033 ranges = <0 0 0x146a5000 0x6000>; 4034 4035 pil-reloc@594c { 4036 compatible = "qcom,pil-reloc-info"; 4037 reg = <0x594c 0xc8>; 4038 }; 4039 }; 4040 4041 apps_smmu: iommu@15000000 { 4042 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4043 reg = <0 0x15000000 0 0x100000>; 4044 #iommu-cells = <2>; 4045 #global-interrupts = <1>; 4046 dma-coherent; 4047 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4128 }; 4129 4130 intc: interrupt-controller@17a00000 { 4131 compatible = "arm,gic-v3"; 4132 #address-cells = <2>; 4133 #size-cells = <2>; 4134 ranges; 4135 #interrupt-cells = <3>; 4136 interrupt-controller; 4137 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4138 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4140 4141 gic-its@17a40000 { 4142 compatible = "arm,gic-v3-its"; 4143 msi-controller; 4144 #msi-cells = <1>; 4145 reg = <0 0x17a40000 0 0x20000>; 4146 status = "disabled"; 4147 }; 4148 }; 4149 4150 watchdog@17c10000 { 4151 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4152 reg = <0 0x17c10000 0 0x1000>; 4153 clocks = <&sleep_clk>; 4154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4155 }; 4156 4157 timer@17c20000 { 4158 #address-cells = <2>; 4159 #size-cells = <2>; 4160 ranges; 4161 compatible = "arm,armv7-timer-mem"; 4162 reg = <0 0x17c20000 0 0x1000>; 4163 4164 frame@17c21000 { 4165 frame-number = <0>; 4166 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4168 reg = <0 0x17c21000 0 0x1000>, 4169 <0 0x17c22000 0 0x1000>; 4170 }; 4171 4172 frame@17c23000 { 4173 frame-number = <1>; 4174 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4175 reg = <0 0x17c23000 0 0x1000>; 4176 status = "disabled"; 4177 }; 4178 4179 frame@17c25000 { 4180 frame-number = <2>; 4181 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4182 reg = <0 0x17c25000 0 0x1000>; 4183 status = "disabled"; 4184 }; 4185 4186 frame@17c27000 { 4187 frame-number = <3>; 4188 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4189 reg = <0 0x17c27000 0 0x1000>; 4190 status = "disabled"; 4191 }; 4192 4193 frame@17c29000 { 4194 frame-number = <4>; 4195 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4196 reg = <0 0x17c29000 0 0x1000>; 4197 status = "disabled"; 4198 }; 4199 4200 frame@17c2b000 { 4201 frame-number = <5>; 4202 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4203 reg = <0 0x17c2b000 0 0x1000>; 4204 status = "disabled"; 4205 }; 4206 4207 frame@17c2d000 { 4208 frame-number = <6>; 4209 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4210 reg = <0 0x17c2d000 0 0x1000>; 4211 status = "disabled"; 4212 }; 4213 }; 4214 4215 apps_rsc: rsc@18200000 { 4216 compatible = "qcom,rpmh-rsc"; 4217 reg = <0 0x18200000 0 0x10000>, 4218 <0 0x18210000 0 0x10000>, 4219 <0 0x18220000 0 0x10000>; 4220 reg-names = "drv-0", "drv-1", "drv-2"; 4221 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4224 qcom,tcs-offset = <0xd00>; 4225 qcom,drv-id = <2>; 4226 qcom,tcs-config = <ACTIVE_TCS 2>, 4227 <SLEEP_TCS 3>, 4228 <WAKE_TCS 3>, 4229 <CONTROL_TCS 1>; 4230 4231 apps_bcm_voter: bcm-voter { 4232 compatible = "qcom,bcm-voter"; 4233 }; 4234 4235 rpmhpd: power-controller { 4236 compatible = "qcom,sc7280-rpmhpd"; 4237 #power-domain-cells = <1>; 4238 operating-points-v2 = <&rpmhpd_opp_table>; 4239 4240 rpmhpd_opp_table: opp-table { 4241 compatible = "operating-points-v2"; 4242 4243 rpmhpd_opp_ret: opp1 { 4244 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4245 }; 4246 4247 rpmhpd_opp_low_svs: opp2 { 4248 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4249 }; 4250 4251 rpmhpd_opp_svs: opp3 { 4252 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4253 }; 4254 4255 rpmhpd_opp_svs_l1: opp4 { 4256 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4257 }; 4258 4259 rpmhpd_opp_svs_l2: opp5 { 4260 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4261 }; 4262 4263 rpmhpd_opp_nom: opp6 { 4264 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4265 }; 4266 4267 rpmhpd_opp_nom_l1: opp7 { 4268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4269 }; 4270 4271 rpmhpd_opp_turbo: opp8 { 4272 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4273 }; 4274 4275 rpmhpd_opp_turbo_l1: opp9 { 4276 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4277 }; 4278 }; 4279 }; 4280 4281 rpmhcc: clock-controller { 4282 compatible = "qcom,sc7280-rpmh-clk"; 4283 clocks = <&xo_board>; 4284 clock-names = "xo"; 4285 #clock-cells = <1>; 4286 }; 4287 }; 4288 4289 cpufreq_hw: cpufreq@18591000 { 4290 compatible = "qcom,cpufreq-epss"; 4291 reg = <0 0x18591000 0 0x1000>, 4292 <0 0x18592000 0 0x1000>, 4293 <0 0x18593000 0 0x1000>; 4294 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4295 clock-names = "xo", "alternate"; 4296 #freq-domain-cells = <1>; 4297 }; 4298 }; 4299 4300 thermal_zones: thermal-zones { 4301 cpu0-thermal { 4302 polling-delay-passive = <250>; 4303 polling-delay = <0>; 4304 4305 thermal-sensors = <&tsens0 1>; 4306 4307 trips { 4308 cpu0_alert0: trip-point0 { 4309 temperature = <90000>; 4310 hysteresis = <2000>; 4311 type = "passive"; 4312 }; 4313 4314 cpu0_alert1: trip-point1 { 4315 temperature = <95000>; 4316 hysteresis = <2000>; 4317 type = "passive"; 4318 }; 4319 4320 cpu0_crit: cpu-crit { 4321 temperature = <110000>; 4322 hysteresis = <0>; 4323 type = "critical"; 4324 }; 4325 }; 4326 4327 cooling-maps { 4328 map0 { 4329 trip = <&cpu0_alert0>; 4330 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4331 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4332 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4333 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4334 }; 4335 map1 { 4336 trip = <&cpu0_alert1>; 4337 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4338 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4339 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4340 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4341 }; 4342 }; 4343 }; 4344 4345 cpu1-thermal { 4346 polling-delay-passive = <250>; 4347 polling-delay = <0>; 4348 4349 thermal-sensors = <&tsens0 2>; 4350 4351 trips { 4352 cpu1_alert0: trip-point0 { 4353 temperature = <90000>; 4354 hysteresis = <2000>; 4355 type = "passive"; 4356 }; 4357 4358 cpu1_alert1: trip-point1 { 4359 temperature = <95000>; 4360 hysteresis = <2000>; 4361 type = "passive"; 4362 }; 4363 4364 cpu1_crit: cpu-crit { 4365 temperature = <110000>; 4366 hysteresis = <0>; 4367 type = "critical"; 4368 }; 4369 }; 4370 4371 cooling-maps { 4372 map0 { 4373 trip = <&cpu1_alert0>; 4374 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4375 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4376 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4377 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4378 }; 4379 map1 { 4380 trip = <&cpu1_alert1>; 4381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4382 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4383 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4384 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4385 }; 4386 }; 4387 }; 4388 4389 cpu2-thermal { 4390 polling-delay-passive = <250>; 4391 polling-delay = <0>; 4392 4393 thermal-sensors = <&tsens0 3>; 4394 4395 trips { 4396 cpu2_alert0: trip-point0 { 4397 temperature = <90000>; 4398 hysteresis = <2000>; 4399 type = "passive"; 4400 }; 4401 4402 cpu2_alert1: trip-point1 { 4403 temperature = <95000>; 4404 hysteresis = <2000>; 4405 type = "passive"; 4406 }; 4407 4408 cpu2_crit: cpu-crit { 4409 temperature = <110000>; 4410 hysteresis = <0>; 4411 type = "critical"; 4412 }; 4413 }; 4414 4415 cooling-maps { 4416 map0 { 4417 trip = <&cpu2_alert0>; 4418 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4419 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4420 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4421 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4422 }; 4423 map1 { 4424 trip = <&cpu2_alert1>; 4425 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4426 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4427 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4428 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4429 }; 4430 }; 4431 }; 4432 4433 cpu3-thermal { 4434 polling-delay-passive = <250>; 4435 polling-delay = <0>; 4436 4437 thermal-sensors = <&tsens0 4>; 4438 4439 trips { 4440 cpu3_alert0: trip-point0 { 4441 temperature = <90000>; 4442 hysteresis = <2000>; 4443 type = "passive"; 4444 }; 4445 4446 cpu3_alert1: trip-point1 { 4447 temperature = <95000>; 4448 hysteresis = <2000>; 4449 type = "passive"; 4450 }; 4451 4452 cpu3_crit: cpu-crit { 4453 temperature = <110000>; 4454 hysteresis = <0>; 4455 type = "critical"; 4456 }; 4457 }; 4458 4459 cooling-maps { 4460 map0 { 4461 trip = <&cpu3_alert0>; 4462 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4464 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4465 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4466 }; 4467 map1 { 4468 trip = <&cpu3_alert1>; 4469 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4470 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4471 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4472 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4473 }; 4474 }; 4475 }; 4476 4477 cpu4-thermal { 4478 polling-delay-passive = <250>; 4479 polling-delay = <0>; 4480 4481 thermal-sensors = <&tsens0 7>; 4482 4483 trips { 4484 cpu4_alert0: trip-point0 { 4485 temperature = <90000>; 4486 hysteresis = <2000>; 4487 type = "passive"; 4488 }; 4489 4490 cpu4_alert1: trip-point1 { 4491 temperature = <95000>; 4492 hysteresis = <2000>; 4493 type = "passive"; 4494 }; 4495 4496 cpu4_crit: cpu-crit { 4497 temperature = <110000>; 4498 hysteresis = <0>; 4499 type = "critical"; 4500 }; 4501 }; 4502 4503 cooling-maps { 4504 map0 { 4505 trip = <&cpu4_alert0>; 4506 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4508 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4509 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4510 }; 4511 map1 { 4512 trip = <&cpu4_alert1>; 4513 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4514 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4515 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4516 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4517 }; 4518 }; 4519 }; 4520 4521 cpu5-thermal { 4522 polling-delay-passive = <250>; 4523 polling-delay = <0>; 4524 4525 thermal-sensors = <&tsens0 8>; 4526 4527 trips { 4528 cpu5_alert0: trip-point0 { 4529 temperature = <90000>; 4530 hysteresis = <2000>; 4531 type = "passive"; 4532 }; 4533 4534 cpu5_alert1: trip-point1 { 4535 temperature = <95000>; 4536 hysteresis = <2000>; 4537 type = "passive"; 4538 }; 4539 4540 cpu5_crit: cpu-crit { 4541 temperature = <110000>; 4542 hysteresis = <0>; 4543 type = "critical"; 4544 }; 4545 }; 4546 4547 cooling-maps { 4548 map0 { 4549 trip = <&cpu5_alert0>; 4550 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4552 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4553 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4554 }; 4555 map1 { 4556 trip = <&cpu5_alert1>; 4557 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4558 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4559 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4560 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4561 }; 4562 }; 4563 }; 4564 4565 cpu6-thermal { 4566 polling-delay-passive = <250>; 4567 polling-delay = <0>; 4568 4569 thermal-sensors = <&tsens0 9>; 4570 4571 trips { 4572 cpu6_alert0: trip-point0 { 4573 temperature = <90000>; 4574 hysteresis = <2000>; 4575 type = "passive"; 4576 }; 4577 4578 cpu6_alert1: trip-point1 { 4579 temperature = <95000>; 4580 hysteresis = <2000>; 4581 type = "passive"; 4582 }; 4583 4584 cpu6_crit: cpu-crit { 4585 temperature = <110000>; 4586 hysteresis = <0>; 4587 type = "critical"; 4588 }; 4589 }; 4590 4591 cooling-maps { 4592 map0 { 4593 trip = <&cpu6_alert0>; 4594 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4596 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4597 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4598 }; 4599 map1 { 4600 trip = <&cpu6_alert1>; 4601 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4602 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4603 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4604 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4605 }; 4606 }; 4607 }; 4608 4609 cpu7-thermal { 4610 polling-delay-passive = <250>; 4611 polling-delay = <0>; 4612 4613 thermal-sensors = <&tsens0 10>; 4614 4615 trips { 4616 cpu7_alert0: trip-point0 { 4617 temperature = <90000>; 4618 hysteresis = <2000>; 4619 type = "passive"; 4620 }; 4621 4622 cpu7_alert1: trip-point1 { 4623 temperature = <95000>; 4624 hysteresis = <2000>; 4625 type = "passive"; 4626 }; 4627 4628 cpu7_crit: cpu-crit { 4629 temperature = <110000>; 4630 hysteresis = <0>; 4631 type = "critical"; 4632 }; 4633 }; 4634 4635 cooling-maps { 4636 map0 { 4637 trip = <&cpu7_alert0>; 4638 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4640 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4642 }; 4643 map1 { 4644 trip = <&cpu7_alert1>; 4645 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4646 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4647 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4648 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4649 }; 4650 }; 4651 }; 4652 4653 cpu8-thermal { 4654 polling-delay-passive = <250>; 4655 polling-delay = <0>; 4656 4657 thermal-sensors = <&tsens0 11>; 4658 4659 trips { 4660 cpu8_alert0: trip-point0 { 4661 temperature = <90000>; 4662 hysteresis = <2000>; 4663 type = "passive"; 4664 }; 4665 4666 cpu8_alert1: trip-point1 { 4667 temperature = <95000>; 4668 hysteresis = <2000>; 4669 type = "passive"; 4670 }; 4671 4672 cpu8_crit: cpu-crit { 4673 temperature = <110000>; 4674 hysteresis = <0>; 4675 type = "critical"; 4676 }; 4677 }; 4678 4679 cooling-maps { 4680 map0 { 4681 trip = <&cpu8_alert0>; 4682 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4686 }; 4687 map1 { 4688 trip = <&cpu8_alert1>; 4689 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4690 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4691 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4692 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4693 }; 4694 }; 4695 }; 4696 4697 cpu9-thermal { 4698 polling-delay-passive = <250>; 4699 polling-delay = <0>; 4700 4701 thermal-sensors = <&tsens0 12>; 4702 4703 trips { 4704 cpu9_alert0: trip-point0 { 4705 temperature = <90000>; 4706 hysteresis = <2000>; 4707 type = "passive"; 4708 }; 4709 4710 cpu9_alert1: trip-point1 { 4711 temperature = <95000>; 4712 hysteresis = <2000>; 4713 type = "passive"; 4714 }; 4715 4716 cpu9_crit: cpu-crit { 4717 temperature = <110000>; 4718 hysteresis = <0>; 4719 type = "critical"; 4720 }; 4721 }; 4722 4723 cooling-maps { 4724 map0 { 4725 trip = <&cpu9_alert0>; 4726 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4730 }; 4731 map1 { 4732 trip = <&cpu9_alert1>; 4733 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4734 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4736 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4737 }; 4738 }; 4739 }; 4740 4741 cpu10-thermal { 4742 polling-delay-passive = <250>; 4743 polling-delay = <0>; 4744 4745 thermal-sensors = <&tsens0 13>; 4746 4747 trips { 4748 cpu10_alert0: trip-point0 { 4749 temperature = <90000>; 4750 hysteresis = <2000>; 4751 type = "passive"; 4752 }; 4753 4754 cpu10_alert1: trip-point1 { 4755 temperature = <95000>; 4756 hysteresis = <2000>; 4757 type = "passive"; 4758 }; 4759 4760 cpu10_crit: cpu-crit { 4761 temperature = <110000>; 4762 hysteresis = <0>; 4763 type = "critical"; 4764 }; 4765 }; 4766 4767 cooling-maps { 4768 map0 { 4769 trip = <&cpu10_alert0>; 4770 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4774 }; 4775 map1 { 4776 trip = <&cpu10_alert1>; 4777 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4779 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4780 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4781 }; 4782 }; 4783 }; 4784 4785 cpu11-thermal { 4786 polling-delay-passive = <250>; 4787 polling-delay = <0>; 4788 4789 thermal-sensors = <&tsens0 14>; 4790 4791 trips { 4792 cpu11_alert0: trip-point0 { 4793 temperature = <90000>; 4794 hysteresis = <2000>; 4795 type = "passive"; 4796 }; 4797 4798 cpu11_alert1: trip-point1 { 4799 temperature = <95000>; 4800 hysteresis = <2000>; 4801 type = "passive"; 4802 }; 4803 4804 cpu11_crit: cpu-crit { 4805 temperature = <110000>; 4806 hysteresis = <0>; 4807 type = "critical"; 4808 }; 4809 }; 4810 4811 cooling-maps { 4812 map0 { 4813 trip = <&cpu11_alert0>; 4814 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4818 }; 4819 map1 { 4820 trip = <&cpu11_alert1>; 4821 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4823 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4824 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4825 }; 4826 }; 4827 }; 4828 4829 aoss0-thermal { 4830 polling-delay-passive = <0>; 4831 polling-delay = <0>; 4832 4833 thermal-sensors = <&tsens0 0>; 4834 4835 trips { 4836 aoss0_alert0: trip-point0 { 4837 temperature = <90000>; 4838 hysteresis = <2000>; 4839 type = "hot"; 4840 }; 4841 4842 aoss0_crit: aoss0-crit { 4843 temperature = <110000>; 4844 hysteresis = <0>; 4845 type = "critical"; 4846 }; 4847 }; 4848 }; 4849 4850 aoss1-thermal { 4851 polling-delay-passive = <0>; 4852 polling-delay = <0>; 4853 4854 thermal-sensors = <&tsens1 0>; 4855 4856 trips { 4857 aoss1_alert0: trip-point0 { 4858 temperature = <90000>; 4859 hysteresis = <2000>; 4860 type = "hot"; 4861 }; 4862 4863 aoss1_crit: aoss1-crit { 4864 temperature = <110000>; 4865 hysteresis = <0>; 4866 type = "critical"; 4867 }; 4868 }; 4869 }; 4870 4871 cpuss0-thermal { 4872 polling-delay-passive = <0>; 4873 polling-delay = <0>; 4874 4875 thermal-sensors = <&tsens0 5>; 4876 4877 trips { 4878 cpuss0_alert0: trip-point0 { 4879 temperature = <90000>; 4880 hysteresis = <2000>; 4881 type = "hot"; 4882 }; 4883 cpuss0_crit: cluster0-crit { 4884 temperature = <110000>; 4885 hysteresis = <0>; 4886 type = "critical"; 4887 }; 4888 }; 4889 }; 4890 4891 cpuss1-thermal { 4892 polling-delay-passive = <0>; 4893 polling-delay = <0>; 4894 4895 thermal-sensors = <&tsens0 6>; 4896 4897 trips { 4898 cpuss1_alert0: trip-point0 { 4899 temperature = <90000>; 4900 hysteresis = <2000>; 4901 type = "hot"; 4902 }; 4903 cpuss1_crit: cluster0-crit { 4904 temperature = <110000>; 4905 hysteresis = <0>; 4906 type = "critical"; 4907 }; 4908 }; 4909 }; 4910 4911 gpuss0-thermal { 4912 polling-delay-passive = <100>; 4913 polling-delay = <0>; 4914 4915 thermal-sensors = <&tsens1 1>; 4916 4917 trips { 4918 gpuss0_alert0: trip-point0 { 4919 temperature = <95000>; 4920 hysteresis = <2000>; 4921 type = "passive"; 4922 }; 4923 4924 gpuss0_crit: gpuss0-crit { 4925 temperature = <110000>; 4926 hysteresis = <0>; 4927 type = "critical"; 4928 }; 4929 }; 4930 4931 cooling-maps { 4932 map0 { 4933 trip = <&gpuss0_alert0>; 4934 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4935 }; 4936 }; 4937 }; 4938 4939 gpuss1-thermal { 4940 polling-delay-passive = <100>; 4941 polling-delay = <0>; 4942 4943 thermal-sensors = <&tsens1 2>; 4944 4945 trips { 4946 gpuss1_alert0: trip-point0 { 4947 temperature = <95000>; 4948 hysteresis = <2000>; 4949 type = "passive"; 4950 }; 4951 4952 gpuss1_crit: gpuss1-crit { 4953 temperature = <110000>; 4954 hysteresis = <0>; 4955 type = "critical"; 4956 }; 4957 }; 4958 4959 cooling-maps { 4960 map0 { 4961 trip = <&gpuss1_alert0>; 4962 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4963 }; 4964 }; 4965 }; 4966 4967 nspss0-thermal { 4968 polling-delay-passive = <0>; 4969 polling-delay = <0>; 4970 4971 thermal-sensors = <&tsens1 3>; 4972 4973 trips { 4974 nspss0_alert0: trip-point0 { 4975 temperature = <90000>; 4976 hysteresis = <2000>; 4977 type = "hot"; 4978 }; 4979 4980 nspss0_crit: nspss0-crit { 4981 temperature = <110000>; 4982 hysteresis = <0>; 4983 type = "critical"; 4984 }; 4985 }; 4986 }; 4987 4988 nspss1-thermal { 4989 polling-delay-passive = <0>; 4990 polling-delay = <0>; 4991 4992 thermal-sensors = <&tsens1 4>; 4993 4994 trips { 4995 nspss1_alert0: trip-point0 { 4996 temperature = <90000>; 4997 hysteresis = <2000>; 4998 type = "hot"; 4999 }; 5000 5001 nspss1_crit: nspss1-crit { 5002 temperature = <110000>; 5003 hysteresis = <0>; 5004 type = "critical"; 5005 }; 5006 }; 5007 }; 5008 5009 video-thermal { 5010 polling-delay-passive = <0>; 5011 polling-delay = <0>; 5012 5013 thermal-sensors = <&tsens1 5>; 5014 5015 trips { 5016 video_alert0: trip-point0 { 5017 temperature = <90000>; 5018 hysteresis = <2000>; 5019 type = "hot"; 5020 }; 5021 5022 video_crit: video-crit { 5023 temperature = <110000>; 5024 hysteresis = <0>; 5025 type = "critical"; 5026 }; 5027 }; 5028 }; 5029 5030 ddr-thermal { 5031 polling-delay-passive = <0>; 5032 polling-delay = <0>; 5033 5034 thermal-sensors = <&tsens1 6>; 5035 5036 trips { 5037 ddr_alert0: trip-point0 { 5038 temperature = <90000>; 5039 hysteresis = <2000>; 5040 type = "hot"; 5041 }; 5042 5043 ddr_crit: ddr-crit { 5044 temperature = <110000>; 5045 hysteresis = <0>; 5046 type = "critical"; 5047 }; 5048 }; 5049 }; 5050 5051 mdmss0-thermal { 5052 polling-delay-passive = <0>; 5053 polling-delay = <0>; 5054 5055 thermal-sensors = <&tsens1 7>; 5056 5057 trips { 5058 mdmss0_alert0: trip-point0 { 5059 temperature = <90000>; 5060 hysteresis = <2000>; 5061 type = "hot"; 5062 }; 5063 5064 mdmss0_crit: mdmss0-crit { 5065 temperature = <110000>; 5066 hysteresis = <0>; 5067 type = "critical"; 5068 }; 5069 }; 5070 }; 5071 5072 mdmss1-thermal { 5073 polling-delay-passive = <0>; 5074 polling-delay = <0>; 5075 5076 thermal-sensors = <&tsens1 8>; 5077 5078 trips { 5079 mdmss1_alert0: trip-point0 { 5080 temperature = <90000>; 5081 hysteresis = <2000>; 5082 type = "hot"; 5083 }; 5084 5085 mdmss1_crit: mdmss1-crit { 5086 temperature = <110000>; 5087 hysteresis = <0>; 5088 type = "critical"; 5089 }; 5090 }; 5091 }; 5092 5093 mdmss2-thermal { 5094 polling-delay-passive = <0>; 5095 polling-delay = <0>; 5096 5097 thermal-sensors = <&tsens1 9>; 5098 5099 trips { 5100 mdmss2_alert0: trip-point0 { 5101 temperature = <90000>; 5102 hysteresis = <2000>; 5103 type = "hot"; 5104 }; 5105 5106 mdmss2_crit: mdmss2-crit { 5107 temperature = <110000>; 5108 hysteresis = <0>; 5109 type = "critical"; 5110 }; 5111 }; 5112 }; 5113 5114 mdmss3-thermal { 5115 polling-delay-passive = <0>; 5116 polling-delay = <0>; 5117 5118 thermal-sensors = <&tsens1 10>; 5119 5120 trips { 5121 mdmss3_alert0: trip-point0 { 5122 temperature = <90000>; 5123 hysteresis = <2000>; 5124 type = "hot"; 5125 }; 5126 5127 mdmss3_crit: mdmss3-crit { 5128 temperature = <110000>; 5129 hysteresis = <0>; 5130 type = "critical"; 5131 }; 5132 }; 5133 }; 5134 5135 camera0-thermal { 5136 polling-delay-passive = <0>; 5137 polling-delay = <0>; 5138 5139 thermal-sensors = <&tsens1 11>; 5140 5141 trips { 5142 camera0_alert0: trip-point0 { 5143 temperature = <90000>; 5144 hysteresis = <2000>; 5145 type = "hot"; 5146 }; 5147 5148 camera0_crit: camera0-crit { 5149 temperature = <110000>; 5150 hysteresis = <0>; 5151 type = "critical"; 5152 }; 5153 }; 5154 }; 5155 }; 5156 5157 timer { 5158 compatible = "arm,armv8-timer"; 5159 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5160 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5161 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5162 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5163 }; 5164}; 5165