1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sc7280.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 i2c12 = &i2c12; 45 i2c13 = &i2c13; 46 i2c14 = &i2c14; 47 i2c15 = &i2c15; 48 mmc1 = &sdhc_1; 49 mmc2 = &sdhc_2; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 clocks { 69 xo_board: xo-board { 70 compatible = "fixed-clock"; 71 clock-frequency = <76800000>; 72 #clock-cells = <0>; 73 }; 74 75 sleep_clk: sleep-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 reserved-memory { 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges; 86 87 hyp_mem: memory@80000000 { 88 reg = <0x0 0x80000000 0x0 0x600000>; 89 no-map; 90 }; 91 92 xbl_mem: memory@80600000 { 93 reg = <0x0 0x80600000 0x0 0x200000>; 94 no-map; 95 }; 96 97 aop_mem: memory@80800000 { 98 reg = <0x0 0x80800000 0x0 0x60000>; 99 no-map; 100 }; 101 102 aop_cmd_db_mem: memory@80860000 { 103 reg = <0x0 0x80860000 0x0 0x20000>; 104 compatible = "qcom,cmd-db"; 105 no-map; 106 }; 107 108 reserved_xbl_uefi_log: memory@80880000 { 109 reg = <0x0 0x80884000 0x0 0x10000>; 110 no-map; 111 }; 112 113 sec_apps_mem: memory@808ff000 { 114 reg = <0x0 0x808ff000 0x0 0x1000>; 115 no-map; 116 }; 117 118 smem_mem: memory@80900000 { 119 reg = <0x0 0x80900000 0x0 0x200000>; 120 no-map; 121 }; 122 123 cpucp_mem: memory@80b00000 { 124 no-map; 125 reg = <0x0 0x80b00000 0x0 0x100000>; 126 }; 127 128 wlan_fw_mem: memory@80c00000 { 129 reg = <0x0 0x80c00000 0x0 0xc00000>; 130 no-map; 131 }; 132 133 video_mem: memory@8b200000 { 134 reg = <0x0 0x8b200000 0x0 0x500000>; 135 no-map; 136 }; 137 138 ipa_fw_mem: memory@8b700000 { 139 reg = <0 0x8b700000 0 0x10000>; 140 no-map; 141 }; 142 143 rmtfs_mem: memory@9c900000 { 144 compatible = "qcom,rmtfs-mem"; 145 reg = <0x0 0x9c900000 0x0 0x280000>; 146 no-map; 147 148 qcom,client-id = <1>; 149 qcom,vmid = <15>; 150 }; 151 }; 152 153 cpus { 154 #address-cells = <2>; 155 #size-cells = <0>; 156 157 CPU0: cpu@0 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x0>; 161 enable-method = "psci"; 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 163 &LITTLE_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_0>; 166 qcom,freq-domain = <&cpufreq_hw 0>; 167 #cooling-cells = <2>; 168 L2_0: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 L3_0: l3-cache { 172 compatible = "cache"; 173 }; 174 }; 175 }; 176 177 CPU1: cpu@100 { 178 device_type = "cpu"; 179 compatible = "arm,kryo"; 180 reg = <0x0 0x100>; 181 enable-method = "psci"; 182 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 183 &LITTLE_CPU_SLEEP_1 184 &CLUSTER_SLEEP_0>; 185 next-level-cache = <&L2_100>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 #cooling-cells = <2>; 188 L2_100: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU2: cpu@200 { 195 device_type = "cpu"; 196 compatible = "arm,kryo"; 197 reg = <0x0 0x200>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_200>; 203 qcom,freq-domain = <&cpufreq_hw 0>; 204 #cooling-cells = <2>; 205 L2_200: l2-cache { 206 compatible = "cache"; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU3: cpu@300 { 212 device_type = "cpu"; 213 compatible = "arm,kryo"; 214 reg = <0x0 0x300>; 215 enable-method = "psci"; 216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 217 &LITTLE_CPU_SLEEP_1 218 &CLUSTER_SLEEP_0>; 219 next-level-cache = <&L2_300>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_300: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU4: cpu@400 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x400>; 232 enable-method = "psci"; 233 cpu-idle-states = <&BIG_CPU_SLEEP_0 234 &BIG_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_400>; 237 qcom,freq-domain = <&cpufreq_hw 1>; 238 #cooling-cells = <2>; 239 L2_400: l2-cache { 240 compatible = "cache"; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 CPU5: cpu@500 { 246 device_type = "cpu"; 247 compatible = "arm,kryo"; 248 reg = <0x0 0x500>; 249 enable-method = "psci"; 250 cpu-idle-states = <&BIG_CPU_SLEEP_0 251 &BIG_CPU_SLEEP_1 252 &CLUSTER_SLEEP_0>; 253 next-level-cache = <&L2_500>; 254 qcom,freq-domain = <&cpufreq_hw 1>; 255 #cooling-cells = <2>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "arm,kryo"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 next-level-cache = <&L2_600>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 #cooling-cells = <2>; 273 L2_600: l2-cache { 274 compatible = "cache"; 275 next-level-cache = <&L3_0>; 276 }; 277 }; 278 279 CPU7: cpu@700 { 280 device_type = "cpu"; 281 compatible = "arm,kryo"; 282 reg = <0x0 0x700>; 283 enable-method = "psci"; 284 cpu-idle-states = <&BIG_CPU_SLEEP_0 285 &BIG_CPU_SLEEP_1 286 &CLUSTER_SLEEP_0>; 287 next-level-cache = <&L2_700>; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 #cooling-cells = <2>; 290 L2_700: l2-cache { 291 compatible = "cache"; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 cpu-map { 297 cluster0 { 298 core0 { 299 cpu = <&CPU0>; 300 }; 301 302 core1 { 303 cpu = <&CPU1>; 304 }; 305 306 core2 { 307 cpu = <&CPU2>; 308 }; 309 310 core3 { 311 cpu = <&CPU3>; 312 }; 313 314 core4 { 315 cpu = <&CPU4>; 316 }; 317 318 core5 { 319 cpu = <&CPU5>; 320 }; 321 322 core6 { 323 cpu = <&CPU6>; 324 }; 325 326 core7 { 327 cpu = <&CPU7>; 328 }; 329 }; 330 }; 331 332 idle-states { 333 entry-method = "psci"; 334 335 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "little-power-down"; 338 arm,psci-suspend-param = <0x40000003>; 339 entry-latency-us = <549>; 340 exit-latency-us = <901>; 341 min-residency-us = <1774>; 342 local-timer-stop; 343 }; 344 345 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-rail-power-down"; 348 arm,psci-suspend-param = <0x40000004>; 349 entry-latency-us = <702>; 350 exit-latency-us = <915>; 351 min-residency-us = <4001>; 352 local-timer-stop; 353 }; 354 355 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "big-power-down"; 358 arm,psci-suspend-param = <0x40000003>; 359 entry-latency-us = <523>; 360 exit-latency-us = <1244>; 361 min-residency-us = <2207>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-rail-power-down"; 368 arm,psci-suspend-param = <0x40000004>; 369 entry-latency-us = <526>; 370 exit-latency-us = <1854>; 371 min-residency-us = <5555>; 372 local-timer-stop; 373 }; 374 375 CLUSTER_SLEEP_0: cluster-sleep-0 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "cluster-power-down"; 378 arm,psci-suspend-param = <0x40003444>; 379 entry-latency-us = <3263>; 380 exit-latency-us = <6562>; 381 min-residency-us = <9926>; 382 local-timer-stop; 383 }; 384 }; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0 0x80000000 0 0>; 391 }; 392 393 firmware { 394 scm { 395 compatible = "qcom,scm-sc7280", "qcom,scm"; 396 }; 397 }; 398 399 clk_virt: interconnect { 400 compatible = "qcom,sc7280-clk-virt"; 401 #interconnect-cells = <2>; 402 qcom,bcm-voters = <&apps_bcm_voter>; 403 }; 404 405 smem { 406 compatible = "qcom,smem"; 407 memory-region = <&smem_mem>; 408 hwlocks = <&tcsr_mutex 3>; 409 }; 410 411 smp2p-adsp { 412 compatible = "qcom,smp2p"; 413 qcom,smem = <443>, <429>; 414 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 415 IPCC_MPROC_SIGNAL_SMP2P 416 IRQ_TYPE_EDGE_RISING>; 417 mboxes = <&ipcc IPCC_CLIENT_LPASS 418 IPCC_MPROC_SIGNAL_SMP2P>; 419 420 qcom,local-pid = <0>; 421 qcom,remote-pid = <2>; 422 423 adsp_smp2p_out: master-kernel { 424 qcom,entry-name = "master-kernel"; 425 #qcom,smem-state-cells = <1>; 426 }; 427 428 adsp_smp2p_in: slave-kernel { 429 qcom,entry-name = "slave-kernel"; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 }; 433 }; 434 435 smp2p-cdsp { 436 compatible = "qcom,smp2p"; 437 qcom,smem = <94>, <432>; 438 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 439 IPCC_MPROC_SIGNAL_SMP2P 440 IRQ_TYPE_EDGE_RISING>; 441 mboxes = <&ipcc IPCC_CLIENT_CDSP 442 IPCC_MPROC_SIGNAL_SMP2P>; 443 444 qcom,local-pid = <0>; 445 qcom,remote-pid = <5>; 446 447 cdsp_smp2p_out: master-kernel { 448 qcom,entry-name = "master-kernel"; 449 #qcom,smem-state-cells = <1>; 450 }; 451 452 cdsp_smp2p_in: slave-kernel { 453 qcom,entry-name = "slave-kernel"; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smp2p-mpss { 460 compatible = "qcom,smp2p"; 461 qcom,smem = <435>, <428>; 462 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 463 IPCC_MPROC_SIGNAL_SMP2P 464 IRQ_TYPE_EDGE_RISING>; 465 mboxes = <&ipcc IPCC_CLIENT_MPSS 466 IPCC_MPROC_SIGNAL_SMP2P>; 467 468 qcom,local-pid = <0>; 469 qcom,remote-pid = <1>; 470 471 modem_smp2p_out: master-kernel { 472 qcom,entry-name = "master-kernel"; 473 #qcom,smem-state-cells = <1>; 474 }; 475 476 modem_smp2p_in: slave-kernel { 477 qcom,entry-name = "slave-kernel"; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 }; 481 482 ipa_smp2p_out: ipa-ap-to-modem { 483 qcom,entry-name = "ipa"; 484 #qcom,smem-state-cells = <1>; 485 }; 486 487 ipa_smp2p_in: ipa-modem-to-ap { 488 qcom,entry-name = "ipa"; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 }; 492 }; 493 494 smp2p-wpss { 495 compatible = "qcom,smp2p"; 496 qcom,smem = <617>, <616>; 497 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 498 IPCC_MPROC_SIGNAL_SMP2P 499 IRQ_TYPE_EDGE_RISING>; 500 mboxes = <&ipcc IPCC_CLIENT_WPSS 501 IPCC_MPROC_SIGNAL_SMP2P>; 502 503 qcom,local-pid = <0>; 504 qcom,remote-pid = <13>; 505 506 wpss_smp2p_out: master-kernel { 507 qcom,entry-name = "master-kernel"; 508 #qcom,smem-state-cells = <1>; 509 }; 510 511 wpss_smp2p_in: slave-kernel { 512 qcom,entry-name = "slave-kernel"; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 }; 517 518 pmu { 519 compatible = "arm,armv8-pmuv3"; 520 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 521 }; 522 523 psci { 524 compatible = "arm,psci-1.0"; 525 method = "smc"; 526 }; 527 528 qspi_opp_table: qspi-opp-table { 529 compatible = "operating-points-v2"; 530 531 opp-75000000 { 532 opp-hz = /bits/ 64 <75000000>; 533 required-opps = <&rpmhpd_opp_low_svs>; 534 }; 535 536 opp-150000000 { 537 opp-hz = /bits/ 64 <150000000>; 538 required-opps = <&rpmhpd_opp_svs>; 539 }; 540 541 opp-200000000 { 542 opp-hz = /bits/ 64 <200000000>; 543 required-opps = <&rpmhpd_opp_svs_l1>; 544 }; 545 546 opp-300000000 { 547 opp-hz = /bits/ 64 <300000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 }; 550 }; 551 552 qup_opp_table: qup-opp-table { 553 compatible = "operating-points-v2"; 554 555 opp-75000000 { 556 opp-hz = /bits/ 64 <75000000>; 557 required-opps = <&rpmhpd_opp_low_svs>; 558 }; 559 560 opp-100000000 { 561 opp-hz = /bits/ 64 <100000000>; 562 required-opps = <&rpmhpd_opp_svs>; 563 }; 564 565 opp-128000000 { 566 opp-hz = /bits/ 64 <128000000>; 567 required-opps = <&rpmhpd_opp_nom>; 568 }; 569 }; 570 571 soc: soc@0 { 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges = <0 0 0 0 0x10 0>; 575 dma-ranges = <0 0 0 0 0x10 0>; 576 compatible = "simple-bus"; 577 578 gcc: clock-controller@100000 { 579 compatible = "qcom,gcc-sc7280"; 580 reg = <0 0x00100000 0 0x1f0000>; 581 clocks = <&rpmhcc RPMH_CXO_CLK>, 582 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 583 <0>, <&pcie1_lane 0>, 584 <0>, <0>, <0>, <0>; 585 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 586 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 587 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 588 "ufs_phy_tx_symbol_0_clk", 589 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 590 #clock-cells = <1>; 591 #reset-cells = <1>; 592 #power-domain-cells = <1>; 593 }; 594 595 ipcc: mailbox@408000 { 596 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 597 reg = <0 0x00408000 0 0x1000>; 598 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-controller; 600 #interrupt-cells = <3>; 601 #mbox-cells = <2>; 602 }; 603 604 qfprom: efuse@784000 { 605 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 606 reg = <0 0x00784000 0 0xa20>, 607 <0 0x00780000 0 0xa20>, 608 <0 0x00782000 0 0x120>, 609 <0 0x00786000 0 0x1fff>; 610 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 611 clock-names = "core"; 612 power-domains = <&rpmhpd SC7280_MX>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 }; 616 617 sdhc_1: sdhci@7c4000 { 618 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 619 pinctrl-names = "default", "sleep"; 620 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 621 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 622 status = "disabled"; 623 624 reg = <0 0x007c4000 0 0x1000>, 625 <0 0x007c5000 0 0x1000>; 626 reg-names = "hc", "cqhci"; 627 628 iommus = <&apps_smmu 0xc0 0x0>; 629 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "hc_irq", "pwr_irq"; 632 633 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 634 <&gcc GCC_SDCC1_AHB_CLK>, 635 <&rpmhcc RPMH_CXO_CLK>; 636 clock-names = "core", "iface", "xo"; 637 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 639 interconnect-names = "sdhc-ddr","cpu-sdhc"; 640 power-domains = <&rpmhpd SC7280_CX>; 641 operating-points-v2 = <&sdhc1_opp_table>; 642 643 bus-width = <8>; 644 supports-cqe; 645 646 qcom,dll-config = <0x0007642c>; 647 qcom,ddr-config = <0x80040868>; 648 649 mmc-ddr-1_8v; 650 mmc-hs200-1_8v; 651 mmc-hs400-1_8v; 652 mmc-hs400-enhanced-strobe; 653 654 sdhc1_opp_table: opp-table { 655 compatible = "operating-points-v2"; 656 657 opp-100000000 { 658 opp-hz = /bits/ 64 <100000000>; 659 required-opps = <&rpmhpd_opp_low_svs>; 660 opp-peak-kBps = <1800000 400000>; 661 opp-avg-kBps = <100000 0>; 662 }; 663 664 opp-384000000 { 665 opp-hz = /bits/ 64 <384000000>; 666 required-opps = <&rpmhpd_opp_nom>; 667 opp-peak-kBps = <5400000 1600000>; 668 opp-avg-kBps = <390000 0>; 669 }; 670 }; 671 672 }; 673 674 qupv3_id_0: geniqup@9c0000 { 675 compatible = "qcom,geni-se-qup"; 676 reg = <0 0x009c0000 0 0x2000>; 677 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 678 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 679 clock-names = "m-ahb", "s-ahb"; 680 #address-cells = <2>; 681 #size-cells = <2>; 682 ranges; 683 iommus = <&apps_smmu 0x123 0x0>; 684 status = "disabled"; 685 686 i2c0: i2c@980000 { 687 compatible = "qcom,geni-i2c"; 688 reg = <0 0x00980000 0 0x4000>; 689 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 690 clock-names = "se"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&qup_i2c0_data_clk>; 693 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 698 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 699 interconnect-names = "qup-core", "qup-config", 700 "qup-memory"; 701 status = "disabled"; 702 }; 703 704 spi0: spi@980000 { 705 compatible = "qcom,geni-spi"; 706 reg = <0 0x00980000 0 0x4000>; 707 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 708 clock-names = "se"; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 711 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 power-domains = <&rpmhpd SC7280_CX>; 715 operating-points-v2 = <&qup_opp_table>; 716 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 717 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 718 interconnect-names = "qup-core", "qup-config"; 719 status = "disabled"; 720 }; 721 722 uart0: serial@980000 { 723 compatible = "qcom,geni-uart"; 724 reg = <0 0x00980000 0 0x4000>; 725 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 726 clock-names = "se"; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 729 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 730 power-domains = <&rpmhpd SC7280_CX>; 731 operating-points-v2 = <&qup_opp_table>; 732 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 733 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 734 interconnect-names = "qup-core", "qup-config"; 735 status = "disabled"; 736 }; 737 738 i2c1: i2c@984000 { 739 compatible = "qcom,geni-i2c"; 740 reg = <0 0x00984000 0 0x4000>; 741 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 742 clock-names = "se"; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&qup_i2c1_data_clk>; 745 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 749 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 750 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 751 interconnect-names = "qup-core", "qup-config", 752 "qup-memory"; 753 status = "disabled"; 754 }; 755 756 spi1: spi@984000 { 757 compatible = "qcom,geni-spi"; 758 reg = <0 0x00984000 0 0x4000>; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 760 clock-names = "se"; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 763 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 power-domains = <&rpmhpd SC7280_CX>; 767 operating-points-v2 = <&qup_opp_table>; 768 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 770 interconnect-names = "qup-core", "qup-config"; 771 status = "disabled"; 772 }; 773 774 uart1: serial@984000 { 775 compatible = "qcom,geni-uart"; 776 reg = <0 0x00984000 0 0x4000>; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 778 clock-names = "se"; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 781 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 782 power-domains = <&rpmhpd SC7280_CX>; 783 operating-points-v2 = <&qup_opp_table>; 784 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 785 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 786 interconnect-names = "qup-core", "qup-config"; 787 status = "disabled"; 788 }; 789 790 i2c2: i2c@988000 { 791 compatible = "qcom,geni-i2c"; 792 reg = <0 0x00988000 0 0x4000>; 793 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 794 clock-names = "se"; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&qup_i2c2_data_clk>; 797 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 801 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 802 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 803 interconnect-names = "qup-core", "qup-config", 804 "qup-memory"; 805 status = "disabled"; 806 }; 807 808 spi2: spi@988000 { 809 compatible = "qcom,geni-spi"; 810 reg = <0 0x00988000 0 0x4000>; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 812 clock-names = "se"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 815 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 power-domains = <&rpmhpd SC7280_CX>; 819 operating-points-v2 = <&qup_opp_table>; 820 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 821 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 822 interconnect-names = "qup-core", "qup-config"; 823 status = "disabled"; 824 }; 825 826 uart2: serial@988000 { 827 compatible = "qcom,geni-uart"; 828 reg = <0 0x00988000 0 0x4000>; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 830 clock-names = "se"; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 833 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 834 power-domains = <&rpmhpd SC7280_CX>; 835 operating-points-v2 = <&qup_opp_table>; 836 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 837 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 838 interconnect-names = "qup-core", "qup-config"; 839 status = "disabled"; 840 }; 841 842 i2c3: i2c@98c000 { 843 compatible = "qcom,geni-i2c"; 844 reg = <0 0x0098c000 0 0x4000>; 845 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 846 clock-names = "se"; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_i2c3_data_clk>; 849 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 854 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 855 interconnect-names = "qup-core", "qup-config", 856 "qup-memory"; 857 status = "disabled"; 858 }; 859 860 spi3: spi@98c000 { 861 compatible = "qcom,geni-spi"; 862 reg = <0 0x0098c000 0 0x4000>; 863 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 864 clock-names = "se"; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 867 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 operating-points-v2 = <&qup_opp_table>; 872 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 874 interconnect-names = "qup-core", "qup-config"; 875 status = "disabled"; 876 }; 877 878 uart3: serial@98c000 { 879 compatible = "qcom,geni-uart"; 880 reg = <0 0x0098c000 0 0x4000>; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 882 clock-names = "se"; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 885 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&rpmhpd SC7280_CX>; 887 operating-points-v2 = <&qup_opp_table>; 888 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 889 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 890 interconnect-names = "qup-core", "qup-config"; 891 status = "disabled"; 892 }; 893 894 i2c4: i2c@990000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0 0x00990000 0 0x4000>; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 898 clock-names = "se"; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&qup_i2c4_data_clk>; 901 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 906 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 907 interconnect-names = "qup-core", "qup-config", 908 "qup-memory"; 909 status = "disabled"; 910 }; 911 912 spi4: spi@990000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00990000 0 0x4000>; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 916 clock-names = "se"; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 919 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 power-domains = <&rpmhpd SC7280_CX>; 923 operating-points-v2 = <&qup_opp_table>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 926 interconnect-names = "qup-core", "qup-config"; 927 status = "disabled"; 928 }; 929 930 uart4: serial@990000 { 931 compatible = "qcom,geni-uart"; 932 reg = <0 0x00990000 0 0x4000>; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 934 clock-names = "se"; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 937 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 938 power-domains = <&rpmhpd SC7280_CX>; 939 operating-points-v2 = <&qup_opp_table>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 942 interconnect-names = "qup-core", "qup-config"; 943 status = "disabled"; 944 }; 945 946 i2c5: i2c@994000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0 0x00994000 0 0x4000>; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 950 clock-names = "se"; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_i2c5_data_clk>; 953 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 958 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 959 interconnect-names = "qup-core", "qup-config", 960 "qup-memory"; 961 status = "disabled"; 962 }; 963 964 spi5: spi@994000 { 965 compatible = "qcom,geni-spi"; 966 reg = <0 0x00994000 0 0x4000>; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 968 clock-names = "se"; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 971 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 power-domains = <&rpmhpd SC7280_CX>; 975 operating-points-v2 = <&qup_opp_table>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 978 interconnect-names = "qup-core", "qup-config"; 979 status = "disabled"; 980 }; 981 982 uart5: serial@994000 { 983 compatible = "qcom,geni-uart"; 984 reg = <0 0x00994000 0 0x4000>; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 986 clock-names = "se"; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 989 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 990 power-domains = <&rpmhpd SC7280_CX>; 991 operating-points-v2 = <&qup_opp_table>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 status = "disabled"; 996 }; 997 998 i2c6: i2c@998000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0 0x00998000 0 0x4000>; 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1002 clock-names = "se"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c6_data_clk>; 1005 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1009 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1010 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1011 interconnect-names = "qup-core", "qup-config", 1012 "qup-memory"; 1013 status = "disabled"; 1014 }; 1015 1016 spi6: spi@998000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00998000 0 0x4000>; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1020 clock-names = "se"; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1023 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 power-domains = <&rpmhpd SC7280_CX>; 1027 operating-points-v2 = <&qup_opp_table>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1030 interconnect-names = "qup-core", "qup-config"; 1031 status = "disabled"; 1032 }; 1033 1034 uart6: serial@998000 { 1035 compatible = "qcom,geni-uart"; 1036 reg = <0 0x00998000 0 0x4000>; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1038 clock-names = "se"; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1041 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1042 power-domains = <&rpmhpd SC7280_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 status = "disabled"; 1048 }; 1049 1050 i2c7: i2c@99c000 { 1051 compatible = "qcom,geni-i2c"; 1052 reg = <0 0x0099c000 0 0x4000>; 1053 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1054 clock-names = "se"; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_i2c7_data_clk>; 1057 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1062 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", 1064 "qup-memory"; 1065 status = "disabled"; 1066 }; 1067 1068 spi7: spi@99c000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x0099c000 0 0x4000>; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1072 clock-names = "se"; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1075 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 uart7: serial@99c000 { 1087 compatible = "qcom,geni-uart"; 1088 reg = <0 0x0099c000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1093 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1094 power-domains = <&rpmhpd SC7280_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 status = "disabled"; 1100 }; 1101 }; 1102 1103 qupv3_id_1: geniqup@ac0000 { 1104 compatible = "qcom,geni-se-qup"; 1105 reg = <0 0x00ac0000 0 0x2000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1107 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1108 clock-names = "m-ahb", "s-ahb"; 1109 #address-cells = <2>; 1110 #size-cells = <2>; 1111 ranges; 1112 iommus = <&apps_smmu 0x43 0x0>; 1113 status = "disabled"; 1114 1115 i2c8: i2c@a80000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0 0x00a80000 0 0x4000>; 1118 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1119 clock-names = "se"; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c8_data_clk>; 1122 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1127 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", 1129 "qup-memory"; 1130 status = "disabled"; 1131 }; 1132 1133 spi8: spi@a80000 { 1134 compatible = "qcom,geni-spi"; 1135 reg = <0 0x00a80000 0 0x4000>; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1137 clock-names = "se"; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1140 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 power-domains = <&rpmhpd SC7280_CX>; 1144 operating-points-v2 = <&qup_opp_table>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1146 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1147 interconnect-names = "qup-core", "qup-config"; 1148 status = "disabled"; 1149 }; 1150 1151 uart8: serial@a80000 { 1152 compatible = "qcom,geni-uart"; 1153 reg = <0 0x00a80000 0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1155 clock-names = "se"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1158 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 status = "disabled"; 1165 }; 1166 1167 i2c9: i2c@a84000 { 1168 compatible = "qcom,geni-i2c"; 1169 reg = <0 0x00a84000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1171 clock-names = "se"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_i2c9_data_clk>; 1174 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1179 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1180 interconnect-names = "qup-core", "qup-config", 1181 "qup-memory"; 1182 status = "disabled"; 1183 }; 1184 1185 spi9: spi@a84000 { 1186 compatible = "qcom,geni-spi"; 1187 reg = <0 0x00a84000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1192 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 power-domains = <&rpmhpd SC7280_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 status = "disabled"; 1201 }; 1202 1203 uart9: serial@a84000 { 1204 compatible = "qcom,geni-uart"; 1205 reg = <0 0x00a84000 0 0x4000>; 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1207 clock-names = "se"; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1210 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1211 power-domains = <&rpmhpd SC7280_CX>; 1212 operating-points-v2 = <&qup_opp_table>; 1213 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1214 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1215 interconnect-names = "qup-core", "qup-config"; 1216 status = "disabled"; 1217 }; 1218 1219 i2c10: i2c@a88000 { 1220 compatible = "qcom,geni-i2c"; 1221 reg = <0 0x00a88000 0 0x4000>; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1223 clock-names = "se"; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_i2c10_data_clk>; 1226 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1230 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1231 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1232 interconnect-names = "qup-core", "qup-config", 1233 "qup-memory"; 1234 status = "disabled"; 1235 }; 1236 1237 spi10: spi@a88000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00a88000 0 0x4000>; 1240 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1241 clock-names = "se"; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1244 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 power-domains = <&rpmhpd SC7280_CX>; 1248 operating-points-v2 = <&qup_opp_table>; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1250 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1251 interconnect-names = "qup-core", "qup-config"; 1252 status = "disabled"; 1253 }; 1254 1255 uart10: serial@a88000 { 1256 compatible = "qcom,geni-uart"; 1257 reg = <0 0x00a88000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1262 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1263 power-domains = <&rpmhpd SC7280_CX>; 1264 operating-points-v2 = <&qup_opp_table>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 i2c11: i2c@a8c000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0 0x00a8c000 0 0x4000>; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1275 clock-names = "se"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_i2c11_data_clk>; 1278 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1283 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1284 interconnect-names = "qup-core", "qup-config", 1285 "qup-memory"; 1286 status = "disabled"; 1287 }; 1288 1289 spi11: spi@a8c000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00a8c000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 power-domains = <&rpmhpd SC7280_CX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 status = "disabled"; 1305 }; 1306 1307 uart11: serial@a8c000 { 1308 compatible = "qcom,geni-uart"; 1309 reg = <0 0x00a8c000 0 0x4000>; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1311 clock-names = "se"; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1314 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1315 power-domains = <&rpmhpd SC7280_CX>; 1316 operating-points-v2 = <&qup_opp_table>; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1318 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1319 interconnect-names = "qup-core", "qup-config"; 1320 status = "disabled"; 1321 }; 1322 1323 i2c12: i2c@a90000 { 1324 compatible = "qcom,geni-i2c"; 1325 reg = <0 0x00a90000 0 0x4000>; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1327 clock-names = "se"; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_i2c12_data_clk>; 1330 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1334 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1335 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", 1337 "qup-memory"; 1338 status = "disabled"; 1339 }; 1340 1341 spi12: spi@a90000 { 1342 compatible = "qcom,geni-spi"; 1343 reg = <0 0x00a90000 0 0x4000>; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1345 clock-names = "se"; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1348 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 power-domains = <&rpmhpd SC7280_CX>; 1352 operating-points-v2 = <&qup_opp_table>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1355 interconnect-names = "qup-core", "qup-config"; 1356 status = "disabled"; 1357 }; 1358 1359 uart12: serial@a90000 { 1360 compatible = "qcom,geni-uart"; 1361 reg = <0 0x00a90000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1366 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1367 power-domains = <&rpmhpd SC7280_CX>; 1368 operating-points-v2 = <&qup_opp_table>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1371 interconnect-names = "qup-core", "qup-config"; 1372 status = "disabled"; 1373 }; 1374 1375 i2c13: i2c@a94000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x00a94000 0 0x4000>; 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1379 clock-names = "se"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_i2c13_data_clk>; 1382 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1386 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1387 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1388 interconnect-names = "qup-core", "qup-config", 1389 "qup-memory"; 1390 status = "disabled"; 1391 }; 1392 1393 spi13: spi@a94000 { 1394 compatible = "qcom,geni-spi"; 1395 reg = <0 0x00a94000 0 0x4000>; 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1397 clock-names = "se"; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1400 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 power-domains = <&rpmhpd SC7280_CX>; 1404 operating-points-v2 = <&qup_opp_table>; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1406 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 status = "disabled"; 1409 }; 1410 1411 uart13: serial@a94000 { 1412 compatible = "qcom,geni-uart"; 1413 reg = <0 0x00a94000 0 0x4000>; 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1415 clock-names = "se"; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1418 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1419 power-domains = <&rpmhpd SC7280_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 status = "disabled"; 1425 }; 1426 1427 i2c14: i2c@a98000 { 1428 compatible = "qcom,geni-i2c"; 1429 reg = <0 0x00a98000 0 0x4000>; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1431 clock-names = "se"; 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&qup_i2c14_data_clk>; 1434 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1438 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1439 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1440 interconnect-names = "qup-core", "qup-config", 1441 "qup-memory"; 1442 status = "disabled"; 1443 }; 1444 1445 spi14: spi@a98000 { 1446 compatible = "qcom,geni-spi"; 1447 reg = <0 0x00a98000 0 0x4000>; 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1449 clock-names = "se"; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1452 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 power-domains = <&rpmhpd SC7280_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1459 interconnect-names = "qup-core", "qup-config"; 1460 status = "disabled"; 1461 }; 1462 1463 uart14: serial@a98000 { 1464 compatible = "qcom,geni-uart"; 1465 reg = <0 0x00a98000 0 0x4000>; 1466 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1467 clock-names = "se"; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1470 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1471 power-domains = <&rpmhpd SC7280_CX>; 1472 operating-points-v2 = <&qup_opp_table>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1475 interconnect-names = "qup-core", "qup-config"; 1476 status = "disabled"; 1477 }; 1478 1479 i2c15: i2c@a9c000 { 1480 compatible = "qcom,geni-i2c"; 1481 reg = <0 0x00a9c000 0 0x4000>; 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1483 clock-names = "se"; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&qup_i2c15_data_clk>; 1486 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1491 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", 1493 "qup-memory"; 1494 status = "disabled"; 1495 }; 1496 1497 spi15: spi@a9c000 { 1498 compatible = "qcom,geni-spi"; 1499 reg = <0 0x00a9c000 0 0x4000>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1501 clock-names = "se"; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1504 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 power-domains = <&rpmhpd SC7280_CX>; 1508 operating-points-v2 = <&qup_opp_table>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1510 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1511 interconnect-names = "qup-core", "qup-config"; 1512 status = "disabled"; 1513 }; 1514 1515 uart15: serial@a9c000 { 1516 compatible = "qcom,geni-uart"; 1517 reg = <0 0x00a9c000 0 0x4000>; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1519 clock-names = "se"; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1522 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1523 power-domains = <&rpmhpd SC7280_CX>; 1524 operating-points-v2 = <&qup_opp_table>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1527 interconnect-names = "qup-core", "qup-config"; 1528 status = "disabled"; 1529 }; 1530 }; 1531 1532 cnoc2: interconnect@1500000 { 1533 reg = <0 0x01500000 0 0x1000>; 1534 compatible = "qcom,sc7280-cnoc2"; 1535 #interconnect-cells = <2>; 1536 qcom,bcm-voters = <&apps_bcm_voter>; 1537 }; 1538 1539 cnoc3: interconnect@1502000 { 1540 reg = <0 0x01502000 0 0x1000>; 1541 compatible = "qcom,sc7280-cnoc3"; 1542 #interconnect-cells = <2>; 1543 qcom,bcm-voters = <&apps_bcm_voter>; 1544 }; 1545 1546 mc_virt: interconnect@1580000 { 1547 reg = <0 0x01580000 0 0x4>; 1548 compatible = "qcom,sc7280-mc-virt"; 1549 #interconnect-cells = <2>; 1550 qcom,bcm-voters = <&apps_bcm_voter>; 1551 }; 1552 1553 system_noc: interconnect@1680000 { 1554 reg = <0 0x01680000 0 0x15480>; 1555 compatible = "qcom,sc7280-system-noc"; 1556 #interconnect-cells = <2>; 1557 qcom,bcm-voters = <&apps_bcm_voter>; 1558 }; 1559 1560 aggre1_noc: interconnect@16e0000 { 1561 compatible = "qcom,sc7280-aggre1-noc"; 1562 reg = <0 0x016e0000 0 0x1c080>; 1563 #interconnect-cells = <2>; 1564 qcom,bcm-voters = <&apps_bcm_voter>; 1565 }; 1566 1567 aggre2_noc: interconnect@1700000 { 1568 reg = <0 0x01700000 0 0x2b080>; 1569 compatible = "qcom,sc7280-aggre2-noc"; 1570 #interconnect-cells = <2>; 1571 qcom,bcm-voters = <&apps_bcm_voter>; 1572 }; 1573 1574 mmss_noc: interconnect@1740000 { 1575 reg = <0 0x01740000 0 0x1e080>; 1576 compatible = "qcom,sc7280-mmss-noc"; 1577 #interconnect-cells = <2>; 1578 qcom,bcm-voters = <&apps_bcm_voter>; 1579 }; 1580 1581 pcie1: pci@1c08000 { 1582 compatible = "qcom,pcie-sc7280"; 1583 reg = <0 0x01c08000 0 0x3000>, 1584 <0 0x40000000 0 0xf1d>, 1585 <0 0x40000f20 0 0xa8>, 1586 <0 0x40001000 0 0x1000>, 1587 <0 0x40100000 0 0x100000>; 1588 1589 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1590 device_type = "pci"; 1591 linux,pci-domain = <1>; 1592 bus-range = <0x00 0xff>; 1593 num-lanes = <2>; 1594 1595 #address-cells = <3>; 1596 #size-cells = <2>; 1597 1598 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1599 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1600 1601 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1602 interrupt-names = "msi"; 1603 #interrupt-cells = <1>; 1604 interrupt-map-mask = <0 0 0 0x7>; 1605 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1606 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1607 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1608 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1609 1610 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1611 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1612 <&pcie1_lane 0>, 1613 <&rpmhcc RPMH_CXO_CLK>, 1614 <&gcc GCC_PCIE_1_AUX_CLK>, 1615 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1616 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1617 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1618 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1619 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1620 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1621 1622 clock-names = "pipe", 1623 "pipe_mux", 1624 "phy_pipe", 1625 "ref", 1626 "aux", 1627 "cfg", 1628 "bus_master", 1629 "bus_slave", 1630 "slave_q2a", 1631 "tbu", 1632 "ddrss_sf_tbu"; 1633 1634 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1635 assigned-clock-rates = <19200000>; 1636 1637 resets = <&gcc GCC_PCIE_1_BCR>; 1638 reset-names = "pci"; 1639 1640 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1641 1642 phys = <&pcie1_lane>; 1643 phy-names = "pciephy"; 1644 1645 pinctrl-names = "default"; 1646 pinctrl-0 = <&pcie1_clkreq_n>; 1647 1648 iommus = <&apps_smmu 0x1c80 0x1>; 1649 1650 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1651 <0x100 &apps_smmu 0x1c81 0x1>; 1652 1653 status = "disabled"; 1654 }; 1655 1656 pcie1_phy: phy@1c0e000 { 1657 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1658 reg = <0 0x01c0e000 0 0x1c0>; 1659 #address-cells = <2>; 1660 #size-cells = <2>; 1661 ranges; 1662 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1663 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1664 <&gcc GCC_PCIE_CLKREF_EN>, 1665 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1666 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1667 1668 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1669 reset-names = "phy"; 1670 1671 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1672 assigned-clock-rates = <100000000>; 1673 1674 status = "disabled"; 1675 1676 pcie1_lane: lanes@1c0e200 { 1677 reg = <0 0x01c0e200 0 0x170>, 1678 <0 0x01c0e400 0 0x200>, 1679 <0 0x01c0ea00 0 0x1f0>, 1680 <0 0x01c0e600 0 0x170>, 1681 <0 0x01c0e800 0 0x200>, 1682 <0 0x01c0ee00 0 0xf4>; 1683 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1684 clock-names = "pipe0"; 1685 1686 #phy-cells = <0>; 1687 #clock-cells = <1>; 1688 clock-output-names = "pcie_1_pipe_clk"; 1689 }; 1690 }; 1691 1692 ipa: ipa@1e40000 { 1693 compatible = "qcom,sc7280-ipa"; 1694 1695 iommus = <&apps_smmu 0x480 0x0>, 1696 <&apps_smmu 0x482 0x0>; 1697 reg = <0 0x1e40000 0 0x8000>, 1698 <0 0x1e50000 0 0x4ad0>, 1699 <0 0x1e04000 0 0x23000>; 1700 reg-names = "ipa-reg", 1701 "ipa-shared", 1702 "gsi"; 1703 1704 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1705 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1706 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1707 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1708 interrupt-names = "ipa", 1709 "gsi", 1710 "ipa-clock-query", 1711 "ipa-setup-ready"; 1712 1713 clocks = <&rpmhcc RPMH_IPA_CLK>; 1714 clock-names = "core"; 1715 1716 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1717 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1718 interconnect-names = "memory", 1719 "config"; 1720 1721 qcom,qmp = <&aoss_qmp>; 1722 1723 qcom,smem-states = <&ipa_smp2p_out 0>, 1724 <&ipa_smp2p_out 1>; 1725 qcom,smem-state-names = "ipa-clock-enabled-valid", 1726 "ipa-clock-enabled"; 1727 1728 status = "disabled"; 1729 }; 1730 1731 tcsr_mutex: hwlock@1f40000 { 1732 compatible = "qcom,tcsr-mutex", "syscon"; 1733 reg = <0 0x01f40000 0 0x40000>; 1734 #hwlock-cells = <1>; 1735 }; 1736 1737 tcsr: syscon@1fc0000 { 1738 compatible = "qcom,sc7280-tcsr", "syscon"; 1739 reg = <0 0x01fc0000 0 0x30000>; 1740 }; 1741 1742 lpasscc: lpasscc@3000000 { 1743 compatible = "qcom,sc7280-lpasscc"; 1744 reg = <0 0x03000000 0 0x40>, 1745 <0 0x03c04000 0 0x4>, 1746 <0 0x03389000 0 0x24>; 1747 reg-names = "qdsp6ss", "top_cc", "cc"; 1748 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1749 clock-names = "iface"; 1750 #clock-cells = <1>; 1751 }; 1752 1753 lpass_ag_noc: interconnect@3c40000 { 1754 reg = <0 0x03c40000 0 0xf080>; 1755 compatible = "qcom,sc7280-lpass-ag-noc"; 1756 #interconnect-cells = <2>; 1757 qcom,bcm-voters = <&apps_bcm_voter>; 1758 }; 1759 1760 gpu: gpu@3d00000 { 1761 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1762 reg = <0 0x03d00000 0 0x40000>, 1763 <0 0x03d9e000 0 0x1000>, 1764 <0 0x03d61000 0 0x800>; 1765 reg-names = "kgsl_3d0_reg_memory", 1766 "cx_mem", 1767 "cx_dbgc"; 1768 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1769 iommus = <&adreno_smmu 0 0x401>; 1770 operating-points-v2 = <&gpu_opp_table>; 1771 qcom,gmu = <&gmu>; 1772 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1773 interconnect-names = "gfx-mem"; 1774 #cooling-cells = <2>; 1775 1776 gpu_opp_table: opp-table { 1777 compatible = "operating-points-v2"; 1778 1779 opp-315000000 { 1780 opp-hz = /bits/ 64 <315000000>; 1781 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1782 opp-peak-kBps = <1804000>; 1783 }; 1784 1785 opp-450000000 { 1786 opp-hz = /bits/ 64 <450000000>; 1787 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1788 opp-peak-kBps = <4068000>; 1789 }; 1790 1791 opp-550000000 { 1792 opp-hz = /bits/ 64 <550000000>; 1793 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1794 opp-peak-kBps = <6832000>; 1795 }; 1796 }; 1797 }; 1798 1799 gmu: gmu@3d6a000 { 1800 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1801 reg = <0 0x03d6a000 0 0x34000>, 1802 <0 0x3de0000 0 0x10000>, 1803 <0 0x0b290000 0 0x10000>; 1804 reg-names = "gmu", "rscc", "gmu_pdc"; 1805 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1807 interrupt-names = "hfi", "gmu"; 1808 clocks = <&gpucc 5>, 1809 <&gpucc 8>, 1810 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1811 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1812 <&gpucc 2>, 1813 <&gpucc 15>, 1814 <&gpucc 11>; 1815 clock-names = "gmu", 1816 "cxo", 1817 "axi", 1818 "memnoc", 1819 "ahb", 1820 "hub", 1821 "smmu_vote"; 1822 power-domains = <&gpucc 0>, 1823 <&gpucc 1>; 1824 power-domain-names = "cx", 1825 "gx"; 1826 iommus = <&adreno_smmu 5 0x400>; 1827 operating-points-v2 = <&gmu_opp_table>; 1828 1829 gmu_opp_table: opp-table { 1830 compatible = "operating-points-v2"; 1831 1832 opp-200000000 { 1833 opp-hz = /bits/ 64 <200000000>; 1834 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1835 }; 1836 }; 1837 }; 1838 1839 gpucc: clock-controller@3d90000 { 1840 compatible = "qcom,sc7280-gpucc"; 1841 reg = <0 0x03d90000 0 0x9000>; 1842 clocks = <&rpmhcc RPMH_CXO_CLK>, 1843 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1844 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1845 clock-names = "bi_tcxo", 1846 "gcc_gpu_gpll0_clk_src", 1847 "gcc_gpu_gpll0_div_clk_src"; 1848 #clock-cells = <1>; 1849 #reset-cells = <1>; 1850 #power-domain-cells = <1>; 1851 }; 1852 1853 adreno_smmu: iommu@3da0000 { 1854 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1855 reg = <0 0x03da0000 0 0x20000>; 1856 #iommu-cells = <2>; 1857 #global-interrupts = <2>; 1858 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1870 1871 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1872 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1873 <&gpucc 2>, 1874 <&gpucc 11>, 1875 <&gpucc 5>, 1876 <&gpucc 15>, 1877 <&gpucc 13>; 1878 clock-names = "gcc_gpu_memnoc_gfx_clk", 1879 "gcc_gpu_snoc_dvm_gfx_clk", 1880 "gpu_cc_ahb_clk", 1881 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1882 "gpu_cc_cx_gmu_clk", 1883 "gpu_cc_hub_cx_int_clk", 1884 "gpu_cc_hub_aon_clk"; 1885 1886 power-domains = <&gpucc 0>; 1887 }; 1888 1889 remoteproc_mpss: remoteproc@4080000 { 1890 compatible = "qcom,sc7280-mpss-pas"; 1891 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1892 reg-names = "qdsp6", "rmb"; 1893 1894 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1895 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1896 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1897 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1898 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1899 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1900 interrupt-names = "wdog", "fatal", "ready", "handover", 1901 "stop-ack", "shutdown-ack"; 1902 1903 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1904 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1905 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1906 <&rpmhcc RPMH_PKA_CLK>, 1907 <&rpmhcc RPMH_CXO_CLK>; 1908 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1909 1910 power-domains = <&rpmhpd SC7280_CX>, 1911 <&rpmhpd SC7280_MSS>; 1912 power-domain-names = "cx", "mss"; 1913 1914 memory-region = <&mpss_mem>; 1915 1916 qcom,qmp = <&aoss_qmp>; 1917 1918 qcom,smem-states = <&modem_smp2p_out 0>; 1919 qcom,smem-state-names = "stop"; 1920 1921 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1922 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1923 reset-names = "mss_restart", "pdc_reset"; 1924 1925 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1926 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1927 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1928 1929 status = "disabled"; 1930 1931 glink-edge { 1932 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1933 IPCC_MPROC_SIGNAL_GLINK_QMP 1934 IRQ_TYPE_EDGE_RISING>; 1935 mboxes = <&ipcc IPCC_CLIENT_MPSS 1936 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1937 label = "modem"; 1938 qcom,remote-pid = <1>; 1939 }; 1940 }; 1941 1942 stm@6002000 { 1943 compatible = "arm,coresight-stm", "arm,primecell"; 1944 reg = <0 0x06002000 0 0x1000>, 1945 <0 0x16280000 0 0x180000>; 1946 reg-names = "stm-base", "stm-stimulus-base"; 1947 1948 clocks = <&aoss_qmp>; 1949 clock-names = "apb_pclk"; 1950 1951 out-ports { 1952 port { 1953 stm_out: endpoint { 1954 remote-endpoint = <&funnel0_in7>; 1955 }; 1956 }; 1957 }; 1958 }; 1959 1960 funnel@6041000 { 1961 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1962 reg = <0 0x06041000 0 0x1000>; 1963 1964 clocks = <&aoss_qmp>; 1965 clock-names = "apb_pclk"; 1966 1967 out-ports { 1968 port { 1969 funnel0_out: endpoint { 1970 remote-endpoint = <&merge_funnel_in0>; 1971 }; 1972 }; 1973 }; 1974 1975 in-ports { 1976 #address-cells = <1>; 1977 #size-cells = <0>; 1978 1979 port@7 { 1980 reg = <7>; 1981 funnel0_in7: endpoint { 1982 remote-endpoint = <&stm_out>; 1983 }; 1984 }; 1985 }; 1986 }; 1987 1988 funnel@6042000 { 1989 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1990 reg = <0 0x06042000 0 0x1000>; 1991 1992 clocks = <&aoss_qmp>; 1993 clock-names = "apb_pclk"; 1994 1995 out-ports { 1996 port { 1997 funnel1_out: endpoint { 1998 remote-endpoint = <&merge_funnel_in1>; 1999 }; 2000 }; 2001 }; 2002 2003 in-ports { 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 port@4 { 2008 reg = <4>; 2009 funnel1_in4: endpoint { 2010 remote-endpoint = <&apss_merge_funnel_out>; 2011 }; 2012 }; 2013 }; 2014 }; 2015 2016 funnel@6045000 { 2017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2018 reg = <0 0x06045000 0 0x1000>; 2019 2020 clocks = <&aoss_qmp>; 2021 clock-names = "apb_pclk"; 2022 2023 out-ports { 2024 port { 2025 merge_funnel_out: endpoint { 2026 remote-endpoint = <&swao_funnel_in>; 2027 }; 2028 }; 2029 }; 2030 2031 in-ports { 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 2035 port@0 { 2036 reg = <0>; 2037 merge_funnel_in0: endpoint { 2038 remote-endpoint = <&funnel0_out>; 2039 }; 2040 }; 2041 2042 port@1 { 2043 reg = <1>; 2044 merge_funnel_in1: endpoint { 2045 remote-endpoint = <&funnel1_out>; 2046 }; 2047 }; 2048 }; 2049 }; 2050 2051 replicator@6046000 { 2052 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2053 reg = <0 0x06046000 0 0x1000>; 2054 2055 clocks = <&aoss_qmp>; 2056 clock-names = "apb_pclk"; 2057 2058 out-ports { 2059 port { 2060 replicator_out: endpoint { 2061 remote-endpoint = <&etr_in>; 2062 }; 2063 }; 2064 }; 2065 2066 in-ports { 2067 port { 2068 replicator_in: endpoint { 2069 remote-endpoint = <&swao_replicator_out>; 2070 }; 2071 }; 2072 }; 2073 }; 2074 2075 etr@6048000 { 2076 compatible = "arm,coresight-tmc", "arm,primecell"; 2077 reg = <0 0x06048000 0 0x1000>; 2078 iommus = <&apps_smmu 0x04c0 0>; 2079 2080 clocks = <&aoss_qmp>; 2081 clock-names = "apb_pclk"; 2082 arm,scatter-gather; 2083 2084 in-ports { 2085 port { 2086 etr_in: endpoint { 2087 remote-endpoint = <&replicator_out>; 2088 }; 2089 }; 2090 }; 2091 }; 2092 2093 funnel@6b04000 { 2094 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2095 reg = <0 0x06b04000 0 0x1000>; 2096 2097 clocks = <&aoss_qmp>; 2098 clock-names = "apb_pclk"; 2099 2100 out-ports { 2101 port { 2102 swao_funnel_out: endpoint { 2103 remote-endpoint = <&etf_in>; 2104 }; 2105 }; 2106 }; 2107 2108 in-ports { 2109 #address-cells = <1>; 2110 #size-cells = <0>; 2111 2112 port@7 { 2113 reg = <7>; 2114 swao_funnel_in: endpoint { 2115 remote-endpoint = <&merge_funnel_out>; 2116 }; 2117 }; 2118 }; 2119 }; 2120 2121 etf@6b05000 { 2122 compatible = "arm,coresight-tmc", "arm,primecell"; 2123 reg = <0 0x06b05000 0 0x1000>; 2124 2125 clocks = <&aoss_qmp>; 2126 clock-names = "apb_pclk"; 2127 2128 out-ports { 2129 port { 2130 etf_out: endpoint { 2131 remote-endpoint = <&swao_replicator_in>; 2132 }; 2133 }; 2134 }; 2135 2136 in-ports { 2137 port { 2138 etf_in: endpoint { 2139 remote-endpoint = <&swao_funnel_out>; 2140 }; 2141 }; 2142 }; 2143 }; 2144 2145 replicator@6b06000 { 2146 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2147 reg = <0 0x06b06000 0 0x1000>; 2148 2149 clocks = <&aoss_qmp>; 2150 clock-names = "apb_pclk"; 2151 qcom,replicator-loses-context; 2152 2153 out-ports { 2154 port { 2155 swao_replicator_out: endpoint { 2156 remote-endpoint = <&replicator_in>; 2157 }; 2158 }; 2159 }; 2160 2161 in-ports { 2162 port { 2163 swao_replicator_in: endpoint { 2164 remote-endpoint = <&etf_out>; 2165 }; 2166 }; 2167 }; 2168 }; 2169 2170 etm@7040000 { 2171 compatible = "arm,coresight-etm4x", "arm,primecell"; 2172 reg = <0 0x07040000 0 0x1000>; 2173 2174 cpu = <&CPU0>; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 arm,coresight-loses-context-with-cpu; 2179 qcom,skip-power-up; 2180 2181 out-ports { 2182 port { 2183 etm0_out: endpoint { 2184 remote-endpoint = <&apss_funnel_in0>; 2185 }; 2186 }; 2187 }; 2188 }; 2189 2190 etm@7140000 { 2191 compatible = "arm,coresight-etm4x", "arm,primecell"; 2192 reg = <0 0x07140000 0 0x1000>; 2193 2194 cpu = <&CPU1>; 2195 2196 clocks = <&aoss_qmp>; 2197 clock-names = "apb_pclk"; 2198 arm,coresight-loses-context-with-cpu; 2199 qcom,skip-power-up; 2200 2201 out-ports { 2202 port { 2203 etm1_out: endpoint { 2204 remote-endpoint = <&apss_funnel_in1>; 2205 }; 2206 }; 2207 }; 2208 }; 2209 2210 etm@7240000 { 2211 compatible = "arm,coresight-etm4x", "arm,primecell"; 2212 reg = <0 0x07240000 0 0x1000>; 2213 2214 cpu = <&CPU2>; 2215 2216 clocks = <&aoss_qmp>; 2217 clock-names = "apb_pclk"; 2218 arm,coresight-loses-context-with-cpu; 2219 qcom,skip-power-up; 2220 2221 out-ports { 2222 port { 2223 etm2_out: endpoint { 2224 remote-endpoint = <&apss_funnel_in2>; 2225 }; 2226 }; 2227 }; 2228 }; 2229 2230 etm@7340000 { 2231 compatible = "arm,coresight-etm4x", "arm,primecell"; 2232 reg = <0 0x07340000 0 0x1000>; 2233 2234 cpu = <&CPU3>; 2235 2236 clocks = <&aoss_qmp>; 2237 clock-names = "apb_pclk"; 2238 arm,coresight-loses-context-with-cpu; 2239 qcom,skip-power-up; 2240 2241 out-ports { 2242 port { 2243 etm3_out: endpoint { 2244 remote-endpoint = <&apss_funnel_in3>; 2245 }; 2246 }; 2247 }; 2248 }; 2249 2250 etm@7440000 { 2251 compatible = "arm,coresight-etm4x", "arm,primecell"; 2252 reg = <0 0x07440000 0 0x1000>; 2253 2254 cpu = <&CPU4>; 2255 2256 clocks = <&aoss_qmp>; 2257 clock-names = "apb_pclk"; 2258 arm,coresight-loses-context-with-cpu; 2259 qcom,skip-power-up; 2260 2261 out-ports { 2262 port { 2263 etm4_out: endpoint { 2264 remote-endpoint = <&apss_funnel_in4>; 2265 }; 2266 }; 2267 }; 2268 }; 2269 2270 etm@7540000 { 2271 compatible = "arm,coresight-etm4x", "arm,primecell"; 2272 reg = <0 0x07540000 0 0x1000>; 2273 2274 cpu = <&CPU5>; 2275 2276 clocks = <&aoss_qmp>; 2277 clock-names = "apb_pclk"; 2278 arm,coresight-loses-context-with-cpu; 2279 qcom,skip-power-up; 2280 2281 out-ports { 2282 port { 2283 etm5_out: endpoint { 2284 remote-endpoint = <&apss_funnel_in5>; 2285 }; 2286 }; 2287 }; 2288 }; 2289 2290 etm@7640000 { 2291 compatible = "arm,coresight-etm4x", "arm,primecell"; 2292 reg = <0 0x07640000 0 0x1000>; 2293 2294 cpu = <&CPU6>; 2295 2296 clocks = <&aoss_qmp>; 2297 clock-names = "apb_pclk"; 2298 arm,coresight-loses-context-with-cpu; 2299 qcom,skip-power-up; 2300 2301 out-ports { 2302 port { 2303 etm6_out: endpoint { 2304 remote-endpoint = <&apss_funnel_in6>; 2305 }; 2306 }; 2307 }; 2308 }; 2309 2310 etm@7740000 { 2311 compatible = "arm,coresight-etm4x", "arm,primecell"; 2312 reg = <0 0x07740000 0 0x1000>; 2313 2314 cpu = <&CPU7>; 2315 2316 clocks = <&aoss_qmp>; 2317 clock-names = "apb_pclk"; 2318 arm,coresight-loses-context-with-cpu; 2319 qcom,skip-power-up; 2320 2321 out-ports { 2322 port { 2323 etm7_out: endpoint { 2324 remote-endpoint = <&apss_funnel_in7>; 2325 }; 2326 }; 2327 }; 2328 }; 2329 2330 funnel@7800000 { /* APSS Funnel */ 2331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2332 reg = <0 0x07800000 0 0x1000>; 2333 2334 clocks = <&aoss_qmp>; 2335 clock-names = "apb_pclk"; 2336 2337 out-ports { 2338 port { 2339 apss_funnel_out: endpoint { 2340 remote-endpoint = <&apss_merge_funnel_in>; 2341 }; 2342 }; 2343 }; 2344 2345 in-ports { 2346 #address-cells = <1>; 2347 #size-cells = <0>; 2348 2349 port@0 { 2350 reg = <0>; 2351 apss_funnel_in0: endpoint { 2352 remote-endpoint = <&etm0_out>; 2353 }; 2354 }; 2355 2356 port@1 { 2357 reg = <1>; 2358 apss_funnel_in1: endpoint { 2359 remote-endpoint = <&etm1_out>; 2360 }; 2361 }; 2362 2363 port@2 { 2364 reg = <2>; 2365 apss_funnel_in2: endpoint { 2366 remote-endpoint = <&etm2_out>; 2367 }; 2368 }; 2369 2370 port@3 { 2371 reg = <3>; 2372 apss_funnel_in3: endpoint { 2373 remote-endpoint = <&etm3_out>; 2374 }; 2375 }; 2376 2377 port@4 { 2378 reg = <4>; 2379 apss_funnel_in4: endpoint { 2380 remote-endpoint = <&etm4_out>; 2381 }; 2382 }; 2383 2384 port@5 { 2385 reg = <5>; 2386 apss_funnel_in5: endpoint { 2387 remote-endpoint = <&etm5_out>; 2388 }; 2389 }; 2390 2391 port@6 { 2392 reg = <6>; 2393 apss_funnel_in6: endpoint { 2394 remote-endpoint = <&etm6_out>; 2395 }; 2396 }; 2397 2398 port@7 { 2399 reg = <7>; 2400 apss_funnel_in7: endpoint { 2401 remote-endpoint = <&etm7_out>; 2402 }; 2403 }; 2404 }; 2405 }; 2406 2407 funnel@7810000 { 2408 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2409 reg = <0 0x07810000 0 0x1000>; 2410 2411 clocks = <&aoss_qmp>; 2412 clock-names = "apb_pclk"; 2413 2414 out-ports { 2415 port { 2416 apss_merge_funnel_out: endpoint { 2417 remote-endpoint = <&funnel1_in4>; 2418 }; 2419 }; 2420 }; 2421 2422 in-ports { 2423 port { 2424 apss_merge_funnel_in: endpoint { 2425 remote-endpoint = <&apss_funnel_out>; 2426 }; 2427 }; 2428 }; 2429 }; 2430 2431 sdhc_2: sdhci@8804000 { 2432 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2433 pinctrl-names = "default", "sleep"; 2434 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2435 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2436 status = "disabled"; 2437 2438 reg = <0 0x08804000 0 0x1000>; 2439 2440 iommus = <&apps_smmu 0x100 0x0>; 2441 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2443 interrupt-names = "hc_irq", "pwr_irq"; 2444 2445 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2446 <&gcc GCC_SDCC2_AHB_CLK>, 2447 <&rpmhcc RPMH_CXO_CLK>; 2448 clock-names = "core", "iface", "xo"; 2449 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2451 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2452 power-domains = <&rpmhpd SC7280_CX>; 2453 operating-points-v2 = <&sdhc2_opp_table>; 2454 2455 bus-width = <4>; 2456 2457 qcom,dll-config = <0x0007642c>; 2458 2459 sdhc2_opp_table: opp-table { 2460 compatible = "operating-points-v2"; 2461 2462 opp-100000000 { 2463 opp-hz = /bits/ 64 <100000000>; 2464 required-opps = <&rpmhpd_opp_low_svs>; 2465 opp-peak-kBps = <1800000 400000>; 2466 opp-avg-kBps = <100000 0>; 2467 }; 2468 2469 opp-202000000 { 2470 opp-hz = /bits/ 64 <202000000>; 2471 required-opps = <&rpmhpd_opp_nom>; 2472 opp-peak-kBps = <5400000 1600000>; 2473 opp-avg-kBps = <200000 0>; 2474 }; 2475 }; 2476 2477 }; 2478 2479 usb_1_hsphy: phy@88e3000 { 2480 compatible = "qcom,sc7280-usb-hs-phy", 2481 "qcom,usb-snps-hs-7nm-phy"; 2482 reg = <0 0x088e3000 0 0x400>; 2483 status = "disabled"; 2484 #phy-cells = <0>; 2485 2486 clocks = <&rpmhcc RPMH_CXO_CLK>; 2487 clock-names = "ref"; 2488 2489 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2490 }; 2491 2492 usb_2_hsphy: phy@88e4000 { 2493 compatible = "qcom,sc7280-usb-hs-phy", 2494 "qcom,usb-snps-hs-7nm-phy"; 2495 reg = <0 0x088e4000 0 0x400>; 2496 status = "disabled"; 2497 #phy-cells = <0>; 2498 2499 clocks = <&rpmhcc RPMH_CXO_CLK>; 2500 clock-names = "ref"; 2501 2502 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2503 }; 2504 2505 usb_1_qmpphy: phy-wrapper@88e9000 { 2506 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2507 "qcom,sm8250-qmp-usb3-dp-phy"; 2508 reg = <0 0x088e9000 0 0x200>, 2509 <0 0x088e8000 0 0x40>, 2510 <0 0x088ea000 0 0x200>; 2511 status = "disabled"; 2512 #address-cells = <2>; 2513 #size-cells = <2>; 2514 ranges; 2515 2516 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2517 <&rpmhcc RPMH_CXO_CLK>, 2518 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2519 clock-names = "aux", "ref_clk_src", "com_aux"; 2520 2521 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2522 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2523 reset-names = "phy", "common"; 2524 2525 usb_1_ssphy: usb3-phy@88e9200 { 2526 reg = <0 0x088e9200 0 0x200>, 2527 <0 0x088e9400 0 0x200>, 2528 <0 0x088e9c00 0 0x400>, 2529 <0 0x088e9600 0 0x200>, 2530 <0 0x088e9800 0 0x200>, 2531 <0 0x088e9a00 0 0x100>; 2532 #clock-cells = <0>; 2533 #phy-cells = <0>; 2534 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2535 clock-names = "pipe0"; 2536 clock-output-names = "usb3_phy_pipe_clk_src"; 2537 }; 2538 2539 dp_phy: dp-phy@88ea200 { 2540 reg = <0 0x088ea200 0 0x200>, 2541 <0 0x088ea400 0 0x200>, 2542 <0 0x088eaa00 0 0x200>, 2543 <0 0x088ea600 0 0x200>, 2544 <0 0x088ea800 0 0x200>; 2545 #phy-cells = <0>; 2546 #clock-cells = <1>; 2547 }; 2548 }; 2549 2550 usb_2: usb@8cf8800 { 2551 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2552 reg = <0 0x08cf8800 0 0x400>; 2553 status = "disabled"; 2554 #address-cells = <2>; 2555 #size-cells = <2>; 2556 ranges; 2557 dma-ranges; 2558 2559 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2560 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2561 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2562 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2563 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2564 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2565 "sleep"; 2566 2567 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2568 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2569 assigned-clock-rates = <19200000>, <200000000>; 2570 2571 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2572 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2573 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2574 interrupt-names = "hs_phy_irq", 2575 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2576 2577 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2578 2579 resets = <&gcc GCC_USB30_SEC_BCR>; 2580 2581 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2582 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2583 interconnect-names = "usb-ddr", "apps-usb"; 2584 2585 usb_2_dwc3: usb@8c00000 { 2586 compatible = "snps,dwc3"; 2587 reg = <0 0x08c00000 0 0xe000>; 2588 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2589 iommus = <&apps_smmu 0xa0 0x0>; 2590 snps,dis_u2_susphy_quirk; 2591 snps,dis_enblslpm_quirk; 2592 phys = <&usb_2_hsphy>; 2593 phy-names = "usb2-phy"; 2594 maximum-speed = "high-speed"; 2595 }; 2596 }; 2597 2598 qspi: spi@88dc000 { 2599 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2600 reg = <0 0x088dc000 0 0x1000>; 2601 #address-cells = <1>; 2602 #size-cells = <0>; 2603 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2604 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2605 <&gcc GCC_QSPI_CORE_CLK>; 2606 clock-names = "iface", "core"; 2607 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2608 &cnoc2 SLAVE_QSPI_0 0>; 2609 interconnect-names = "qspi-config"; 2610 power-domains = <&rpmhpd SC7280_CX>; 2611 operating-points-v2 = <&qspi_opp_table>; 2612 status = "disabled"; 2613 }; 2614 2615 dc_noc: interconnect@90e0000 { 2616 reg = <0 0x090e0000 0 0x5080>; 2617 compatible = "qcom,sc7280-dc-noc"; 2618 #interconnect-cells = <2>; 2619 qcom,bcm-voters = <&apps_bcm_voter>; 2620 }; 2621 2622 gem_noc: interconnect@9100000 { 2623 reg = <0 0x9100000 0 0xe2200>; 2624 compatible = "qcom,sc7280-gem-noc"; 2625 #interconnect-cells = <2>; 2626 qcom,bcm-voters = <&apps_bcm_voter>; 2627 }; 2628 2629 system-cache-controller@9200000 { 2630 compatible = "qcom,sc7280-llcc"; 2631 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2632 reg-names = "llcc_base", "llcc_broadcast_base"; 2633 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2634 }; 2635 2636 nsp_noc: interconnect@a0c0000 { 2637 reg = <0 0x0a0c0000 0 0x10000>; 2638 compatible = "qcom,sc7280-nsp-noc"; 2639 #interconnect-cells = <2>; 2640 qcom,bcm-voters = <&apps_bcm_voter>; 2641 }; 2642 2643 usb_1: usb@a6f8800 { 2644 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2645 reg = <0 0x0a6f8800 0 0x400>; 2646 status = "disabled"; 2647 #address-cells = <2>; 2648 #size-cells = <2>; 2649 ranges; 2650 dma-ranges; 2651 2652 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2653 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2654 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2655 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2656 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2657 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2658 "sleep"; 2659 2660 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2661 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2662 assigned-clock-rates = <19200000>, <200000000>; 2663 2664 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2665 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2666 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2667 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2668 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2669 "dm_hs_phy_irq", "ss_phy_irq"; 2670 2671 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2672 2673 resets = <&gcc GCC_USB30_PRIM_BCR>; 2674 2675 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2676 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2677 interconnect-names = "usb-ddr", "apps-usb"; 2678 2679 usb_1_dwc3: usb@a600000 { 2680 compatible = "snps,dwc3"; 2681 reg = <0 0x0a600000 0 0xe000>; 2682 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2683 iommus = <&apps_smmu 0xe0 0x0>; 2684 snps,dis_u2_susphy_quirk; 2685 snps,dis_enblslpm_quirk; 2686 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2687 phy-names = "usb2-phy", "usb3-phy"; 2688 maximum-speed = "super-speed"; 2689 }; 2690 }; 2691 2692 venus: video-codec@aa00000 { 2693 compatible = "qcom,sc7280-venus"; 2694 reg = <0 0x0aa00000 0 0xd0600>; 2695 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2696 2697 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2698 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2699 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2700 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2701 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2702 clock-names = "core", "bus", "iface", 2703 "vcodec_core", "vcodec_bus"; 2704 2705 power-domains = <&videocc MVSC_GDSC>, 2706 <&videocc MVS0_GDSC>, 2707 <&rpmhpd SC7280_CX>; 2708 power-domain-names = "venus", "vcodec0", "cx"; 2709 operating-points-v2 = <&venus_opp_table>; 2710 2711 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2712 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2713 interconnect-names = "cpu-cfg", "video-mem"; 2714 2715 iommus = <&apps_smmu 0x2180 0x20>, 2716 <&apps_smmu 0x2184 0x20>; 2717 memory-region = <&video_mem>; 2718 2719 video-decoder { 2720 compatible = "venus-decoder"; 2721 }; 2722 2723 video-encoder { 2724 compatible = "venus-encoder"; 2725 }; 2726 2727 video-firmware { 2728 iommus = <&apps_smmu 0x21a2 0x0>; 2729 }; 2730 2731 venus_opp_table: venus-opp-table { 2732 compatible = "operating-points-v2"; 2733 2734 opp-133330000 { 2735 opp-hz = /bits/ 64 <133330000>; 2736 required-opps = <&rpmhpd_opp_low_svs>; 2737 }; 2738 2739 opp-240000000 { 2740 opp-hz = /bits/ 64 <240000000>; 2741 required-opps = <&rpmhpd_opp_svs>; 2742 }; 2743 2744 opp-335000000 { 2745 opp-hz = /bits/ 64 <335000000>; 2746 required-opps = <&rpmhpd_opp_svs_l1>; 2747 }; 2748 2749 opp-424000000 { 2750 opp-hz = /bits/ 64 <424000000>; 2751 required-opps = <&rpmhpd_opp_nom>; 2752 }; 2753 2754 opp-460000048 { 2755 opp-hz = /bits/ 64 <460000048>; 2756 required-opps = <&rpmhpd_opp_turbo>; 2757 }; 2758 }; 2759 2760 }; 2761 2762 videocc: clock-controller@aaf0000 { 2763 compatible = "qcom,sc7280-videocc"; 2764 reg = <0 0xaaf0000 0 0x10000>; 2765 clocks = <&rpmhcc RPMH_CXO_CLK>, 2766 <&rpmhcc RPMH_CXO_CLK_A>; 2767 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2768 #clock-cells = <1>; 2769 #reset-cells = <1>; 2770 #power-domain-cells = <1>; 2771 }; 2772 2773 camcc: clock-controller@ad00000 { 2774 compatible = "qcom,sc7280-camcc"; 2775 reg = <0 0x0ad00000 0 0x10000>; 2776 clocks = <&rpmhcc RPMH_CXO_CLK>, 2777 <&rpmhcc RPMH_CXO_CLK_A>, 2778 <&sleep_clk>; 2779 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 2780 #clock-cells = <1>; 2781 #reset-cells = <1>; 2782 #power-domain-cells = <1>; 2783 }; 2784 2785 dispcc: clock-controller@af00000 { 2786 compatible = "qcom,sc7280-dispcc"; 2787 reg = <0 0xaf00000 0 0x20000>; 2788 clocks = <&rpmhcc RPMH_CXO_CLK>, 2789 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2790 <&mdss_dsi_phy 0>, 2791 <&mdss_dsi_phy 1>, 2792 <&dp_phy 0>, 2793 <&dp_phy 1>, 2794 <&mdss_edp_phy 0>, 2795 <&mdss_edp_phy 1>; 2796 clock-names = "bi_tcxo", 2797 "gcc_disp_gpll0_clk", 2798 "dsi0_phy_pll_out_byteclk", 2799 "dsi0_phy_pll_out_dsiclk", 2800 "dp_phy_pll_link_clk", 2801 "dp_phy_pll_vco_div_clk", 2802 "edp_phy_pll_link_clk", 2803 "edp_phy_pll_vco_div_clk"; 2804 #clock-cells = <1>; 2805 #reset-cells = <1>; 2806 #power-domain-cells = <1>; 2807 }; 2808 2809 mdss: display-subsystem@ae00000 { 2810 compatible = "qcom,sc7280-mdss"; 2811 reg = <0 0x0ae00000 0 0x1000>; 2812 reg-names = "mdss"; 2813 2814 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 2815 2816 clocks = <&gcc GCC_DISP_AHB_CLK>, 2817 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2818 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2819 clock-names = "iface", 2820 "ahb", 2821 "core"; 2822 2823 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2824 assigned-clock-rates = <300000000>; 2825 2826 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2827 interrupt-controller; 2828 #interrupt-cells = <1>; 2829 2830 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2831 interconnect-names = "mdp0-mem"; 2832 2833 iommus = <&apps_smmu 0x900 0x402>; 2834 2835 #address-cells = <2>; 2836 #size-cells = <2>; 2837 ranges; 2838 2839 status = "disabled"; 2840 2841 mdss_mdp: display-controller@ae01000 { 2842 compatible = "qcom,sc7280-dpu"; 2843 reg = <0 0x0ae01000 0 0x8f030>, 2844 <0 0x0aeb0000 0 0x2008>; 2845 reg-names = "mdp", "vbif"; 2846 2847 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2848 <&gcc GCC_DISP_SF_AXI_CLK>, 2849 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2850 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2851 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2852 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2853 clock-names = "bus", 2854 "nrt_bus", 2855 "iface", 2856 "lut", 2857 "core", 2858 "vsync"; 2859 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2860 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2861 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2862 assigned-clock-rates = <300000000>, 2863 <19200000>, 2864 <19200000>; 2865 operating-points-v2 = <&mdp_opp_table>; 2866 power-domains = <&rpmhpd SC7280_CX>; 2867 2868 interrupt-parent = <&mdss>; 2869 interrupts = <0>; 2870 2871 status = "disabled"; 2872 2873 ports { 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 2877 port@0 { 2878 reg = <0>; 2879 dpu_intf1_out: endpoint { 2880 remote-endpoint = <&dsi0_in>; 2881 }; 2882 }; 2883 2884 port@1 { 2885 reg = <1>; 2886 dpu_intf5_out: endpoint { 2887 remote-endpoint = <&edp_in>; 2888 }; 2889 }; 2890 2891 port@2 { 2892 reg = <2>; 2893 dpu_intf0_out: endpoint { 2894 remote-endpoint = <&dp_in>; 2895 }; 2896 }; 2897 }; 2898 2899 mdp_opp_table: opp-table { 2900 compatible = "operating-points-v2"; 2901 2902 opp-200000000 { 2903 opp-hz = /bits/ 64 <200000000>; 2904 required-opps = <&rpmhpd_opp_low_svs>; 2905 }; 2906 2907 opp-300000000 { 2908 opp-hz = /bits/ 64 <300000000>; 2909 required-opps = <&rpmhpd_opp_svs>; 2910 }; 2911 2912 opp-380000000 { 2913 opp-hz = /bits/ 64 <380000000>; 2914 required-opps = <&rpmhpd_opp_svs_l1>; 2915 }; 2916 2917 opp-506666667 { 2918 opp-hz = /bits/ 64 <506666667>; 2919 required-opps = <&rpmhpd_opp_nom>; 2920 }; 2921 }; 2922 }; 2923 2924 mdss_dsi: dsi@ae94000 { 2925 compatible = "qcom,mdss-dsi-ctrl"; 2926 reg = <0 0x0ae94000 0 0x400>; 2927 reg-names = "dsi_ctrl"; 2928 2929 interrupt-parent = <&mdss>; 2930 interrupts = <4>; 2931 2932 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2933 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2934 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2935 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2936 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2937 <&gcc GCC_DISP_HF_AXI_CLK>; 2938 clock-names = "byte", 2939 "byte_intf", 2940 "pixel", 2941 "core", 2942 "iface", 2943 "bus"; 2944 2945 operating-points-v2 = <&dsi_opp_table>; 2946 power-domains = <&rpmhpd SC7280_CX>; 2947 2948 phys = <&mdss_dsi_phy>; 2949 phy-names = "dsi"; 2950 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 status = "disabled"; 2955 2956 ports { 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 port@0 { 2961 reg = <0>; 2962 dsi0_in: endpoint { 2963 remote-endpoint = <&dpu_intf1_out>; 2964 }; 2965 }; 2966 2967 port@1 { 2968 reg = <1>; 2969 dsi0_out: endpoint { 2970 }; 2971 }; 2972 }; 2973 2974 dsi_opp_table: opp-table { 2975 compatible = "operating-points-v2"; 2976 2977 opp-187500000 { 2978 opp-hz = /bits/ 64 <187500000>; 2979 required-opps = <&rpmhpd_opp_low_svs>; 2980 }; 2981 2982 opp-300000000 { 2983 opp-hz = /bits/ 64 <300000000>; 2984 required-opps = <&rpmhpd_opp_svs>; 2985 }; 2986 2987 opp-358000000 { 2988 opp-hz = /bits/ 64 <358000000>; 2989 required-opps = <&rpmhpd_opp_svs_l1>; 2990 }; 2991 }; 2992 }; 2993 2994 mdss_dsi_phy: phy@ae94400 { 2995 compatible = "qcom,sc7280-dsi-phy-7nm"; 2996 reg = <0 0x0ae94400 0 0x200>, 2997 <0 0x0ae94600 0 0x280>, 2998 <0 0x0ae94900 0 0x280>; 2999 reg-names = "dsi_phy", 3000 "dsi_phy_lane", 3001 "dsi_pll"; 3002 3003 #clock-cells = <1>; 3004 #phy-cells = <0>; 3005 3006 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3007 <&rpmhcc RPMH_CXO_CLK>; 3008 clock-names = "iface", "ref"; 3009 3010 status = "disabled"; 3011 }; 3012 3013 mdss_edp: edp@aea0000 { 3014 compatible = "qcom,sc7280-edp"; 3015 pinctrl-names = "default"; 3016 pinctrl-0 = <&edp_hot_plug_det>; 3017 3018 reg = <0 0xaea0000 0 0x200>, 3019 <0 0xaea0200 0 0x200>, 3020 <0 0xaea0400 0 0xc00>, 3021 <0 0xaea1000 0 0x400>; 3022 3023 interrupt-parent = <&mdss>; 3024 interrupts = <14>; 3025 3026 clocks = <&rpmhcc RPMH_CXO_CLK>, 3027 <&gcc GCC_EDP_CLKREF_EN>, 3028 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3029 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3030 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3031 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3032 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3033 clock-names = "core_xo", 3034 "core_ref", 3035 "core_iface", 3036 "core_aux", 3037 "ctrl_link", 3038 "ctrl_link_iface", 3039 "stream_pixel"; 3040 #clock-cells = <1>; 3041 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3042 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3043 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3044 3045 phys = <&mdss_edp_phy>; 3046 phy-names = "dp"; 3047 3048 operating-points-v2 = <&edp_opp_table>; 3049 power-domains = <&rpmhpd SC7280_CX>; 3050 3051 #address-cells = <1>; 3052 #size-cells = <0>; 3053 3054 status = "disabled"; 3055 3056 ports { 3057 #address-cells = <1>; 3058 #size-cells = <0>; 3059 3060 port@0 { 3061 reg = <0>; 3062 edp_in: endpoint { 3063 remote-endpoint = <&dpu_intf5_out>; 3064 }; 3065 }; 3066 3067 port@1 { 3068 reg = <1>; 3069 edp_out: endpoint { }; 3070 }; 3071 }; 3072 3073 edp_opp_table: opp-table { 3074 compatible = "operating-points-v2"; 3075 3076 opp-160000000 { 3077 opp-hz = /bits/ 64 <160000000>; 3078 required-opps = <&rpmhpd_opp_low_svs>; 3079 }; 3080 3081 opp-270000000 { 3082 opp-hz = /bits/ 64 <270000000>; 3083 required-opps = <&rpmhpd_opp_svs>; 3084 }; 3085 3086 opp-540000000 { 3087 opp-hz = /bits/ 64 <540000000>; 3088 required-opps = <&rpmhpd_opp_nom>; 3089 }; 3090 3091 opp-810000000 { 3092 opp-hz = /bits/ 64 <810000000>; 3093 required-opps = <&rpmhpd_opp_nom>; 3094 }; 3095 }; 3096 }; 3097 3098 mdss_edp_phy: phy@aec2a00 { 3099 compatible = "qcom,sc7280-edp-phy"; 3100 3101 reg = <0 0xaec2a00 0 0x19c>, 3102 <0 0xaec2200 0 0xa0>, 3103 <0 0xaec2600 0 0xa0>, 3104 <0 0xaec2000 0 0x1c0>; 3105 3106 clocks = <&rpmhcc RPMH_CXO_CLK>, 3107 <&gcc GCC_EDP_CLKREF_EN>; 3108 clock-names = "aux", 3109 "cfg_ahb"; 3110 3111 #clock-cells = <1>; 3112 #phy-cells = <0>; 3113 3114 status = "disabled"; 3115 }; 3116 3117 mdss_dp: displayport-controller@ae90000 { 3118 compatible = "qcom,sc7280-dp"; 3119 3120 reg = <0 0x0ae90000 0 0x1400>; 3121 3122 interrupt-parent = <&mdss>; 3123 interrupts = <12>; 3124 3125 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3126 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3127 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3128 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3129 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3130 clock-names = "core_iface", 3131 "core_aux", 3132 "ctrl_link", 3133 "ctrl_link_iface", 3134 "stream_pixel"; 3135 #clock-cells = <1>; 3136 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3137 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3138 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3139 phys = <&dp_phy>; 3140 phy-names = "dp"; 3141 3142 operating-points-v2 = <&dp_opp_table>; 3143 power-domains = <&rpmhpd SC7280_CX>; 3144 3145 #sound-dai-cells = <0>; 3146 3147 status = "disabled"; 3148 3149 ports { 3150 #address-cells = <1>; 3151 #size-cells = <0>; 3152 port@0 { 3153 reg = <0>; 3154 dp_in: endpoint { 3155 remote-endpoint = <&dpu_intf0_out>; 3156 }; 3157 }; 3158 3159 port@1 { 3160 reg = <1>; 3161 dp_out: endpoint { }; 3162 }; 3163 }; 3164 3165 dp_opp_table: opp-table { 3166 compatible = "operating-points-v2"; 3167 3168 opp-160000000 { 3169 opp-hz = /bits/ 64 <160000000>; 3170 required-opps = <&rpmhpd_opp_low_svs>; 3171 }; 3172 3173 opp-270000000 { 3174 opp-hz = /bits/ 64 <270000000>; 3175 required-opps = <&rpmhpd_opp_svs>; 3176 }; 3177 3178 opp-540000000 { 3179 opp-hz = /bits/ 64 <540000000>; 3180 required-opps = <&rpmhpd_opp_svs_l1>; 3181 }; 3182 3183 opp-810000000 { 3184 opp-hz = /bits/ 64 <810000000>; 3185 required-opps = <&rpmhpd_opp_nom>; 3186 }; 3187 }; 3188 }; 3189 }; 3190 3191 pdc: interrupt-controller@b220000 { 3192 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3193 reg = <0 0x0b220000 0 0x30000>; 3194 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3195 <55 306 4>, <59 312 3>, <62 374 2>, 3196 <64 434 2>, <66 438 3>, <69 86 1>, 3197 <70 520 54>, <124 609 31>, <155 63 1>, 3198 <156 716 12>; 3199 #interrupt-cells = <2>; 3200 interrupt-parent = <&intc>; 3201 interrupt-controller; 3202 }; 3203 3204 pdc_reset: reset-controller@b5e0000 { 3205 compatible = "qcom,sc7280-pdc-global"; 3206 reg = <0 0x0b5e0000 0 0x20000>; 3207 #reset-cells = <1>; 3208 }; 3209 3210 tsens0: thermal-sensor@c263000 { 3211 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3212 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3213 <0 0x0c222000 0 0x1ff>; /* SROT */ 3214 #qcom,sensors = <15>; 3215 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3217 interrupt-names = "uplow","critical"; 3218 #thermal-sensor-cells = <1>; 3219 }; 3220 3221 tsens1: thermal-sensor@c265000 { 3222 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3223 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3224 <0 0x0c223000 0 0x1ff>; /* SROT */ 3225 #qcom,sensors = <12>; 3226 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3228 interrupt-names = "uplow","critical"; 3229 #thermal-sensor-cells = <1>; 3230 }; 3231 3232 aoss_reset: reset-controller@c2a0000 { 3233 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3234 reg = <0 0x0c2a0000 0 0x31000>; 3235 #reset-cells = <1>; 3236 }; 3237 3238 aoss_qmp: power-controller@c300000 { 3239 compatible = "qcom,sc7280-aoss-qmp"; 3240 reg = <0 0x0c300000 0 0x400>; 3241 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3242 IPCC_MPROC_SIGNAL_GLINK_QMP 3243 IRQ_TYPE_EDGE_RISING>; 3244 mboxes = <&ipcc IPCC_CLIENT_AOP 3245 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3246 3247 #clock-cells = <0>; 3248 }; 3249 3250 sram@c3f0000 { 3251 compatible = "qcom,rpmh-stats"; 3252 reg = <0 0x0c3f0000 0 0x400>; 3253 }; 3254 3255 spmi_bus: spmi@c440000 { 3256 compatible = "qcom,spmi-pmic-arb"; 3257 reg = <0 0x0c440000 0 0x1100>, 3258 <0 0x0c600000 0 0x2000000>, 3259 <0 0x0e600000 0 0x100000>, 3260 <0 0x0e700000 0 0xa0000>, 3261 <0 0x0c40a000 0 0x26000>; 3262 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3263 interrupt-names = "periph_irq"; 3264 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3265 qcom,ee = <0>; 3266 qcom,channel = <0>; 3267 #address-cells = <1>; 3268 #size-cells = <1>; 3269 interrupt-controller; 3270 #interrupt-cells = <4>; 3271 }; 3272 3273 tlmm: pinctrl@f100000 { 3274 compatible = "qcom,sc7280-pinctrl"; 3275 reg = <0 0x0f100000 0 0x300000>; 3276 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3277 gpio-controller; 3278 #gpio-cells = <2>; 3279 interrupt-controller; 3280 #interrupt-cells = <2>; 3281 gpio-ranges = <&tlmm 0 0 175>; 3282 wakeup-parent = <&pdc>; 3283 3284 dp_hot_plug_det: dp-hot-plug-det { 3285 pins = "gpio47"; 3286 function = "dp_hot"; 3287 bias-disable; 3288 }; 3289 3290 edp_hot_plug_det: edp-hot-plug-det { 3291 pins = "gpio60"; 3292 function = "edp_hot"; 3293 }; 3294 3295 pcie1_clkreq_n: pcie1-clkreq-n { 3296 pins = "gpio79"; 3297 function = "pcie1_clkreqn"; 3298 }; 3299 3300 qspi_clk: qspi-clk { 3301 pins = "gpio14"; 3302 function = "qspi_clk"; 3303 }; 3304 3305 qspi_cs0: qspi-cs0 { 3306 pins = "gpio15"; 3307 function = "qspi_cs"; 3308 }; 3309 3310 qspi_cs1: qspi-cs1 { 3311 pins = "gpio19"; 3312 function = "qspi_cs"; 3313 }; 3314 3315 qspi_data01: qspi-data01 { 3316 pins = "gpio12", "gpio13"; 3317 function = "qspi_data"; 3318 }; 3319 3320 qspi_data12: qspi-data12 { 3321 pins = "gpio16", "gpio17"; 3322 function = "qspi_data"; 3323 }; 3324 3325 qup_i2c0_data_clk: qup-i2c0-data-clk { 3326 pins = "gpio0", "gpio1"; 3327 function = "qup00"; 3328 }; 3329 3330 qup_i2c1_data_clk: qup-i2c1-data-clk { 3331 pins = "gpio4", "gpio5"; 3332 function = "qup01"; 3333 }; 3334 3335 qup_i2c2_data_clk: qup-i2c2-data-clk { 3336 pins = "gpio8", "gpio9"; 3337 function = "qup02"; 3338 }; 3339 3340 qup_i2c3_data_clk: qup-i2c3-data-clk { 3341 pins = "gpio12", "gpio13"; 3342 function = "qup03"; 3343 }; 3344 3345 qup_i2c4_data_clk: qup-i2c4-data-clk { 3346 pins = "gpio16", "gpio17"; 3347 function = "qup04"; 3348 }; 3349 3350 qup_i2c5_data_clk: qup-i2c5-data-clk { 3351 pins = "gpio20", "gpio21"; 3352 function = "qup05"; 3353 }; 3354 3355 qup_i2c6_data_clk: qup-i2c6-data-clk { 3356 pins = "gpio24", "gpio25"; 3357 function = "qup06"; 3358 }; 3359 3360 qup_i2c7_data_clk: qup-i2c7-data-clk { 3361 pins = "gpio28", "gpio29"; 3362 function = "qup07"; 3363 }; 3364 3365 qup_i2c8_data_clk: qup-i2c8-data-clk { 3366 pins = "gpio32", "gpio33"; 3367 function = "qup10"; 3368 }; 3369 3370 qup_i2c9_data_clk: qup-i2c9-data-clk { 3371 pins = "gpio36", "gpio37"; 3372 function = "qup11"; 3373 }; 3374 3375 qup_i2c10_data_clk: qup-i2c10-data-clk { 3376 pins = "gpio40", "gpio41"; 3377 function = "qup12"; 3378 }; 3379 3380 qup_i2c11_data_clk: qup-i2c11-data-clk { 3381 pins = "gpio44", "gpio45"; 3382 function = "qup13"; 3383 }; 3384 3385 qup_i2c12_data_clk: qup-i2c12-data-clk { 3386 pins = "gpio48", "gpio49"; 3387 function = "qup14"; 3388 }; 3389 3390 qup_i2c13_data_clk: qup-i2c13-data-clk { 3391 pins = "gpio52", "gpio53"; 3392 function = "qup15"; 3393 }; 3394 3395 qup_i2c14_data_clk: qup-i2c14-data-clk { 3396 pins = "gpio56", "gpio57"; 3397 function = "qup16"; 3398 }; 3399 3400 qup_i2c15_data_clk: qup-i2c15-data-clk { 3401 pins = "gpio60", "gpio61"; 3402 function = "qup17"; 3403 }; 3404 3405 qup_spi0_data_clk: qup-spi0-data-clk { 3406 pins = "gpio0", "gpio1", "gpio2"; 3407 function = "qup00"; 3408 }; 3409 3410 qup_spi0_cs: qup-spi0-cs { 3411 pins = "gpio3"; 3412 function = "qup00"; 3413 }; 3414 3415 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3416 pins = "gpio3"; 3417 function = "gpio"; 3418 }; 3419 3420 qup_spi1_data_clk: qup-spi1-data-clk { 3421 pins = "gpio4", "gpio5", "gpio6"; 3422 function = "qup01"; 3423 }; 3424 3425 qup_spi1_cs: qup-spi1-cs { 3426 pins = "gpio7"; 3427 function = "qup01"; 3428 }; 3429 3430 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3431 pins = "gpio7"; 3432 function = "gpio"; 3433 }; 3434 3435 qup_spi2_data_clk: qup-spi2-data-clk { 3436 pins = "gpio8", "gpio9", "gpio10"; 3437 function = "qup02"; 3438 }; 3439 3440 qup_spi2_cs: qup-spi2-cs { 3441 pins = "gpio11"; 3442 function = "qup02"; 3443 }; 3444 3445 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3446 pins = "gpio11"; 3447 function = "gpio"; 3448 }; 3449 3450 qup_spi3_data_clk: qup-spi3-data-clk { 3451 pins = "gpio12", "gpio13", "gpio14"; 3452 function = "qup03"; 3453 }; 3454 3455 qup_spi3_cs: qup-spi3-cs { 3456 pins = "gpio15"; 3457 function = "qup03"; 3458 }; 3459 3460 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3461 pins = "gpio15"; 3462 function = "gpio"; 3463 }; 3464 3465 qup_spi4_data_clk: qup-spi4-data-clk { 3466 pins = "gpio16", "gpio17", "gpio18"; 3467 function = "qup04"; 3468 }; 3469 3470 qup_spi4_cs: qup-spi4-cs { 3471 pins = "gpio19"; 3472 function = "qup04"; 3473 }; 3474 3475 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3476 pins = "gpio19"; 3477 function = "gpio"; 3478 }; 3479 3480 qup_spi5_data_clk: qup-spi5-data-clk { 3481 pins = "gpio20", "gpio21", "gpio22"; 3482 function = "qup05"; 3483 }; 3484 3485 qup_spi5_cs: qup-spi5-cs { 3486 pins = "gpio23"; 3487 function = "qup05"; 3488 }; 3489 3490 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3491 pins = "gpio23"; 3492 function = "gpio"; 3493 }; 3494 3495 qup_spi6_data_clk: qup-spi6-data-clk { 3496 pins = "gpio24", "gpio25", "gpio26"; 3497 function = "qup06"; 3498 }; 3499 3500 qup_spi6_cs: qup-spi6-cs { 3501 pins = "gpio27"; 3502 function = "qup06"; 3503 }; 3504 3505 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3506 pins = "gpio27"; 3507 function = "gpio"; 3508 }; 3509 3510 qup_spi7_data_clk: qup-spi7-data-clk { 3511 pins = "gpio28", "gpio29", "gpio30"; 3512 function = "qup07"; 3513 }; 3514 3515 qup_spi7_cs: qup-spi7-cs { 3516 pins = "gpio31"; 3517 function = "qup07"; 3518 }; 3519 3520 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3521 pins = "gpio31"; 3522 function = "gpio"; 3523 }; 3524 3525 qup_spi8_data_clk: qup-spi8-data-clk { 3526 pins = "gpio32", "gpio33", "gpio34"; 3527 function = "qup10"; 3528 }; 3529 3530 qup_spi8_cs: qup-spi8-cs { 3531 pins = "gpio35"; 3532 function = "qup10"; 3533 }; 3534 3535 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3536 pins = "gpio35"; 3537 function = "gpio"; 3538 }; 3539 3540 qup_spi9_data_clk: qup-spi9-data-clk { 3541 pins = "gpio36", "gpio37", "gpio38"; 3542 function = "qup11"; 3543 }; 3544 3545 qup_spi9_cs: qup-spi9-cs { 3546 pins = "gpio39"; 3547 function = "qup11"; 3548 }; 3549 3550 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3551 pins = "gpio39"; 3552 function = "gpio"; 3553 }; 3554 3555 qup_spi10_data_clk: qup-spi10-data-clk { 3556 pins = "gpio40", "gpio41", "gpio42"; 3557 function = "qup12"; 3558 }; 3559 3560 qup_spi10_cs: qup-spi10-cs { 3561 pins = "gpio43"; 3562 function = "qup12"; 3563 }; 3564 3565 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3566 pins = "gpio43"; 3567 function = "gpio"; 3568 }; 3569 3570 qup_spi11_data_clk: qup-spi11-data-clk { 3571 pins = "gpio44", "gpio45", "gpio46"; 3572 function = "qup13"; 3573 }; 3574 3575 qup_spi11_cs: qup-spi11-cs { 3576 pins = "gpio47"; 3577 function = "qup13"; 3578 }; 3579 3580 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3581 pins = "gpio47"; 3582 function = "gpio"; 3583 }; 3584 3585 qup_spi12_data_clk: qup-spi12-data-clk { 3586 pins = "gpio48", "gpio49", "gpio50"; 3587 function = "qup14"; 3588 }; 3589 3590 qup_spi12_cs: qup-spi12-cs { 3591 pins = "gpio51"; 3592 function = "qup14"; 3593 }; 3594 3595 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3596 pins = "gpio51"; 3597 function = "gpio"; 3598 }; 3599 3600 qup_spi13_data_clk: qup-spi13-data-clk { 3601 pins = "gpio52", "gpio53", "gpio54"; 3602 function = "qup15"; 3603 }; 3604 3605 qup_spi13_cs: qup-spi13-cs { 3606 pins = "gpio55"; 3607 function = "qup15"; 3608 }; 3609 3610 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3611 pins = "gpio55"; 3612 function = "gpio"; 3613 }; 3614 3615 qup_spi14_data_clk: qup-spi14-data-clk { 3616 pins = "gpio56", "gpio57", "gpio58"; 3617 function = "qup16"; 3618 }; 3619 3620 qup_spi14_cs: qup-spi14-cs { 3621 pins = "gpio59"; 3622 function = "qup16"; 3623 }; 3624 3625 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3626 pins = "gpio59"; 3627 function = "gpio"; 3628 }; 3629 3630 qup_spi15_data_clk: qup-spi15-data-clk { 3631 pins = "gpio60", "gpio61", "gpio62"; 3632 function = "qup17"; 3633 }; 3634 3635 qup_spi15_cs: qup-spi15-cs { 3636 pins = "gpio63"; 3637 function = "qup17"; 3638 }; 3639 3640 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3641 pins = "gpio63"; 3642 function = "gpio"; 3643 }; 3644 3645 qup_uart0_cts: qup-uart0-cts { 3646 pins = "gpio0"; 3647 function = "qup00"; 3648 }; 3649 3650 qup_uart0_rts: qup-uart0-rts { 3651 pins = "gpio1"; 3652 function = "qup00"; 3653 }; 3654 3655 qup_uart0_tx: qup-uart0-tx { 3656 pins = "gpio2"; 3657 function = "qup00"; 3658 }; 3659 3660 qup_uart0_rx: qup-uart0-rx { 3661 pins = "gpio3"; 3662 function = "qup00"; 3663 }; 3664 3665 qup_uart1_cts: qup-uart1-cts { 3666 pins = "gpio4"; 3667 function = "qup01"; 3668 }; 3669 3670 qup_uart1_rts: qup-uart1-rts { 3671 pins = "gpio5"; 3672 function = "qup01"; 3673 }; 3674 3675 qup_uart1_tx: qup-uart1-tx { 3676 pins = "gpio6"; 3677 function = "qup01"; 3678 }; 3679 3680 qup_uart1_rx: qup-uart1-rx { 3681 pins = "gpio7"; 3682 function = "qup01"; 3683 }; 3684 3685 qup_uart2_cts: qup-uart2-cts { 3686 pins = "gpio8"; 3687 function = "qup02"; 3688 }; 3689 3690 qup_uart2_rts: qup-uart2-rts { 3691 pins = "gpio9"; 3692 function = "qup02"; 3693 }; 3694 3695 qup_uart2_tx: qup-uart2-tx { 3696 pins = "gpio10"; 3697 function = "qup02"; 3698 }; 3699 3700 qup_uart2_rx: qup-uart2-rx { 3701 pins = "gpio11"; 3702 function = "qup02"; 3703 }; 3704 3705 qup_uart3_cts: qup-uart3-cts { 3706 pins = "gpio12"; 3707 function = "qup03"; 3708 }; 3709 3710 qup_uart3_rts: qup-uart3-rts { 3711 pins = "gpio13"; 3712 function = "qup03"; 3713 }; 3714 3715 qup_uart3_tx: qup-uart3-tx { 3716 pins = "gpio14"; 3717 function = "qup03"; 3718 }; 3719 3720 qup_uart3_rx: qup-uart3-rx { 3721 pins = "gpio15"; 3722 function = "qup03"; 3723 }; 3724 3725 qup_uart4_cts: qup-uart4-cts { 3726 pins = "gpio16"; 3727 function = "qup04"; 3728 }; 3729 3730 qup_uart4_rts: qup-uart4-rts { 3731 pins = "gpio17"; 3732 function = "qup04"; 3733 }; 3734 3735 qup_uart4_tx: qup-uart4-tx { 3736 pins = "gpio18"; 3737 function = "qup04"; 3738 }; 3739 3740 qup_uart4_rx: qup-uart4-rx { 3741 pins = "gpio19"; 3742 function = "qup04"; 3743 }; 3744 3745 qup_uart5_cts: qup-uart5-cts { 3746 pins = "gpio20"; 3747 function = "qup05"; 3748 }; 3749 3750 qup_uart5_rts: qup-uart5-rts { 3751 pins = "gpio21"; 3752 function = "qup05"; 3753 }; 3754 3755 qup_uart5_tx: qup-uart5-tx { 3756 pins = "gpio22"; 3757 function = "qup05"; 3758 }; 3759 3760 qup_uart5_rx: qup-uart5-rx { 3761 pins = "gpio23"; 3762 function = "qup05"; 3763 }; 3764 3765 qup_uart6_cts: qup-uart6-cts { 3766 pins = "gpio24"; 3767 function = "qup06"; 3768 }; 3769 3770 qup_uart6_rts: qup-uart6-rts { 3771 pins = "gpio25"; 3772 function = "qup06"; 3773 }; 3774 3775 qup_uart6_tx: qup-uart6-tx { 3776 pins = "gpio26"; 3777 function = "qup06"; 3778 }; 3779 3780 qup_uart6_rx: qup-uart6-rx { 3781 pins = "gpio27"; 3782 function = "qup06"; 3783 }; 3784 3785 qup_uart7_cts: qup-uart7-cts { 3786 pins = "gpio28"; 3787 function = "qup07"; 3788 }; 3789 3790 qup_uart7_rts: qup-uart7-rts { 3791 pins = "gpio29"; 3792 function = "qup07"; 3793 }; 3794 3795 qup_uart7_tx: qup-uart7-tx { 3796 pins = "gpio30"; 3797 function = "qup07"; 3798 }; 3799 3800 qup_uart7_rx: qup-uart7-rx { 3801 pins = "gpio31"; 3802 function = "qup07"; 3803 }; 3804 3805 qup_uart8_cts: qup-uart8-cts { 3806 pins = "gpio32"; 3807 function = "qup10"; 3808 }; 3809 3810 qup_uart8_rts: qup-uart8-rts { 3811 pins = "gpio33"; 3812 function = "qup10"; 3813 }; 3814 3815 qup_uart8_tx: qup-uart8-tx { 3816 pins = "gpio34"; 3817 function = "qup10"; 3818 }; 3819 3820 qup_uart8_rx: qup-uart8-rx { 3821 pins = "gpio35"; 3822 function = "qup10"; 3823 }; 3824 3825 qup_uart9_cts: qup-uart9-cts { 3826 pins = "gpio36"; 3827 function = "qup11"; 3828 }; 3829 3830 qup_uart9_rts: qup-uart9-rts { 3831 pins = "gpio37"; 3832 function = "qup11"; 3833 }; 3834 3835 qup_uart9_tx: qup-uart9-tx { 3836 pins = "gpio38"; 3837 function = "qup11"; 3838 }; 3839 3840 qup_uart9_rx: qup-uart9-rx { 3841 pins = "gpio39"; 3842 function = "qup11"; 3843 }; 3844 3845 qup_uart10_cts: qup-uart10-cts { 3846 pins = "gpio40"; 3847 function = "qup12"; 3848 }; 3849 3850 qup_uart10_rts: qup-uart10-rts { 3851 pins = "gpio41"; 3852 function = "qup12"; 3853 }; 3854 3855 qup_uart10_tx: qup-uart10-tx { 3856 pins = "gpio42"; 3857 function = "qup12"; 3858 }; 3859 3860 qup_uart10_rx: qup-uart10-rx { 3861 pins = "gpio43"; 3862 function = "qup12"; 3863 }; 3864 3865 qup_uart11_cts: qup-uart11-cts { 3866 pins = "gpio44"; 3867 function = "qup13"; 3868 }; 3869 3870 qup_uart11_rts: qup-uart11-rts { 3871 pins = "gpio45"; 3872 function = "qup13"; 3873 }; 3874 3875 qup_uart11_tx: qup-uart11-tx { 3876 pins = "gpio46"; 3877 function = "qup13"; 3878 }; 3879 3880 qup_uart11_rx: qup-uart11-rx { 3881 pins = "gpio47"; 3882 function = "qup13"; 3883 }; 3884 3885 qup_uart12_cts: qup-uart12-cts { 3886 pins = "gpio48"; 3887 function = "qup14"; 3888 }; 3889 3890 qup_uart12_rts: qup-uart12-rts { 3891 pins = "gpio49"; 3892 function = "qup14"; 3893 }; 3894 3895 qup_uart12_tx: qup-uart12-tx { 3896 pins = "gpio50"; 3897 function = "qup14"; 3898 }; 3899 3900 qup_uart12_rx: qup-uart12-rx { 3901 pins = "gpio51"; 3902 function = "qup14"; 3903 }; 3904 3905 qup_uart13_cts: qup-uart13-cts { 3906 pins = "gpio52"; 3907 function = "qup15"; 3908 }; 3909 3910 qup_uart13_rts: qup-uart13-rts { 3911 pins = "gpio53"; 3912 function = "qup15"; 3913 }; 3914 3915 qup_uart13_tx: qup-uart13-tx { 3916 pins = "gpio54"; 3917 function = "qup15"; 3918 }; 3919 3920 qup_uart13_rx: qup-uart13-rx { 3921 pins = "gpio55"; 3922 function = "qup15"; 3923 }; 3924 3925 qup_uart14_cts: qup-uart14-cts { 3926 pins = "gpio56"; 3927 function = "qup16"; 3928 }; 3929 3930 qup_uart14_rts: qup-uart14-rts { 3931 pins = "gpio57"; 3932 function = "qup16"; 3933 }; 3934 3935 qup_uart14_tx: qup-uart14-tx { 3936 pins = "gpio58"; 3937 function = "qup16"; 3938 }; 3939 3940 qup_uart14_rx: qup-uart14-rx { 3941 pins = "gpio59"; 3942 function = "qup16"; 3943 }; 3944 3945 qup_uart15_cts: qup-uart15-cts { 3946 pins = "gpio60"; 3947 function = "qup17"; 3948 }; 3949 3950 qup_uart15_rts: qup-uart15-rts { 3951 pins = "gpio61"; 3952 function = "qup17"; 3953 }; 3954 3955 qup_uart15_tx: qup-uart15-tx { 3956 pins = "gpio62"; 3957 function = "qup17"; 3958 }; 3959 3960 qup_uart15_rx: qup-uart15-rx { 3961 pins = "gpio63"; 3962 function = "qup17"; 3963 }; 3964 3965 sdc1_clk: sdc1-clk { 3966 pins = "sdc1_clk"; 3967 }; 3968 3969 sdc1_cmd: sdc1-cmd { 3970 pins = "sdc1_cmd"; 3971 }; 3972 3973 sdc1_data: sdc1-data { 3974 pins = "sdc1_data"; 3975 }; 3976 3977 sdc1_rclk: sdc1-rclk { 3978 pins = "sdc1_rclk"; 3979 }; 3980 3981 sdc1_clk_sleep: sdc1-clk-sleep { 3982 pins = "sdc1_clk"; 3983 drive-strength = <2>; 3984 bias-bus-hold; 3985 }; 3986 3987 sdc1_cmd_sleep: sdc1-cmd-sleep { 3988 pins = "sdc1_cmd"; 3989 drive-strength = <2>; 3990 bias-bus-hold; 3991 }; 3992 3993 sdc1_data_sleep: sdc1-data-sleep { 3994 pins = "sdc1_data"; 3995 drive-strength = <2>; 3996 bias-bus-hold; 3997 }; 3998 3999 sdc1_rclk_sleep: sdc1-rclk-sleep { 4000 pins = "sdc1_rclk"; 4001 drive-strength = <2>; 4002 bias-bus-hold; 4003 }; 4004 4005 sdc2_clk: sdc2-clk { 4006 pins = "sdc2_clk"; 4007 }; 4008 4009 sdc2_cmd: sdc2-cmd { 4010 pins = "sdc2_cmd"; 4011 }; 4012 4013 sdc2_data: sdc2-data { 4014 pins = "sdc2_data"; 4015 }; 4016 4017 sdc2_clk_sleep: sdc2-clk-sleep { 4018 pins = "sdc2_clk"; 4019 drive-strength = <2>; 4020 bias-bus-hold; 4021 }; 4022 4023 sdc2_cmd_sleep: sdc2-cmd-sleep { 4024 pins = "sdc2_cmd"; 4025 drive-strength = <2>; 4026 bias-bus-hold; 4027 }; 4028 4029 sdc2_data_sleep: sdc2-data-sleep { 4030 pins = "sdc2_data"; 4031 drive-strength = <2>; 4032 bias-bus-hold; 4033 }; 4034 }; 4035 4036 imem@146a5000 { 4037 compatible = "qcom,sc7280-imem", "syscon"; 4038 reg = <0 0x146a5000 0 0x6000>; 4039 4040 #address-cells = <1>; 4041 #size-cells = <1>; 4042 4043 ranges = <0 0 0x146a5000 0x6000>; 4044 4045 pil-reloc@594c { 4046 compatible = "qcom,pil-reloc-info"; 4047 reg = <0x594c 0xc8>; 4048 }; 4049 }; 4050 4051 apps_smmu: iommu@15000000 { 4052 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4053 reg = <0 0x15000000 0 0x100000>; 4054 #iommu-cells = <2>; 4055 #global-interrupts = <1>; 4056 dma-coherent; 4057 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4138 }; 4139 4140 intc: interrupt-controller@17a00000 { 4141 compatible = "arm,gic-v3"; 4142 #address-cells = <2>; 4143 #size-cells = <2>; 4144 ranges; 4145 #interrupt-cells = <3>; 4146 interrupt-controller; 4147 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4148 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4150 4151 gic-its@17a40000 { 4152 compatible = "arm,gic-v3-its"; 4153 msi-controller; 4154 #msi-cells = <1>; 4155 reg = <0 0x17a40000 0 0x20000>; 4156 status = "disabled"; 4157 }; 4158 }; 4159 4160 watchdog@17c10000 { 4161 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4162 reg = <0 0x17c10000 0 0x1000>; 4163 clocks = <&sleep_clk>; 4164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4165 }; 4166 4167 timer@17c20000 { 4168 #address-cells = <2>; 4169 #size-cells = <2>; 4170 ranges; 4171 compatible = "arm,armv7-timer-mem"; 4172 reg = <0 0x17c20000 0 0x1000>; 4173 4174 frame@17c21000 { 4175 frame-number = <0>; 4176 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4178 reg = <0 0x17c21000 0 0x1000>, 4179 <0 0x17c22000 0 0x1000>; 4180 }; 4181 4182 frame@17c23000 { 4183 frame-number = <1>; 4184 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4185 reg = <0 0x17c23000 0 0x1000>; 4186 status = "disabled"; 4187 }; 4188 4189 frame@17c25000 { 4190 frame-number = <2>; 4191 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4192 reg = <0 0x17c25000 0 0x1000>; 4193 status = "disabled"; 4194 }; 4195 4196 frame@17c27000 { 4197 frame-number = <3>; 4198 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4199 reg = <0 0x17c27000 0 0x1000>; 4200 status = "disabled"; 4201 }; 4202 4203 frame@17c29000 { 4204 frame-number = <4>; 4205 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4206 reg = <0 0x17c29000 0 0x1000>; 4207 status = "disabled"; 4208 }; 4209 4210 frame@17c2b000 { 4211 frame-number = <5>; 4212 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4213 reg = <0 0x17c2b000 0 0x1000>; 4214 status = "disabled"; 4215 }; 4216 4217 frame@17c2d000 { 4218 frame-number = <6>; 4219 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4220 reg = <0 0x17c2d000 0 0x1000>; 4221 status = "disabled"; 4222 }; 4223 }; 4224 4225 apps_rsc: rsc@18200000 { 4226 compatible = "qcom,rpmh-rsc"; 4227 reg = <0 0x18200000 0 0x10000>, 4228 <0 0x18210000 0 0x10000>, 4229 <0 0x18220000 0 0x10000>; 4230 reg-names = "drv-0", "drv-1", "drv-2"; 4231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4234 qcom,tcs-offset = <0xd00>; 4235 qcom,drv-id = <2>; 4236 qcom,tcs-config = <ACTIVE_TCS 2>, 4237 <SLEEP_TCS 3>, 4238 <WAKE_TCS 3>, 4239 <CONTROL_TCS 1>; 4240 4241 apps_bcm_voter: bcm-voter { 4242 compatible = "qcom,bcm-voter"; 4243 }; 4244 4245 rpmhpd: power-controller { 4246 compatible = "qcom,sc7280-rpmhpd"; 4247 #power-domain-cells = <1>; 4248 operating-points-v2 = <&rpmhpd_opp_table>; 4249 4250 rpmhpd_opp_table: opp-table { 4251 compatible = "operating-points-v2"; 4252 4253 rpmhpd_opp_ret: opp1 { 4254 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4255 }; 4256 4257 rpmhpd_opp_low_svs: opp2 { 4258 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4259 }; 4260 4261 rpmhpd_opp_svs: opp3 { 4262 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4263 }; 4264 4265 rpmhpd_opp_svs_l1: opp4 { 4266 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4267 }; 4268 4269 rpmhpd_opp_svs_l2: opp5 { 4270 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4271 }; 4272 4273 rpmhpd_opp_nom: opp6 { 4274 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4275 }; 4276 4277 rpmhpd_opp_nom_l1: opp7 { 4278 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4279 }; 4280 4281 rpmhpd_opp_turbo: opp8 { 4282 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4283 }; 4284 4285 rpmhpd_opp_turbo_l1: opp9 { 4286 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4287 }; 4288 }; 4289 }; 4290 4291 rpmhcc: clock-controller { 4292 compatible = "qcom,sc7280-rpmh-clk"; 4293 clocks = <&xo_board>; 4294 clock-names = "xo"; 4295 #clock-cells = <1>; 4296 }; 4297 }; 4298 4299 cpufreq_hw: cpufreq@18591000 { 4300 compatible = "qcom,cpufreq-epss"; 4301 reg = <0 0x18591000 0 0x1000>, 4302 <0 0x18592000 0 0x1000>, 4303 <0 0x18593000 0 0x1000>; 4304 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4305 clock-names = "xo", "alternate"; 4306 #freq-domain-cells = <1>; 4307 }; 4308 }; 4309 4310 thermal_zones: thermal-zones { 4311 cpu0-thermal { 4312 polling-delay-passive = <250>; 4313 polling-delay = <0>; 4314 4315 thermal-sensors = <&tsens0 1>; 4316 4317 trips { 4318 cpu0_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "passive"; 4322 }; 4323 4324 cpu0_alert1: trip-point1 { 4325 temperature = <95000>; 4326 hysteresis = <2000>; 4327 type = "passive"; 4328 }; 4329 4330 cpu0_crit: cpu-crit { 4331 temperature = <110000>; 4332 hysteresis = <0>; 4333 type = "critical"; 4334 }; 4335 }; 4336 4337 cooling-maps { 4338 map0 { 4339 trip = <&cpu0_alert0>; 4340 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4341 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4342 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4343 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4344 }; 4345 map1 { 4346 trip = <&cpu0_alert1>; 4347 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4348 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4349 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4350 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4351 }; 4352 }; 4353 }; 4354 4355 cpu1-thermal { 4356 polling-delay-passive = <250>; 4357 polling-delay = <0>; 4358 4359 thermal-sensors = <&tsens0 2>; 4360 4361 trips { 4362 cpu1_alert0: trip-point0 { 4363 temperature = <90000>; 4364 hysteresis = <2000>; 4365 type = "passive"; 4366 }; 4367 4368 cpu1_alert1: trip-point1 { 4369 temperature = <95000>; 4370 hysteresis = <2000>; 4371 type = "passive"; 4372 }; 4373 4374 cpu1_crit: cpu-crit { 4375 temperature = <110000>; 4376 hysteresis = <0>; 4377 type = "critical"; 4378 }; 4379 }; 4380 4381 cooling-maps { 4382 map0 { 4383 trip = <&cpu1_alert0>; 4384 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4385 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4386 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4387 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4388 }; 4389 map1 { 4390 trip = <&cpu1_alert1>; 4391 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4392 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4393 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4394 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4395 }; 4396 }; 4397 }; 4398 4399 cpu2-thermal { 4400 polling-delay-passive = <250>; 4401 polling-delay = <0>; 4402 4403 thermal-sensors = <&tsens0 3>; 4404 4405 trips { 4406 cpu2_alert0: trip-point0 { 4407 temperature = <90000>; 4408 hysteresis = <2000>; 4409 type = "passive"; 4410 }; 4411 4412 cpu2_alert1: trip-point1 { 4413 temperature = <95000>; 4414 hysteresis = <2000>; 4415 type = "passive"; 4416 }; 4417 4418 cpu2_crit: cpu-crit { 4419 temperature = <110000>; 4420 hysteresis = <0>; 4421 type = "critical"; 4422 }; 4423 }; 4424 4425 cooling-maps { 4426 map0 { 4427 trip = <&cpu2_alert0>; 4428 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4429 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4430 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4431 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4432 }; 4433 map1 { 4434 trip = <&cpu2_alert1>; 4435 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4436 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4437 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4438 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4439 }; 4440 }; 4441 }; 4442 4443 cpu3-thermal { 4444 polling-delay-passive = <250>; 4445 polling-delay = <0>; 4446 4447 thermal-sensors = <&tsens0 4>; 4448 4449 trips { 4450 cpu3_alert0: trip-point0 { 4451 temperature = <90000>; 4452 hysteresis = <2000>; 4453 type = "passive"; 4454 }; 4455 4456 cpu3_alert1: trip-point1 { 4457 temperature = <95000>; 4458 hysteresis = <2000>; 4459 type = "passive"; 4460 }; 4461 4462 cpu3_crit: cpu-crit { 4463 temperature = <110000>; 4464 hysteresis = <0>; 4465 type = "critical"; 4466 }; 4467 }; 4468 4469 cooling-maps { 4470 map0 { 4471 trip = <&cpu3_alert0>; 4472 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4473 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4474 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4475 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4476 }; 4477 map1 { 4478 trip = <&cpu3_alert1>; 4479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4483 }; 4484 }; 4485 }; 4486 4487 cpu4-thermal { 4488 polling-delay-passive = <250>; 4489 polling-delay = <0>; 4490 4491 thermal-sensors = <&tsens0 7>; 4492 4493 trips { 4494 cpu4_alert0: trip-point0 { 4495 temperature = <90000>; 4496 hysteresis = <2000>; 4497 type = "passive"; 4498 }; 4499 4500 cpu4_alert1: trip-point1 { 4501 temperature = <95000>; 4502 hysteresis = <2000>; 4503 type = "passive"; 4504 }; 4505 4506 cpu4_crit: cpu-crit { 4507 temperature = <110000>; 4508 hysteresis = <0>; 4509 type = "critical"; 4510 }; 4511 }; 4512 4513 cooling-maps { 4514 map0 { 4515 trip = <&cpu4_alert0>; 4516 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4517 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4519 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4520 }; 4521 map1 { 4522 trip = <&cpu4_alert1>; 4523 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4524 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4525 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4526 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4527 }; 4528 }; 4529 }; 4530 4531 cpu5-thermal { 4532 polling-delay-passive = <250>; 4533 polling-delay = <0>; 4534 4535 thermal-sensors = <&tsens0 8>; 4536 4537 trips { 4538 cpu5_alert0: trip-point0 { 4539 temperature = <90000>; 4540 hysteresis = <2000>; 4541 type = "passive"; 4542 }; 4543 4544 cpu5_alert1: trip-point1 { 4545 temperature = <95000>; 4546 hysteresis = <2000>; 4547 type = "passive"; 4548 }; 4549 4550 cpu5_crit: cpu-crit { 4551 temperature = <110000>; 4552 hysteresis = <0>; 4553 type = "critical"; 4554 }; 4555 }; 4556 4557 cooling-maps { 4558 map0 { 4559 trip = <&cpu5_alert0>; 4560 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4561 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4562 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4563 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4564 }; 4565 map1 { 4566 trip = <&cpu5_alert1>; 4567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4571 }; 4572 }; 4573 }; 4574 4575 cpu6-thermal { 4576 polling-delay-passive = <250>; 4577 polling-delay = <0>; 4578 4579 thermal-sensors = <&tsens0 9>; 4580 4581 trips { 4582 cpu6_alert0: trip-point0 { 4583 temperature = <90000>; 4584 hysteresis = <2000>; 4585 type = "passive"; 4586 }; 4587 4588 cpu6_alert1: trip-point1 { 4589 temperature = <95000>; 4590 hysteresis = <2000>; 4591 type = "passive"; 4592 }; 4593 4594 cpu6_crit: cpu-crit { 4595 temperature = <110000>; 4596 hysteresis = <0>; 4597 type = "critical"; 4598 }; 4599 }; 4600 4601 cooling-maps { 4602 map0 { 4603 trip = <&cpu6_alert0>; 4604 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4605 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4606 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4607 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4608 }; 4609 map1 { 4610 trip = <&cpu6_alert1>; 4611 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4612 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4613 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4614 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4615 }; 4616 }; 4617 }; 4618 4619 cpu7-thermal { 4620 polling-delay-passive = <250>; 4621 polling-delay = <0>; 4622 4623 thermal-sensors = <&tsens0 10>; 4624 4625 trips { 4626 cpu7_alert0: trip-point0 { 4627 temperature = <90000>; 4628 hysteresis = <2000>; 4629 type = "passive"; 4630 }; 4631 4632 cpu7_alert1: trip-point1 { 4633 temperature = <95000>; 4634 hysteresis = <2000>; 4635 type = "passive"; 4636 }; 4637 4638 cpu7_crit: cpu-crit { 4639 temperature = <110000>; 4640 hysteresis = <0>; 4641 type = "critical"; 4642 }; 4643 }; 4644 4645 cooling-maps { 4646 map0 { 4647 trip = <&cpu7_alert0>; 4648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4652 }; 4653 map1 { 4654 trip = <&cpu7_alert1>; 4655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4659 }; 4660 }; 4661 }; 4662 4663 cpu8-thermal { 4664 polling-delay-passive = <250>; 4665 polling-delay = <0>; 4666 4667 thermal-sensors = <&tsens0 11>; 4668 4669 trips { 4670 cpu8_alert0: trip-point0 { 4671 temperature = <90000>; 4672 hysteresis = <2000>; 4673 type = "passive"; 4674 }; 4675 4676 cpu8_alert1: trip-point1 { 4677 temperature = <95000>; 4678 hysteresis = <2000>; 4679 type = "passive"; 4680 }; 4681 4682 cpu8_crit: cpu-crit { 4683 temperature = <110000>; 4684 hysteresis = <0>; 4685 type = "critical"; 4686 }; 4687 }; 4688 4689 cooling-maps { 4690 map0 { 4691 trip = <&cpu8_alert0>; 4692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4696 }; 4697 map1 { 4698 trip = <&cpu8_alert1>; 4699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4703 }; 4704 }; 4705 }; 4706 4707 cpu9-thermal { 4708 polling-delay-passive = <250>; 4709 polling-delay = <0>; 4710 4711 thermal-sensors = <&tsens0 12>; 4712 4713 trips { 4714 cpu9_alert0: trip-point0 { 4715 temperature = <90000>; 4716 hysteresis = <2000>; 4717 type = "passive"; 4718 }; 4719 4720 cpu9_alert1: trip-point1 { 4721 temperature = <95000>; 4722 hysteresis = <2000>; 4723 type = "passive"; 4724 }; 4725 4726 cpu9_crit: cpu-crit { 4727 temperature = <110000>; 4728 hysteresis = <0>; 4729 type = "critical"; 4730 }; 4731 }; 4732 4733 cooling-maps { 4734 map0 { 4735 trip = <&cpu9_alert0>; 4736 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4737 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4738 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4739 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4740 }; 4741 map1 { 4742 trip = <&cpu9_alert1>; 4743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4747 }; 4748 }; 4749 }; 4750 4751 cpu10-thermal { 4752 polling-delay-passive = <250>; 4753 polling-delay = <0>; 4754 4755 thermal-sensors = <&tsens0 13>; 4756 4757 trips { 4758 cpu10_alert0: trip-point0 { 4759 temperature = <90000>; 4760 hysteresis = <2000>; 4761 type = "passive"; 4762 }; 4763 4764 cpu10_alert1: trip-point1 { 4765 temperature = <95000>; 4766 hysteresis = <2000>; 4767 type = "passive"; 4768 }; 4769 4770 cpu10_crit: cpu-crit { 4771 temperature = <110000>; 4772 hysteresis = <0>; 4773 type = "critical"; 4774 }; 4775 }; 4776 4777 cooling-maps { 4778 map0 { 4779 trip = <&cpu10_alert0>; 4780 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4782 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4783 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4784 }; 4785 map1 { 4786 trip = <&cpu10_alert1>; 4787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4791 }; 4792 }; 4793 }; 4794 4795 cpu11-thermal { 4796 polling-delay-passive = <250>; 4797 polling-delay = <0>; 4798 4799 thermal-sensors = <&tsens0 14>; 4800 4801 trips { 4802 cpu11_alert0: trip-point0 { 4803 temperature = <90000>; 4804 hysteresis = <2000>; 4805 type = "passive"; 4806 }; 4807 4808 cpu11_alert1: trip-point1 { 4809 temperature = <95000>; 4810 hysteresis = <2000>; 4811 type = "passive"; 4812 }; 4813 4814 cpu11_crit: cpu-crit { 4815 temperature = <110000>; 4816 hysteresis = <0>; 4817 type = "critical"; 4818 }; 4819 }; 4820 4821 cooling-maps { 4822 map0 { 4823 trip = <&cpu11_alert0>; 4824 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4826 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4827 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4828 }; 4829 map1 { 4830 trip = <&cpu11_alert1>; 4831 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4832 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4833 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4834 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4835 }; 4836 }; 4837 }; 4838 4839 aoss0-thermal { 4840 polling-delay-passive = <0>; 4841 polling-delay = <0>; 4842 4843 thermal-sensors = <&tsens0 0>; 4844 4845 trips { 4846 aoss0_alert0: trip-point0 { 4847 temperature = <90000>; 4848 hysteresis = <2000>; 4849 type = "hot"; 4850 }; 4851 4852 aoss0_crit: aoss0-crit { 4853 temperature = <110000>; 4854 hysteresis = <0>; 4855 type = "critical"; 4856 }; 4857 }; 4858 }; 4859 4860 aoss1-thermal { 4861 polling-delay-passive = <0>; 4862 polling-delay = <0>; 4863 4864 thermal-sensors = <&tsens1 0>; 4865 4866 trips { 4867 aoss1_alert0: trip-point0 { 4868 temperature = <90000>; 4869 hysteresis = <2000>; 4870 type = "hot"; 4871 }; 4872 4873 aoss1_crit: aoss1-crit { 4874 temperature = <110000>; 4875 hysteresis = <0>; 4876 type = "critical"; 4877 }; 4878 }; 4879 }; 4880 4881 cpuss0-thermal { 4882 polling-delay-passive = <0>; 4883 polling-delay = <0>; 4884 4885 thermal-sensors = <&tsens0 5>; 4886 4887 trips { 4888 cpuss0_alert0: trip-point0 { 4889 temperature = <90000>; 4890 hysteresis = <2000>; 4891 type = "hot"; 4892 }; 4893 cpuss0_crit: cluster0-crit { 4894 temperature = <110000>; 4895 hysteresis = <0>; 4896 type = "critical"; 4897 }; 4898 }; 4899 }; 4900 4901 cpuss1-thermal { 4902 polling-delay-passive = <0>; 4903 polling-delay = <0>; 4904 4905 thermal-sensors = <&tsens0 6>; 4906 4907 trips { 4908 cpuss1_alert0: trip-point0 { 4909 temperature = <90000>; 4910 hysteresis = <2000>; 4911 type = "hot"; 4912 }; 4913 cpuss1_crit: cluster0-crit { 4914 temperature = <110000>; 4915 hysteresis = <0>; 4916 type = "critical"; 4917 }; 4918 }; 4919 }; 4920 4921 gpuss0-thermal { 4922 polling-delay-passive = <100>; 4923 polling-delay = <0>; 4924 4925 thermal-sensors = <&tsens1 1>; 4926 4927 trips { 4928 gpuss0_alert0: trip-point0 { 4929 temperature = <95000>; 4930 hysteresis = <2000>; 4931 type = "passive"; 4932 }; 4933 4934 gpuss0_crit: gpuss0-crit { 4935 temperature = <110000>; 4936 hysteresis = <0>; 4937 type = "critical"; 4938 }; 4939 }; 4940 4941 cooling-maps { 4942 map0 { 4943 trip = <&gpuss0_alert0>; 4944 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4945 }; 4946 }; 4947 }; 4948 4949 gpuss1-thermal { 4950 polling-delay-passive = <100>; 4951 polling-delay = <0>; 4952 4953 thermal-sensors = <&tsens1 2>; 4954 4955 trips { 4956 gpuss1_alert0: trip-point0 { 4957 temperature = <95000>; 4958 hysteresis = <2000>; 4959 type = "passive"; 4960 }; 4961 4962 gpuss1_crit: gpuss1-crit { 4963 temperature = <110000>; 4964 hysteresis = <0>; 4965 type = "critical"; 4966 }; 4967 }; 4968 4969 cooling-maps { 4970 map0 { 4971 trip = <&gpuss1_alert0>; 4972 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4973 }; 4974 }; 4975 }; 4976 4977 nspss0-thermal { 4978 polling-delay-passive = <0>; 4979 polling-delay = <0>; 4980 4981 thermal-sensors = <&tsens1 3>; 4982 4983 trips { 4984 nspss0_alert0: trip-point0 { 4985 temperature = <90000>; 4986 hysteresis = <2000>; 4987 type = "hot"; 4988 }; 4989 4990 nspss0_crit: nspss0-crit { 4991 temperature = <110000>; 4992 hysteresis = <0>; 4993 type = "critical"; 4994 }; 4995 }; 4996 }; 4997 4998 nspss1-thermal { 4999 polling-delay-passive = <0>; 5000 polling-delay = <0>; 5001 5002 thermal-sensors = <&tsens1 4>; 5003 5004 trips { 5005 nspss1_alert0: trip-point0 { 5006 temperature = <90000>; 5007 hysteresis = <2000>; 5008 type = "hot"; 5009 }; 5010 5011 nspss1_crit: nspss1-crit { 5012 temperature = <110000>; 5013 hysteresis = <0>; 5014 type = "critical"; 5015 }; 5016 }; 5017 }; 5018 5019 video-thermal { 5020 polling-delay-passive = <0>; 5021 polling-delay = <0>; 5022 5023 thermal-sensors = <&tsens1 5>; 5024 5025 trips { 5026 video_alert0: trip-point0 { 5027 temperature = <90000>; 5028 hysteresis = <2000>; 5029 type = "hot"; 5030 }; 5031 5032 video_crit: video-crit { 5033 temperature = <110000>; 5034 hysteresis = <0>; 5035 type = "critical"; 5036 }; 5037 }; 5038 }; 5039 5040 ddr-thermal { 5041 polling-delay-passive = <0>; 5042 polling-delay = <0>; 5043 5044 thermal-sensors = <&tsens1 6>; 5045 5046 trips { 5047 ddr_alert0: trip-point0 { 5048 temperature = <90000>; 5049 hysteresis = <2000>; 5050 type = "hot"; 5051 }; 5052 5053 ddr_crit: ddr-crit { 5054 temperature = <110000>; 5055 hysteresis = <0>; 5056 type = "critical"; 5057 }; 5058 }; 5059 }; 5060 5061 mdmss0-thermal { 5062 polling-delay-passive = <0>; 5063 polling-delay = <0>; 5064 5065 thermal-sensors = <&tsens1 7>; 5066 5067 trips { 5068 mdmss0_alert0: trip-point0 { 5069 temperature = <90000>; 5070 hysteresis = <2000>; 5071 type = "hot"; 5072 }; 5073 5074 mdmss0_crit: mdmss0-crit { 5075 temperature = <110000>; 5076 hysteresis = <0>; 5077 type = "critical"; 5078 }; 5079 }; 5080 }; 5081 5082 mdmss1-thermal { 5083 polling-delay-passive = <0>; 5084 polling-delay = <0>; 5085 5086 thermal-sensors = <&tsens1 8>; 5087 5088 trips { 5089 mdmss1_alert0: trip-point0 { 5090 temperature = <90000>; 5091 hysteresis = <2000>; 5092 type = "hot"; 5093 }; 5094 5095 mdmss1_crit: mdmss1-crit { 5096 temperature = <110000>; 5097 hysteresis = <0>; 5098 type = "critical"; 5099 }; 5100 }; 5101 }; 5102 5103 mdmss2-thermal { 5104 polling-delay-passive = <0>; 5105 polling-delay = <0>; 5106 5107 thermal-sensors = <&tsens1 9>; 5108 5109 trips { 5110 mdmss2_alert0: trip-point0 { 5111 temperature = <90000>; 5112 hysteresis = <2000>; 5113 type = "hot"; 5114 }; 5115 5116 mdmss2_crit: mdmss2-crit { 5117 temperature = <110000>; 5118 hysteresis = <0>; 5119 type = "critical"; 5120 }; 5121 }; 5122 }; 5123 5124 mdmss3-thermal { 5125 polling-delay-passive = <0>; 5126 polling-delay = <0>; 5127 5128 thermal-sensors = <&tsens1 10>; 5129 5130 trips { 5131 mdmss3_alert0: trip-point0 { 5132 temperature = <90000>; 5133 hysteresis = <2000>; 5134 type = "hot"; 5135 }; 5136 5137 mdmss3_crit: mdmss3-crit { 5138 temperature = <110000>; 5139 hysteresis = <0>; 5140 type = "critical"; 5141 }; 5142 }; 5143 }; 5144 5145 camera0-thermal { 5146 polling-delay-passive = <0>; 5147 polling-delay = <0>; 5148 5149 thermal-sensors = <&tsens1 11>; 5150 5151 trips { 5152 camera0_alert0: trip-point0 { 5153 temperature = <90000>; 5154 hysteresis = <2000>; 5155 type = "hot"; 5156 }; 5157 5158 camera0_crit: camera0-crit { 5159 temperature = <110000>; 5160 hysteresis = <0>; 5161 type = "critical"; 5162 }; 5163 }; 5164 }; 5165 }; 5166 5167 timer { 5168 compatible = "arm,armv8-timer"; 5169 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5170 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5171 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5172 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5173 }; 5174}; 5175