1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sc7280.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 i2c12 = &i2c12; 45 i2c13 = &i2c13; 46 i2c14 = &i2c14; 47 i2c15 = &i2c15; 48 mmc1 = &sdhc_1; 49 mmc2 = &sdhc_2; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 clocks { 69 xo_board: xo-board { 70 compatible = "fixed-clock"; 71 clock-frequency = <76800000>; 72 #clock-cells = <0>; 73 }; 74 75 sleep_clk: sleep-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 reserved-memory { 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges; 86 87 hyp_mem: memory@80000000 { 88 reg = <0x0 0x80000000 0x0 0x600000>; 89 no-map; 90 }; 91 92 xbl_mem: memory@80600000 { 93 reg = <0x0 0x80600000 0x0 0x200000>; 94 no-map; 95 }; 96 97 aop_mem: memory@80800000 { 98 reg = <0x0 0x80800000 0x0 0x60000>; 99 no-map; 100 }; 101 102 aop_cmd_db_mem: memory@80860000 { 103 reg = <0x0 0x80860000 0x0 0x20000>; 104 compatible = "qcom,cmd-db"; 105 no-map; 106 }; 107 108 reserved_xbl_uefi_log: memory@80880000 { 109 reg = <0x0 0x80884000 0x0 0x10000>; 110 no-map; 111 }; 112 113 sec_apps_mem: memory@808ff000 { 114 reg = <0x0 0x808ff000 0x0 0x1000>; 115 no-map; 116 }; 117 118 smem_mem: memory@80900000 { 119 reg = <0x0 0x80900000 0x0 0x200000>; 120 no-map; 121 }; 122 123 cpucp_mem: memory@80b00000 { 124 no-map; 125 reg = <0x0 0x80b00000 0x0 0x100000>; 126 }; 127 128 wlan_fw_mem: memory@80c00000 { 129 reg = <0x0 0x80c00000 0x0 0xc00000>; 130 no-map; 131 }; 132 133 video_mem: memory@8b200000 { 134 reg = <0x0 0x8b200000 0x0 0x500000>; 135 no-map; 136 }; 137 138 ipa_fw_mem: memory@8b700000 { 139 reg = <0 0x8b700000 0 0x10000>; 140 no-map; 141 }; 142 143 rmtfs_mem: memory@9c900000 { 144 compatible = "qcom,rmtfs-mem"; 145 reg = <0x0 0x9c900000 0x0 0x280000>; 146 no-map; 147 148 qcom,client-id = <1>; 149 qcom,vmid = <15>; 150 }; 151 }; 152 153 cpus { 154 #address-cells = <2>; 155 #size-cells = <0>; 156 157 CPU0: cpu@0 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x0>; 161 enable-method = "psci"; 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 163 &LITTLE_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_0>; 166 qcom,freq-domain = <&cpufreq_hw 0>; 167 #cooling-cells = <2>; 168 L2_0: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 L3_0: l3-cache { 172 compatible = "cache"; 173 }; 174 }; 175 }; 176 177 CPU1: cpu@100 { 178 device_type = "cpu"; 179 compatible = "arm,kryo"; 180 reg = <0x0 0x100>; 181 enable-method = "psci"; 182 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 183 &LITTLE_CPU_SLEEP_1 184 &CLUSTER_SLEEP_0>; 185 next-level-cache = <&L2_100>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 #cooling-cells = <2>; 188 L2_100: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU2: cpu@200 { 195 device_type = "cpu"; 196 compatible = "arm,kryo"; 197 reg = <0x0 0x200>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_200>; 203 qcom,freq-domain = <&cpufreq_hw 0>; 204 #cooling-cells = <2>; 205 L2_200: l2-cache { 206 compatible = "cache"; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU3: cpu@300 { 212 device_type = "cpu"; 213 compatible = "arm,kryo"; 214 reg = <0x0 0x300>; 215 enable-method = "psci"; 216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 217 &LITTLE_CPU_SLEEP_1 218 &CLUSTER_SLEEP_0>; 219 next-level-cache = <&L2_300>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_300: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU4: cpu@400 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x400>; 232 enable-method = "psci"; 233 cpu-idle-states = <&BIG_CPU_SLEEP_0 234 &BIG_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_400>; 237 qcom,freq-domain = <&cpufreq_hw 1>; 238 #cooling-cells = <2>; 239 L2_400: l2-cache { 240 compatible = "cache"; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 CPU5: cpu@500 { 246 device_type = "cpu"; 247 compatible = "arm,kryo"; 248 reg = <0x0 0x500>; 249 enable-method = "psci"; 250 cpu-idle-states = <&BIG_CPU_SLEEP_0 251 &BIG_CPU_SLEEP_1 252 &CLUSTER_SLEEP_0>; 253 next-level-cache = <&L2_500>; 254 qcom,freq-domain = <&cpufreq_hw 1>; 255 #cooling-cells = <2>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "arm,kryo"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 next-level-cache = <&L2_600>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 #cooling-cells = <2>; 273 L2_600: l2-cache { 274 compatible = "cache"; 275 next-level-cache = <&L3_0>; 276 }; 277 }; 278 279 CPU7: cpu@700 { 280 device_type = "cpu"; 281 compatible = "arm,kryo"; 282 reg = <0x0 0x700>; 283 enable-method = "psci"; 284 cpu-idle-states = <&BIG_CPU_SLEEP_0 285 &BIG_CPU_SLEEP_1 286 &CLUSTER_SLEEP_0>; 287 next-level-cache = <&L2_700>; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 #cooling-cells = <2>; 290 L2_700: l2-cache { 291 compatible = "cache"; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 cpu-map { 297 cluster0 { 298 core0 { 299 cpu = <&CPU0>; 300 }; 301 302 core1 { 303 cpu = <&CPU1>; 304 }; 305 306 core2 { 307 cpu = <&CPU2>; 308 }; 309 310 core3 { 311 cpu = <&CPU3>; 312 }; 313 314 core4 { 315 cpu = <&CPU4>; 316 }; 317 318 core5 { 319 cpu = <&CPU5>; 320 }; 321 322 core6 { 323 cpu = <&CPU6>; 324 }; 325 326 core7 { 327 cpu = <&CPU7>; 328 }; 329 }; 330 }; 331 332 idle-states { 333 entry-method = "psci"; 334 335 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "little-power-down"; 338 arm,psci-suspend-param = <0x40000003>; 339 entry-latency-us = <549>; 340 exit-latency-us = <901>; 341 min-residency-us = <1774>; 342 local-timer-stop; 343 }; 344 345 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-rail-power-down"; 348 arm,psci-suspend-param = <0x40000004>; 349 entry-latency-us = <702>; 350 exit-latency-us = <915>; 351 min-residency-us = <4001>; 352 local-timer-stop; 353 }; 354 355 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "big-power-down"; 358 arm,psci-suspend-param = <0x40000003>; 359 entry-latency-us = <523>; 360 exit-latency-us = <1244>; 361 min-residency-us = <2207>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-rail-power-down"; 368 arm,psci-suspend-param = <0x40000004>; 369 entry-latency-us = <526>; 370 exit-latency-us = <1854>; 371 min-residency-us = <5555>; 372 local-timer-stop; 373 }; 374 375 CLUSTER_SLEEP_0: cluster-sleep-0 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "cluster-power-down"; 378 arm,psci-suspend-param = <0x40003444>; 379 entry-latency-us = <3263>; 380 exit-latency-us = <6562>; 381 min-residency-us = <9926>; 382 local-timer-stop; 383 }; 384 }; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0 0x80000000 0 0>; 391 }; 392 393 firmware { 394 scm { 395 compatible = "qcom,scm-sc7280", "qcom,scm"; 396 }; 397 }; 398 399 clk_virt: interconnect { 400 compatible = "qcom,sc7280-clk-virt"; 401 #interconnect-cells = <2>; 402 qcom,bcm-voters = <&apps_bcm_voter>; 403 }; 404 405 smem { 406 compatible = "qcom,smem"; 407 memory-region = <&smem_mem>; 408 hwlocks = <&tcsr_mutex 3>; 409 }; 410 411 smp2p-adsp { 412 compatible = "qcom,smp2p"; 413 qcom,smem = <443>, <429>; 414 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 415 IPCC_MPROC_SIGNAL_SMP2P 416 IRQ_TYPE_EDGE_RISING>; 417 mboxes = <&ipcc IPCC_CLIENT_LPASS 418 IPCC_MPROC_SIGNAL_SMP2P>; 419 420 qcom,local-pid = <0>; 421 qcom,remote-pid = <2>; 422 423 adsp_smp2p_out: master-kernel { 424 qcom,entry-name = "master-kernel"; 425 #qcom,smem-state-cells = <1>; 426 }; 427 428 adsp_smp2p_in: slave-kernel { 429 qcom,entry-name = "slave-kernel"; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 }; 433 }; 434 435 smp2p-cdsp { 436 compatible = "qcom,smp2p"; 437 qcom,smem = <94>, <432>; 438 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 439 IPCC_MPROC_SIGNAL_SMP2P 440 IRQ_TYPE_EDGE_RISING>; 441 mboxes = <&ipcc IPCC_CLIENT_CDSP 442 IPCC_MPROC_SIGNAL_SMP2P>; 443 444 qcom,local-pid = <0>; 445 qcom,remote-pid = <5>; 446 447 cdsp_smp2p_out: master-kernel { 448 qcom,entry-name = "master-kernel"; 449 #qcom,smem-state-cells = <1>; 450 }; 451 452 cdsp_smp2p_in: slave-kernel { 453 qcom,entry-name = "slave-kernel"; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smp2p-mpss { 460 compatible = "qcom,smp2p"; 461 qcom,smem = <435>, <428>; 462 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 463 IPCC_MPROC_SIGNAL_SMP2P 464 IRQ_TYPE_EDGE_RISING>; 465 mboxes = <&ipcc IPCC_CLIENT_MPSS 466 IPCC_MPROC_SIGNAL_SMP2P>; 467 468 qcom,local-pid = <0>; 469 qcom,remote-pid = <1>; 470 471 modem_smp2p_out: master-kernel { 472 qcom,entry-name = "master-kernel"; 473 #qcom,smem-state-cells = <1>; 474 }; 475 476 modem_smp2p_in: slave-kernel { 477 qcom,entry-name = "slave-kernel"; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 }; 481 482 ipa_smp2p_out: ipa-ap-to-modem { 483 qcom,entry-name = "ipa"; 484 #qcom,smem-state-cells = <1>; 485 }; 486 487 ipa_smp2p_in: ipa-modem-to-ap { 488 qcom,entry-name = "ipa"; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 }; 492 }; 493 494 smp2p-wpss { 495 compatible = "qcom,smp2p"; 496 qcom,smem = <617>, <616>; 497 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 498 IPCC_MPROC_SIGNAL_SMP2P 499 IRQ_TYPE_EDGE_RISING>; 500 mboxes = <&ipcc IPCC_CLIENT_WPSS 501 IPCC_MPROC_SIGNAL_SMP2P>; 502 503 qcom,local-pid = <0>; 504 qcom,remote-pid = <13>; 505 506 wpss_smp2p_out: master-kernel { 507 qcom,entry-name = "master-kernel"; 508 #qcom,smem-state-cells = <1>; 509 }; 510 511 wpss_smp2p_in: slave-kernel { 512 qcom,entry-name = "slave-kernel"; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 }; 517 518 pmu { 519 compatible = "arm,armv8-pmuv3"; 520 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 521 }; 522 523 psci { 524 compatible = "arm,psci-1.0"; 525 method = "smc"; 526 }; 527 528 qspi_opp_table: qspi-opp-table { 529 compatible = "operating-points-v2"; 530 531 opp-75000000 { 532 opp-hz = /bits/ 64 <75000000>; 533 required-opps = <&rpmhpd_opp_low_svs>; 534 }; 535 536 opp-150000000 { 537 opp-hz = /bits/ 64 <150000000>; 538 required-opps = <&rpmhpd_opp_svs>; 539 }; 540 541 opp-200000000 { 542 opp-hz = /bits/ 64 <200000000>; 543 required-opps = <&rpmhpd_opp_svs_l1>; 544 }; 545 546 opp-300000000 { 547 opp-hz = /bits/ 64 <300000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 }; 550 }; 551 552 qup_opp_table: qup-opp-table { 553 compatible = "operating-points-v2"; 554 555 opp-75000000 { 556 opp-hz = /bits/ 64 <75000000>; 557 required-opps = <&rpmhpd_opp_low_svs>; 558 }; 559 560 opp-100000000 { 561 opp-hz = /bits/ 64 <100000000>; 562 required-opps = <&rpmhpd_opp_svs>; 563 }; 564 565 opp-128000000 { 566 opp-hz = /bits/ 64 <128000000>; 567 required-opps = <&rpmhpd_opp_nom>; 568 }; 569 }; 570 571 soc: soc@0 { 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges = <0 0 0 0 0x10 0>; 575 dma-ranges = <0 0 0 0 0x10 0>; 576 compatible = "simple-bus"; 577 578 gcc: clock-controller@100000 { 579 compatible = "qcom,gcc-sc7280"; 580 reg = <0 0x00100000 0 0x1f0000>; 581 clocks = <&rpmhcc RPMH_CXO_CLK>, 582 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 583 <0>, <&pcie1_lane 0>, 584 <0>, <0>, <0>, <0>; 585 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 586 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 587 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 588 "ufs_phy_tx_symbol_0_clk", 589 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 590 #clock-cells = <1>; 591 #reset-cells = <1>; 592 #power-domain-cells = <1>; 593 }; 594 595 ipcc: mailbox@408000 { 596 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 597 reg = <0 0x00408000 0 0x1000>; 598 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-controller; 600 #interrupt-cells = <3>; 601 #mbox-cells = <2>; 602 }; 603 604 qfprom: efuse@784000 { 605 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 606 reg = <0 0x00784000 0 0xa20>, 607 <0 0x00780000 0 0xa20>, 608 <0 0x00782000 0 0x120>, 609 <0 0x00786000 0 0x1fff>; 610 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 611 clock-names = "core"; 612 power-domains = <&rpmhpd SC7280_MX>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 }; 616 617 sdhc_1: sdhci@7c4000 { 618 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 619 status = "disabled"; 620 621 reg = <0 0x007c4000 0 0x1000>, 622 <0 0x007c5000 0 0x1000>; 623 reg-names = "hc", "cqhci"; 624 625 iommus = <&apps_smmu 0xc0 0x0>; 626 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "hc_irq", "pwr_irq"; 629 630 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 631 <&gcc GCC_SDCC1_AHB_CLK>, 632 <&rpmhcc RPMH_CXO_CLK>; 633 clock-names = "core", "iface", "xo"; 634 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 635 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 636 interconnect-names = "sdhc-ddr","cpu-sdhc"; 637 power-domains = <&rpmhpd SC7280_CX>; 638 operating-points-v2 = <&sdhc1_opp_table>; 639 640 bus-width = <8>; 641 supports-cqe; 642 643 qcom,dll-config = <0x0007642c>; 644 qcom,ddr-config = <0x80040868>; 645 646 mmc-ddr-1_8v; 647 mmc-hs200-1_8v; 648 mmc-hs400-1_8v; 649 mmc-hs400-enhanced-strobe; 650 651 sdhc1_opp_table: opp-table { 652 compatible = "operating-points-v2"; 653 654 opp-100000000 { 655 opp-hz = /bits/ 64 <100000000>; 656 required-opps = <&rpmhpd_opp_low_svs>; 657 opp-peak-kBps = <1800000 400000>; 658 opp-avg-kBps = <100000 0>; 659 }; 660 661 opp-384000000 { 662 opp-hz = /bits/ 64 <384000000>; 663 required-opps = <&rpmhpd_opp_nom>; 664 opp-peak-kBps = <5400000 1600000>; 665 opp-avg-kBps = <390000 0>; 666 }; 667 }; 668 669 }; 670 671 qupv3_id_0: geniqup@9c0000 { 672 compatible = "qcom,geni-se-qup"; 673 reg = <0 0x009c0000 0 0x2000>; 674 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 675 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 676 clock-names = "m-ahb", "s-ahb"; 677 #address-cells = <2>; 678 #size-cells = <2>; 679 ranges; 680 iommus = <&apps_smmu 0x123 0x0>; 681 status = "disabled"; 682 683 i2c0: i2c@980000 { 684 compatible = "qcom,geni-i2c"; 685 reg = <0 0x00980000 0 0x4000>; 686 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 687 clock-names = "se"; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&qup_i2c0_data_clk>; 690 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 694 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 695 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 696 interconnect-names = "qup-core", "qup-config", 697 "qup-memory"; 698 status = "disabled"; 699 }; 700 701 spi0: spi@980000 { 702 compatible = "qcom,geni-spi"; 703 reg = <0 0x00980000 0 0x4000>; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 705 clock-names = "se"; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 708 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 power-domains = <&rpmhpd SC7280_CX>; 712 operating-points-v2 = <&qup_opp_table>; 713 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 715 interconnect-names = "qup-core", "qup-config"; 716 status = "disabled"; 717 }; 718 719 uart0: serial@980000 { 720 compatible = "qcom,geni-uart"; 721 reg = <0 0x00980000 0 0x4000>; 722 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 723 clock-names = "se"; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 726 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 727 power-domains = <&rpmhpd SC7280_CX>; 728 operating-points-v2 = <&qup_opp_table>; 729 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 730 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 731 interconnect-names = "qup-core", "qup-config"; 732 status = "disabled"; 733 }; 734 735 i2c1: i2c@984000 { 736 compatible = "qcom,geni-i2c"; 737 reg = <0 0x00984000 0 0x4000>; 738 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 739 clock-names = "se"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&qup_i2c1_data_clk>; 742 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 747 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 748 interconnect-names = "qup-core", "qup-config", 749 "qup-memory"; 750 status = "disabled"; 751 }; 752 753 spi1: spi@984000 { 754 compatible = "qcom,geni-spi"; 755 reg = <0 0x00984000 0 0x4000>; 756 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 757 clock-names = "se"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 760 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 power-domains = <&rpmhpd SC7280_CX>; 764 operating-points-v2 = <&qup_opp_table>; 765 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 766 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 767 interconnect-names = "qup-core", "qup-config"; 768 status = "disabled"; 769 }; 770 771 uart1: serial@984000 { 772 compatible = "qcom,geni-uart"; 773 reg = <0 0x00984000 0 0x4000>; 774 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 775 clock-names = "se"; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 778 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 779 power-domains = <&rpmhpd SC7280_CX>; 780 operating-points-v2 = <&qup_opp_table>; 781 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 782 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 783 interconnect-names = "qup-core", "qup-config"; 784 status = "disabled"; 785 }; 786 787 i2c2: i2c@988000 { 788 compatible = "qcom,geni-i2c"; 789 reg = <0 0x00988000 0 0x4000>; 790 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 791 clock-names = "se"; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_i2c2_data_clk>; 794 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 799 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 800 interconnect-names = "qup-core", "qup-config", 801 "qup-memory"; 802 status = "disabled"; 803 }; 804 805 spi2: spi@988000 { 806 compatible = "qcom,geni-spi"; 807 reg = <0 0x00988000 0 0x4000>; 808 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 809 clock-names = "se"; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 812 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 power-domains = <&rpmhpd SC7280_CX>; 816 operating-points-v2 = <&qup_opp_table>; 817 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 819 interconnect-names = "qup-core", "qup-config"; 820 status = "disabled"; 821 }; 822 823 uart2: serial@988000 { 824 compatible = "qcom,geni-uart"; 825 reg = <0 0x00988000 0 0x4000>; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 827 clock-names = "se"; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 830 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 831 power-domains = <&rpmhpd SC7280_CX>; 832 operating-points-v2 = <&qup_opp_table>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 status = "disabled"; 837 }; 838 839 i2c3: i2c@98c000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0 0x0098c000 0 0x4000>; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 843 clock-names = "se"; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&qup_i2c3_data_clk>; 846 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 850 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 851 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 852 interconnect-names = "qup-core", "qup-config", 853 "qup-memory"; 854 status = "disabled"; 855 }; 856 857 spi3: spi@98c000 { 858 compatible = "qcom,geni-spi"; 859 reg = <0 0x0098c000 0 0x4000>; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 861 clock-names = "se"; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 864 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 power-domains = <&rpmhpd SC7280_CX>; 868 operating-points-v2 = <&qup_opp_table>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 870 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 871 interconnect-names = "qup-core", "qup-config"; 872 status = "disabled"; 873 }; 874 875 uart3: serial@98c000 { 876 compatible = "qcom,geni-uart"; 877 reg = <0 0x0098c000 0 0x4000>; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 879 clock-names = "se"; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 882 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmhpd SC7280_CX>; 884 operating-points-v2 = <&qup_opp_table>; 885 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 886 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 887 interconnect-names = "qup-core", "qup-config"; 888 status = "disabled"; 889 }; 890 891 i2c4: i2c@990000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0 0x00990000 0 0x4000>; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 895 clock-names = "se"; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&qup_i2c4_data_clk>; 898 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 902 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 903 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 904 interconnect-names = "qup-core", "qup-config", 905 "qup-memory"; 906 status = "disabled"; 907 }; 908 909 spi4: spi@990000 { 910 compatible = "qcom,geni-spi"; 911 reg = <0 0x00990000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 913 clock-names = "se"; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 916 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 power-domains = <&rpmhpd SC7280_CX>; 920 operating-points-v2 = <&qup_opp_table>; 921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 923 interconnect-names = "qup-core", "qup-config"; 924 status = "disabled"; 925 }; 926 927 uart4: serial@990000 { 928 compatible = "qcom,geni-uart"; 929 reg = <0 0x00990000 0 0x4000>; 930 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 931 clock-names = "se"; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 934 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 935 power-domains = <&rpmhpd SC7280_CX>; 936 operating-points-v2 = <&qup_opp_table>; 937 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 939 interconnect-names = "qup-core", "qup-config"; 940 status = "disabled"; 941 }; 942 943 i2c5: i2c@994000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00994000 0 0x4000>; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 947 clock-names = "se"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_i2c5_data_clk>; 950 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 955 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 956 interconnect-names = "qup-core", "qup-config", 957 "qup-memory"; 958 status = "disabled"; 959 }; 960 961 spi5: spi@994000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0 0x00994000 0 0x4000>; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 965 clock-names = "se"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 968 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 power-domains = <&rpmhpd SC7280_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 uart5: serial@994000 { 980 compatible = "qcom,geni-uart"; 981 reg = <0 0x00994000 0 0x4000>; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 983 clock-names = "se"; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 986 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmhpd SC7280_CX>; 988 operating-points-v2 = <&qup_opp_table>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 status = "disabled"; 993 }; 994 995 i2c6: i2c@998000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00998000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c6_data_clk>; 1002 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", 1009 "qup-memory"; 1010 status = "disabled"; 1011 }; 1012 1013 spi6: spi@998000 { 1014 compatible = "qcom,geni-spi"; 1015 reg = <0 0x00998000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1017 clock-names = "se"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1020 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 power-domains = <&rpmhpd SC7280_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 1031 uart6: serial@998000 { 1032 compatible = "qcom,geni-uart"; 1033 reg = <0 0x00998000 0 0x4000>; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1035 clock-names = "se"; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1038 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1039 power-domains = <&rpmhpd SC7280_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1042 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1043 interconnect-names = "qup-core", "qup-config"; 1044 status = "disabled"; 1045 }; 1046 1047 i2c7: i2c@99c000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x0099c000 0 0x4000>; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1051 clock-names = "se"; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c7_data_clk>; 1054 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1059 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1060 interconnect-names = "qup-core", "qup-config", 1061 "qup-memory"; 1062 status = "disabled"; 1063 }; 1064 1065 spi7: spi@99c000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0 0x0099c000 0 0x4000>; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1069 clock-names = "se"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1072 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 power-domains = <&rpmhpd SC7280_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 status = "disabled"; 1081 }; 1082 1083 uart7: serial@99c000 { 1084 compatible = "qcom,geni-uart"; 1085 reg = <0 0x0099c000 0 0x4000>; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1087 clock-names = "se"; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1090 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SC7280_CX>; 1092 operating-points-v2 = <&qup_opp_table>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1095 interconnect-names = "qup-core", "qup-config"; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 qupv3_id_1: geniqup@ac0000 { 1101 compatible = "qcom,geni-se-qup"; 1102 reg = <0 0x00ac0000 0 0x2000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1104 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1105 clock-names = "m-ahb", "s-ahb"; 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 iommus = <&apps_smmu 0x43 0x0>; 1110 status = "disabled"; 1111 1112 i2c8: i2c@a80000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00a80000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c8_data_clk>; 1119 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1124 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", 1126 "qup-memory"; 1127 status = "disabled"; 1128 }; 1129 1130 spi8: spi@a80000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00a80000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1137 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SC7280_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 status = "disabled"; 1146 }; 1147 1148 uart8: serial@a80000 { 1149 compatible = "qcom,geni-uart"; 1150 reg = <0 0x00a80000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1152 clock-names = "se"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1155 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&rpmhpd SC7280_CX>; 1157 operating-points-v2 = <&qup_opp_table>; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c9: i2c@a84000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a84000 0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1168 clock-names = "se"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c9_data_clk>; 1171 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1176 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1177 interconnect-names = "qup-core", "qup-config", 1178 "qup-memory"; 1179 status = "disabled"; 1180 }; 1181 1182 spi9: spi@a84000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0 0x00a84000 0 0x4000>; 1185 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1186 clock-names = "se"; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1189 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 power-domains = <&rpmhpd SC7280_CX>; 1193 operating-points-v2 = <&qup_opp_table>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 uart9: serial@a84000 { 1201 compatible = "qcom,geni-uart"; 1202 reg = <0 0x00a84000 0 0x4000>; 1203 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1204 clock-names = "se"; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1208 power-domains = <&rpmhpd SC7280_CX>; 1209 operating-points-v2 = <&qup_opp_table>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1212 interconnect-names = "qup-core", "qup-config"; 1213 status = "disabled"; 1214 }; 1215 1216 i2c10: i2c@a88000 { 1217 compatible = "qcom,geni-i2c"; 1218 reg = <0 0x00a88000 0 0x4000>; 1219 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1220 clock-names = "se"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_i2c10_data_clk>; 1223 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1228 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1229 interconnect-names = "qup-core", "qup-config", 1230 "qup-memory"; 1231 status = "disabled"; 1232 }; 1233 1234 spi10: spi@a88000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0 0x00a88000 0 0x4000>; 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1238 clock-names = "se"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1241 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 power-domains = <&rpmhpd SC7280_CX>; 1245 operating-points-v2 = <&qup_opp_table>; 1246 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1247 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1248 interconnect-names = "qup-core", "qup-config"; 1249 status = "disabled"; 1250 }; 1251 1252 uart10: serial@a88000 { 1253 compatible = "qcom,geni-uart"; 1254 reg = <0 0x00a88000 0 0x4000>; 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1256 clock-names = "se"; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1259 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1260 power-domains = <&rpmhpd SC7280_CX>; 1261 operating-points-v2 = <&qup_opp_table>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 status = "disabled"; 1266 }; 1267 1268 i2c11: i2c@a8c000 { 1269 compatible = "qcom,geni-i2c"; 1270 reg = <0 0x00a8c000 0 0x4000>; 1271 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1272 clock-names = "se"; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_i2c11_data_clk>; 1275 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1280 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1281 interconnect-names = "qup-core", "qup-config", 1282 "qup-memory"; 1283 status = "disabled"; 1284 }; 1285 1286 spi11: spi@a8c000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00a8c000 0 0x4000>; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1290 clock-names = "se"; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1293 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 power-domains = <&rpmhpd SC7280_CX>; 1297 operating-points-v2 = <&qup_opp_table>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1300 interconnect-names = "qup-core", "qup-config"; 1301 status = "disabled"; 1302 }; 1303 1304 uart11: serial@a8c000 { 1305 compatible = "qcom,geni-uart"; 1306 reg = <0 0x00a8c000 0 0x4000>; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1308 clock-names = "se"; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1311 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd SC7280_CX>; 1313 operating-points-v2 = <&qup_opp_table>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1316 interconnect-names = "qup-core", "qup-config"; 1317 status = "disabled"; 1318 }; 1319 1320 i2c12: i2c@a90000 { 1321 compatible = "qcom,geni-i2c"; 1322 reg = <0 0x00a90000 0 0x4000>; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1324 clock-names = "se"; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_i2c12_data_clk>; 1327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1332 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", 1334 "qup-memory"; 1335 status = "disabled"; 1336 }; 1337 1338 spi12: spi@a90000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00a90000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1345 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 power-domains = <&rpmhpd SC7280_CX>; 1349 operating-points-v2 = <&qup_opp_table>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1351 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1352 interconnect-names = "qup-core", "qup-config"; 1353 status = "disabled"; 1354 }; 1355 1356 uart12: serial@a90000 { 1357 compatible = "qcom,geni-uart"; 1358 reg = <0 0x00a90000 0 0x4000>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1360 clock-names = "se"; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1363 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1364 power-domains = <&rpmhpd SC7280_CX>; 1365 operating-points-v2 = <&qup_opp_table>; 1366 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1367 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 status = "disabled"; 1370 }; 1371 1372 i2c13: i2c@a94000 { 1373 compatible = "qcom,geni-i2c"; 1374 reg = <0 0x00a94000 0 0x4000>; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1376 clock-names = "se"; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&qup_i2c13_data_clk>; 1379 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1384 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1385 interconnect-names = "qup-core", "qup-config", 1386 "qup-memory"; 1387 status = "disabled"; 1388 }; 1389 1390 spi13: spi@a94000 { 1391 compatible = "qcom,geni-spi"; 1392 reg = <0 0x00a94000 0 0x4000>; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1394 clock-names = "se"; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1397 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 power-domains = <&rpmhpd SC7280_CX>; 1401 operating-points-v2 = <&qup_opp_table>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1404 interconnect-names = "qup-core", "qup-config"; 1405 status = "disabled"; 1406 }; 1407 1408 uart13: serial@a94000 { 1409 compatible = "qcom,geni-uart"; 1410 reg = <0 0x00a94000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1415 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1416 power-domains = <&rpmhpd SC7280_CX>; 1417 operating-points-v2 = <&qup_opp_table>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1420 interconnect-names = "qup-core", "qup-config"; 1421 status = "disabled"; 1422 }; 1423 1424 i2c14: i2c@a98000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0 0x00a98000 0 0x4000>; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1428 clock-names = "se"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_i2c14_data_clk>; 1431 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1435 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1436 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1437 interconnect-names = "qup-core", "qup-config", 1438 "qup-memory"; 1439 status = "disabled"; 1440 }; 1441 1442 spi14: spi@a98000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a98000 0 0x4000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1446 clock-names = "se"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1449 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 power-domains = <&rpmhpd SC7280_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 uart14: serial@a98000 { 1461 compatible = "qcom,geni-uart"; 1462 reg = <0 0x00a98000 0 0x4000>; 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1464 clock-names = "se"; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1467 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&rpmhpd SC7280_CX>; 1469 operating-points-v2 = <&qup_opp_table>; 1470 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 status = "disabled"; 1474 }; 1475 1476 i2c15: i2c@a9c000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0 0x00a9c000 0 0x4000>; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1480 clock-names = "se"; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_i2c15_data_clk>; 1483 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1488 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", 1490 "qup-memory"; 1491 status = "disabled"; 1492 }; 1493 1494 spi15: spi@a9c000 { 1495 compatible = "qcom,geni-spi"; 1496 reg = <0 0x00a9c000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1501 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 power-domains = <&rpmhpd SC7280_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1508 interconnect-names = "qup-core", "qup-config"; 1509 status = "disabled"; 1510 }; 1511 1512 uart15: serial@a9c000 { 1513 compatible = "qcom,geni-uart"; 1514 reg = <0 0x00a9c000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1519 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC7280_CX>; 1521 operating-points-v2 = <&qup_opp_table>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 }; 1528 1529 cnoc2: interconnect@1500000 { 1530 reg = <0 0x01500000 0 0x1000>; 1531 compatible = "qcom,sc7280-cnoc2"; 1532 #interconnect-cells = <2>; 1533 qcom,bcm-voters = <&apps_bcm_voter>; 1534 }; 1535 1536 cnoc3: interconnect@1502000 { 1537 reg = <0 0x01502000 0 0x1000>; 1538 compatible = "qcom,sc7280-cnoc3"; 1539 #interconnect-cells = <2>; 1540 qcom,bcm-voters = <&apps_bcm_voter>; 1541 }; 1542 1543 mc_virt: interconnect@1580000 { 1544 reg = <0 0x01580000 0 0x4>; 1545 compatible = "qcom,sc7280-mc-virt"; 1546 #interconnect-cells = <2>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 system_noc: interconnect@1680000 { 1551 reg = <0 0x01680000 0 0x15480>; 1552 compatible = "qcom,sc7280-system-noc"; 1553 #interconnect-cells = <2>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 aggre1_noc: interconnect@16e0000 { 1558 compatible = "qcom,sc7280-aggre1-noc"; 1559 reg = <0 0x016e0000 0 0x1c080>; 1560 #interconnect-cells = <2>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 aggre2_noc: interconnect@1700000 { 1565 reg = <0 0x01700000 0 0x2b080>; 1566 compatible = "qcom,sc7280-aggre2-noc"; 1567 #interconnect-cells = <2>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 mmss_noc: interconnect@1740000 { 1572 reg = <0 0x01740000 0 0x1e080>; 1573 compatible = "qcom,sc7280-mmss-noc"; 1574 #interconnect-cells = <2>; 1575 qcom,bcm-voters = <&apps_bcm_voter>; 1576 }; 1577 1578 pcie1: pci@1c08000 { 1579 compatible = "qcom,pcie-sc7280"; 1580 reg = <0 0x01c08000 0 0x3000>, 1581 <0 0x40000000 0 0xf1d>, 1582 <0 0x40000f20 0 0xa8>, 1583 <0 0x40001000 0 0x1000>, 1584 <0 0x40100000 0 0x100000>; 1585 1586 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1587 device_type = "pci"; 1588 linux,pci-domain = <1>; 1589 bus-range = <0x00 0xff>; 1590 num-lanes = <2>; 1591 1592 #address-cells = <3>; 1593 #size-cells = <2>; 1594 1595 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1596 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1597 1598 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1599 interrupt-names = "msi"; 1600 #interrupt-cells = <1>; 1601 interrupt-map-mask = <0 0 0 0x7>; 1602 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1604 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1605 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1606 1607 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1608 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1609 <&pcie1_lane 0>, 1610 <&rpmhcc RPMH_CXO_CLK>, 1611 <&gcc GCC_PCIE_1_AUX_CLK>, 1612 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1613 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1615 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1616 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1617 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1618 1619 clock-names = "pipe", 1620 "pipe_mux", 1621 "phy_pipe", 1622 "ref", 1623 "aux", 1624 "cfg", 1625 "bus_master", 1626 "bus_slave", 1627 "slave_q2a", 1628 "tbu", 1629 "ddrss_sf_tbu"; 1630 1631 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1632 assigned-clock-rates = <19200000>; 1633 1634 resets = <&gcc GCC_PCIE_1_BCR>; 1635 reset-names = "pci"; 1636 1637 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1638 1639 phys = <&pcie1_lane>; 1640 phy-names = "pciephy"; 1641 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&pcie1_clkreq_n>; 1644 1645 iommus = <&apps_smmu 0x1c80 0x1>; 1646 1647 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1648 <0x100 &apps_smmu 0x1c81 0x1>; 1649 1650 status = "disabled"; 1651 }; 1652 1653 pcie1_phy: phy@1c0e000 { 1654 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1655 reg = <0 0x01c0e000 0 0x1c0>; 1656 #address-cells = <2>; 1657 #size-cells = <2>; 1658 ranges; 1659 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1660 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1661 <&gcc GCC_PCIE_CLKREF_EN>, 1662 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1663 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1664 1665 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1666 reset-names = "phy"; 1667 1668 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1669 assigned-clock-rates = <100000000>; 1670 1671 status = "disabled"; 1672 1673 pcie1_lane: lanes@1c0e200 { 1674 reg = <0 0x01c0e200 0 0x170>, 1675 <0 0x01c0e400 0 0x200>, 1676 <0 0x01c0ea00 0 0x1f0>, 1677 <0 0x01c0e600 0 0x170>, 1678 <0 0x01c0e800 0 0x200>, 1679 <0 0x01c0ee00 0 0xf4>; 1680 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1681 clock-names = "pipe0"; 1682 1683 #phy-cells = <0>; 1684 #clock-cells = <1>; 1685 clock-output-names = "pcie_1_pipe_clk"; 1686 }; 1687 }; 1688 1689 ipa: ipa@1e40000 { 1690 compatible = "qcom,sc7280-ipa"; 1691 1692 iommus = <&apps_smmu 0x480 0x0>, 1693 <&apps_smmu 0x482 0x0>; 1694 reg = <0 0x1e40000 0 0x8000>, 1695 <0 0x1e50000 0 0x4ad0>, 1696 <0 0x1e04000 0 0x23000>; 1697 reg-names = "ipa-reg", 1698 "ipa-shared", 1699 "gsi"; 1700 1701 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1702 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1703 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1704 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1705 interrupt-names = "ipa", 1706 "gsi", 1707 "ipa-clock-query", 1708 "ipa-setup-ready"; 1709 1710 clocks = <&rpmhcc RPMH_IPA_CLK>; 1711 clock-names = "core"; 1712 1713 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1715 interconnect-names = "memory", 1716 "config"; 1717 1718 qcom,smem-states = <&ipa_smp2p_out 0>, 1719 <&ipa_smp2p_out 1>; 1720 qcom,smem-state-names = "ipa-clock-enabled-valid", 1721 "ipa-clock-enabled"; 1722 1723 status = "disabled"; 1724 }; 1725 1726 tcsr_mutex: hwlock@1f40000 { 1727 compatible = "qcom,tcsr-mutex", "syscon"; 1728 reg = <0 0x01f40000 0 0x40000>; 1729 #hwlock-cells = <1>; 1730 }; 1731 1732 tcsr: syscon@1fc0000 { 1733 compatible = "qcom,sc7280-tcsr", "syscon"; 1734 reg = <0 0x01fc0000 0 0x30000>; 1735 }; 1736 1737 lpasscc: lpasscc@3000000 { 1738 compatible = "qcom,sc7280-lpasscc"; 1739 reg = <0 0x03000000 0 0x40>, 1740 <0 0x03c04000 0 0x4>, 1741 <0 0x03389000 0 0x24>; 1742 reg-names = "qdsp6ss", "top_cc", "cc"; 1743 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1744 clock-names = "iface"; 1745 #clock-cells = <1>; 1746 }; 1747 1748 lpass_ag_noc: interconnect@3c40000 { 1749 reg = <0 0x03c40000 0 0xf080>; 1750 compatible = "qcom,sc7280-lpass-ag-noc"; 1751 #interconnect-cells = <2>; 1752 qcom,bcm-voters = <&apps_bcm_voter>; 1753 }; 1754 1755 gpu: gpu@3d00000 { 1756 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1757 reg = <0 0x03d00000 0 0x40000>, 1758 <0 0x03d9e000 0 0x1000>, 1759 <0 0x03d61000 0 0x800>; 1760 reg-names = "kgsl_3d0_reg_memory", 1761 "cx_mem", 1762 "cx_dbgc"; 1763 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1764 iommus = <&adreno_smmu 0 0x401>; 1765 operating-points-v2 = <&gpu_opp_table>; 1766 qcom,gmu = <&gmu>; 1767 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1768 interconnect-names = "gfx-mem"; 1769 #cooling-cells = <2>; 1770 1771 gpu_opp_table: opp-table { 1772 compatible = "operating-points-v2"; 1773 1774 opp-315000000 { 1775 opp-hz = /bits/ 64 <315000000>; 1776 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1777 opp-peak-kBps = <1804000>; 1778 }; 1779 1780 opp-450000000 { 1781 opp-hz = /bits/ 64 <450000000>; 1782 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1783 opp-peak-kBps = <4068000>; 1784 }; 1785 1786 opp-550000000 { 1787 opp-hz = /bits/ 64 <550000000>; 1788 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1789 opp-peak-kBps = <6832000>; 1790 }; 1791 }; 1792 }; 1793 1794 gmu: gmu@3d6a000 { 1795 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1796 reg = <0 0x03d6a000 0 0x34000>, 1797 <0 0x3de0000 0 0x10000>, 1798 <0 0x0b290000 0 0x10000>; 1799 reg-names = "gmu", "rscc", "gmu_pdc"; 1800 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1802 interrupt-names = "hfi", "gmu"; 1803 clocks = <&gpucc 5>, 1804 <&gpucc 8>, 1805 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1806 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1807 <&gpucc 2>, 1808 <&gpucc 15>, 1809 <&gpucc 11>; 1810 clock-names = "gmu", 1811 "cxo", 1812 "axi", 1813 "memnoc", 1814 "ahb", 1815 "hub", 1816 "smmu_vote"; 1817 power-domains = <&gpucc 0>, 1818 <&gpucc 1>; 1819 power-domain-names = "cx", 1820 "gx"; 1821 iommus = <&adreno_smmu 5 0x400>; 1822 operating-points-v2 = <&gmu_opp_table>; 1823 1824 gmu_opp_table: opp-table { 1825 compatible = "operating-points-v2"; 1826 1827 opp-200000000 { 1828 opp-hz = /bits/ 64 <200000000>; 1829 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1830 }; 1831 }; 1832 }; 1833 1834 gpucc: clock-controller@3d90000 { 1835 compatible = "qcom,sc7280-gpucc"; 1836 reg = <0 0x03d90000 0 0x9000>; 1837 clocks = <&rpmhcc RPMH_CXO_CLK>, 1838 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1839 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1840 clock-names = "bi_tcxo", 1841 "gcc_gpu_gpll0_clk_src", 1842 "gcc_gpu_gpll0_div_clk_src"; 1843 #clock-cells = <1>; 1844 #reset-cells = <1>; 1845 #power-domain-cells = <1>; 1846 }; 1847 1848 adreno_smmu: iommu@3da0000 { 1849 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1850 reg = <0 0x03da0000 0 0x20000>; 1851 #iommu-cells = <2>; 1852 #global-interrupts = <2>; 1853 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1865 1866 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1867 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1868 <&gpucc 2>, 1869 <&gpucc 11>, 1870 <&gpucc 5>, 1871 <&gpucc 15>, 1872 <&gpucc 13>; 1873 clock-names = "gcc_gpu_memnoc_gfx_clk", 1874 "gcc_gpu_snoc_dvm_gfx_clk", 1875 "gpu_cc_ahb_clk", 1876 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1877 "gpu_cc_cx_gmu_clk", 1878 "gpu_cc_hub_cx_int_clk", 1879 "gpu_cc_hub_aon_clk"; 1880 1881 power-domains = <&gpucc 0>; 1882 }; 1883 1884 remoteproc_mpss: remoteproc@4080000 { 1885 compatible = "qcom,sc7280-mpss-pas"; 1886 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1887 reg-names = "qdsp6", "rmb"; 1888 1889 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1890 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1891 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1894 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1895 interrupt-names = "wdog", "fatal", "ready", "handover", 1896 "stop-ack", "shutdown-ack"; 1897 1898 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1899 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1900 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1901 <&rpmhcc RPMH_PKA_CLK>, 1902 <&rpmhcc RPMH_CXO_CLK>; 1903 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1904 1905 power-domains = <&rpmhpd SC7280_CX>, 1906 <&rpmhpd SC7280_MSS>; 1907 power-domain-names = "cx", "mss"; 1908 1909 memory-region = <&mpss_mem>; 1910 1911 qcom,qmp = <&aoss_qmp>; 1912 1913 qcom,smem-states = <&modem_smp2p_out 0>; 1914 qcom,smem-state-names = "stop"; 1915 1916 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1917 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1918 reset-names = "mss_restart", "pdc_reset"; 1919 1920 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1921 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1922 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1923 1924 status = "disabled"; 1925 1926 glink-edge { 1927 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1928 IPCC_MPROC_SIGNAL_GLINK_QMP 1929 IRQ_TYPE_EDGE_RISING>; 1930 mboxes = <&ipcc IPCC_CLIENT_MPSS 1931 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1932 label = "modem"; 1933 qcom,remote-pid = <1>; 1934 }; 1935 }; 1936 1937 stm@6002000 { 1938 compatible = "arm,coresight-stm", "arm,primecell"; 1939 reg = <0 0x06002000 0 0x1000>, 1940 <0 0x16280000 0 0x180000>; 1941 reg-names = "stm-base", "stm-stimulus-base"; 1942 1943 clocks = <&aoss_qmp>; 1944 clock-names = "apb_pclk"; 1945 1946 out-ports { 1947 port { 1948 stm_out: endpoint { 1949 remote-endpoint = <&funnel0_in7>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 1955 funnel@6041000 { 1956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1957 reg = <0 0x06041000 0 0x1000>; 1958 1959 clocks = <&aoss_qmp>; 1960 clock-names = "apb_pclk"; 1961 1962 out-ports { 1963 port { 1964 funnel0_out: endpoint { 1965 remote-endpoint = <&merge_funnel_in0>; 1966 }; 1967 }; 1968 }; 1969 1970 in-ports { 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 port@7 { 1975 reg = <7>; 1976 funnel0_in7: endpoint { 1977 remote-endpoint = <&stm_out>; 1978 }; 1979 }; 1980 }; 1981 }; 1982 1983 funnel@6042000 { 1984 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1985 reg = <0 0x06042000 0 0x1000>; 1986 1987 clocks = <&aoss_qmp>; 1988 clock-names = "apb_pclk"; 1989 1990 out-ports { 1991 port { 1992 funnel1_out: endpoint { 1993 remote-endpoint = <&merge_funnel_in1>; 1994 }; 1995 }; 1996 }; 1997 1998 in-ports { 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 2002 port@4 { 2003 reg = <4>; 2004 funnel1_in4: endpoint { 2005 remote-endpoint = <&apss_merge_funnel_out>; 2006 }; 2007 }; 2008 }; 2009 }; 2010 2011 funnel@6045000 { 2012 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2013 reg = <0 0x06045000 0 0x1000>; 2014 2015 clocks = <&aoss_qmp>; 2016 clock-names = "apb_pclk"; 2017 2018 out-ports { 2019 port { 2020 merge_funnel_out: endpoint { 2021 remote-endpoint = <&swao_funnel_in>; 2022 }; 2023 }; 2024 }; 2025 2026 in-ports { 2027 #address-cells = <1>; 2028 #size-cells = <0>; 2029 2030 port@0 { 2031 reg = <0>; 2032 merge_funnel_in0: endpoint { 2033 remote-endpoint = <&funnel0_out>; 2034 }; 2035 }; 2036 2037 port@1 { 2038 reg = <1>; 2039 merge_funnel_in1: endpoint { 2040 remote-endpoint = <&funnel1_out>; 2041 }; 2042 }; 2043 }; 2044 }; 2045 2046 replicator@6046000 { 2047 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2048 reg = <0 0x06046000 0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 2053 out-ports { 2054 port { 2055 replicator_out: endpoint { 2056 remote-endpoint = <&etr_in>; 2057 }; 2058 }; 2059 }; 2060 2061 in-ports { 2062 port { 2063 replicator_in: endpoint { 2064 remote-endpoint = <&swao_replicator_out>; 2065 }; 2066 }; 2067 }; 2068 }; 2069 2070 etr@6048000 { 2071 compatible = "arm,coresight-tmc", "arm,primecell"; 2072 reg = <0 0x06048000 0 0x1000>; 2073 iommus = <&apps_smmu 0x04c0 0>; 2074 2075 clocks = <&aoss_qmp>; 2076 clock-names = "apb_pclk"; 2077 arm,scatter-gather; 2078 2079 in-ports { 2080 port { 2081 etr_in: endpoint { 2082 remote-endpoint = <&replicator_out>; 2083 }; 2084 }; 2085 }; 2086 }; 2087 2088 funnel@6b04000 { 2089 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2090 reg = <0 0x06b04000 0 0x1000>; 2091 2092 clocks = <&aoss_qmp>; 2093 clock-names = "apb_pclk"; 2094 2095 out-ports { 2096 port { 2097 swao_funnel_out: endpoint { 2098 remote-endpoint = <&etf_in>; 2099 }; 2100 }; 2101 }; 2102 2103 in-ports { 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 port@7 { 2108 reg = <7>; 2109 swao_funnel_in: endpoint { 2110 remote-endpoint = <&merge_funnel_out>; 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 etf@6b05000 { 2117 compatible = "arm,coresight-tmc", "arm,primecell"; 2118 reg = <0 0x06b05000 0 0x1000>; 2119 2120 clocks = <&aoss_qmp>; 2121 clock-names = "apb_pclk"; 2122 2123 out-ports { 2124 port { 2125 etf_out: endpoint { 2126 remote-endpoint = <&swao_replicator_in>; 2127 }; 2128 }; 2129 }; 2130 2131 in-ports { 2132 port { 2133 etf_in: endpoint { 2134 remote-endpoint = <&swao_funnel_out>; 2135 }; 2136 }; 2137 }; 2138 }; 2139 2140 replicator@6b06000 { 2141 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2142 reg = <0 0x06b06000 0 0x1000>; 2143 2144 clocks = <&aoss_qmp>; 2145 clock-names = "apb_pclk"; 2146 qcom,replicator-loses-context; 2147 2148 out-ports { 2149 port { 2150 swao_replicator_out: endpoint { 2151 remote-endpoint = <&replicator_in>; 2152 }; 2153 }; 2154 }; 2155 2156 in-ports { 2157 port { 2158 swao_replicator_in: endpoint { 2159 remote-endpoint = <&etf_out>; 2160 }; 2161 }; 2162 }; 2163 }; 2164 2165 etm@7040000 { 2166 compatible = "arm,coresight-etm4x", "arm,primecell"; 2167 reg = <0 0x07040000 0 0x1000>; 2168 2169 cpu = <&CPU0>; 2170 2171 clocks = <&aoss_qmp>; 2172 clock-names = "apb_pclk"; 2173 arm,coresight-loses-context-with-cpu; 2174 qcom,skip-power-up; 2175 2176 out-ports { 2177 port { 2178 etm0_out: endpoint { 2179 remote-endpoint = <&apss_funnel_in0>; 2180 }; 2181 }; 2182 }; 2183 }; 2184 2185 etm@7140000 { 2186 compatible = "arm,coresight-etm4x", "arm,primecell"; 2187 reg = <0 0x07140000 0 0x1000>; 2188 2189 cpu = <&CPU1>; 2190 2191 clocks = <&aoss_qmp>; 2192 clock-names = "apb_pclk"; 2193 arm,coresight-loses-context-with-cpu; 2194 qcom,skip-power-up; 2195 2196 out-ports { 2197 port { 2198 etm1_out: endpoint { 2199 remote-endpoint = <&apss_funnel_in1>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 etm@7240000 { 2206 compatible = "arm,coresight-etm4x", "arm,primecell"; 2207 reg = <0 0x07240000 0 0x1000>; 2208 2209 cpu = <&CPU2>; 2210 2211 clocks = <&aoss_qmp>; 2212 clock-names = "apb_pclk"; 2213 arm,coresight-loses-context-with-cpu; 2214 qcom,skip-power-up; 2215 2216 out-ports { 2217 port { 2218 etm2_out: endpoint { 2219 remote-endpoint = <&apss_funnel_in2>; 2220 }; 2221 }; 2222 }; 2223 }; 2224 2225 etm@7340000 { 2226 compatible = "arm,coresight-etm4x", "arm,primecell"; 2227 reg = <0 0x07340000 0 0x1000>; 2228 2229 cpu = <&CPU3>; 2230 2231 clocks = <&aoss_qmp>; 2232 clock-names = "apb_pclk"; 2233 arm,coresight-loses-context-with-cpu; 2234 qcom,skip-power-up; 2235 2236 out-ports { 2237 port { 2238 etm3_out: endpoint { 2239 remote-endpoint = <&apss_funnel_in3>; 2240 }; 2241 }; 2242 }; 2243 }; 2244 2245 etm@7440000 { 2246 compatible = "arm,coresight-etm4x", "arm,primecell"; 2247 reg = <0 0x07440000 0 0x1000>; 2248 2249 cpu = <&CPU4>; 2250 2251 clocks = <&aoss_qmp>; 2252 clock-names = "apb_pclk"; 2253 arm,coresight-loses-context-with-cpu; 2254 qcom,skip-power-up; 2255 2256 out-ports { 2257 port { 2258 etm4_out: endpoint { 2259 remote-endpoint = <&apss_funnel_in4>; 2260 }; 2261 }; 2262 }; 2263 }; 2264 2265 etm@7540000 { 2266 compatible = "arm,coresight-etm4x", "arm,primecell"; 2267 reg = <0 0x07540000 0 0x1000>; 2268 2269 cpu = <&CPU5>; 2270 2271 clocks = <&aoss_qmp>; 2272 clock-names = "apb_pclk"; 2273 arm,coresight-loses-context-with-cpu; 2274 qcom,skip-power-up; 2275 2276 out-ports { 2277 port { 2278 etm5_out: endpoint { 2279 remote-endpoint = <&apss_funnel_in5>; 2280 }; 2281 }; 2282 }; 2283 }; 2284 2285 etm@7640000 { 2286 compatible = "arm,coresight-etm4x", "arm,primecell"; 2287 reg = <0 0x07640000 0 0x1000>; 2288 2289 cpu = <&CPU6>; 2290 2291 clocks = <&aoss_qmp>; 2292 clock-names = "apb_pclk"; 2293 arm,coresight-loses-context-with-cpu; 2294 qcom,skip-power-up; 2295 2296 out-ports { 2297 port { 2298 etm6_out: endpoint { 2299 remote-endpoint = <&apss_funnel_in6>; 2300 }; 2301 }; 2302 }; 2303 }; 2304 2305 etm@7740000 { 2306 compatible = "arm,coresight-etm4x", "arm,primecell"; 2307 reg = <0 0x07740000 0 0x1000>; 2308 2309 cpu = <&CPU7>; 2310 2311 clocks = <&aoss_qmp>; 2312 clock-names = "apb_pclk"; 2313 arm,coresight-loses-context-with-cpu; 2314 qcom,skip-power-up; 2315 2316 out-ports { 2317 port { 2318 etm7_out: endpoint { 2319 remote-endpoint = <&apss_funnel_in7>; 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 funnel@7800000 { /* APSS Funnel */ 2326 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2327 reg = <0 0x07800000 0 0x1000>; 2328 2329 clocks = <&aoss_qmp>; 2330 clock-names = "apb_pclk"; 2331 2332 out-ports { 2333 port { 2334 apss_funnel_out: endpoint { 2335 remote-endpoint = <&apss_merge_funnel_in>; 2336 }; 2337 }; 2338 }; 2339 2340 in-ports { 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 2344 port@0 { 2345 reg = <0>; 2346 apss_funnel_in0: endpoint { 2347 remote-endpoint = <&etm0_out>; 2348 }; 2349 }; 2350 2351 port@1 { 2352 reg = <1>; 2353 apss_funnel_in1: endpoint { 2354 remote-endpoint = <&etm1_out>; 2355 }; 2356 }; 2357 2358 port@2 { 2359 reg = <2>; 2360 apss_funnel_in2: endpoint { 2361 remote-endpoint = <&etm2_out>; 2362 }; 2363 }; 2364 2365 port@3 { 2366 reg = <3>; 2367 apss_funnel_in3: endpoint { 2368 remote-endpoint = <&etm3_out>; 2369 }; 2370 }; 2371 2372 port@4 { 2373 reg = <4>; 2374 apss_funnel_in4: endpoint { 2375 remote-endpoint = <&etm4_out>; 2376 }; 2377 }; 2378 2379 port@5 { 2380 reg = <5>; 2381 apss_funnel_in5: endpoint { 2382 remote-endpoint = <&etm5_out>; 2383 }; 2384 }; 2385 2386 port@6 { 2387 reg = <6>; 2388 apss_funnel_in6: endpoint { 2389 remote-endpoint = <&etm6_out>; 2390 }; 2391 }; 2392 2393 port@7 { 2394 reg = <7>; 2395 apss_funnel_in7: endpoint { 2396 remote-endpoint = <&etm7_out>; 2397 }; 2398 }; 2399 }; 2400 }; 2401 2402 funnel@7810000 { 2403 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2404 reg = <0 0x07810000 0 0x1000>; 2405 2406 clocks = <&aoss_qmp>; 2407 clock-names = "apb_pclk"; 2408 2409 out-ports { 2410 port { 2411 apss_merge_funnel_out: endpoint { 2412 remote-endpoint = <&funnel1_in4>; 2413 }; 2414 }; 2415 }; 2416 2417 in-ports { 2418 port { 2419 apss_merge_funnel_in: endpoint { 2420 remote-endpoint = <&apss_funnel_out>; 2421 }; 2422 }; 2423 }; 2424 }; 2425 2426 sdhc_2: sdhci@8804000 { 2427 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2428 status = "disabled"; 2429 2430 reg = <0 0x08804000 0 0x1000>; 2431 2432 iommus = <&apps_smmu 0x100 0x0>; 2433 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2435 interrupt-names = "hc_irq", "pwr_irq"; 2436 2437 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2438 <&gcc GCC_SDCC2_AHB_CLK>, 2439 <&rpmhcc RPMH_CXO_CLK>; 2440 clock-names = "core", "iface", "xo"; 2441 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2442 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2443 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2444 power-domains = <&rpmhpd SC7280_CX>; 2445 operating-points-v2 = <&sdhc2_opp_table>; 2446 2447 bus-width = <4>; 2448 2449 qcom,dll-config = <0x0007642c>; 2450 2451 sdhc2_opp_table: opp-table { 2452 compatible = "operating-points-v2"; 2453 2454 opp-100000000 { 2455 opp-hz = /bits/ 64 <100000000>; 2456 required-opps = <&rpmhpd_opp_low_svs>; 2457 opp-peak-kBps = <1800000 400000>; 2458 opp-avg-kBps = <100000 0>; 2459 }; 2460 2461 opp-202000000 { 2462 opp-hz = /bits/ 64 <202000000>; 2463 required-opps = <&rpmhpd_opp_nom>; 2464 opp-peak-kBps = <5400000 1600000>; 2465 opp-avg-kBps = <200000 0>; 2466 }; 2467 }; 2468 2469 }; 2470 2471 usb_1_hsphy: phy@88e3000 { 2472 compatible = "qcom,sc7280-usb-hs-phy", 2473 "qcom,usb-snps-hs-7nm-phy"; 2474 reg = <0 0x088e3000 0 0x400>; 2475 status = "disabled"; 2476 #phy-cells = <0>; 2477 2478 clocks = <&rpmhcc RPMH_CXO_CLK>; 2479 clock-names = "ref"; 2480 2481 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2482 }; 2483 2484 usb_2_hsphy: phy@88e4000 { 2485 compatible = "qcom,sc7280-usb-hs-phy", 2486 "qcom,usb-snps-hs-7nm-phy"; 2487 reg = <0 0x088e4000 0 0x400>; 2488 status = "disabled"; 2489 #phy-cells = <0>; 2490 2491 clocks = <&rpmhcc RPMH_CXO_CLK>; 2492 clock-names = "ref"; 2493 2494 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2495 }; 2496 2497 usb_1_qmpphy: phy-wrapper@88e9000 { 2498 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2499 "qcom,sm8250-qmp-usb3-dp-phy"; 2500 reg = <0 0x088e9000 0 0x200>, 2501 <0 0x088e8000 0 0x40>, 2502 <0 0x088ea000 0 0x200>; 2503 status = "disabled"; 2504 #address-cells = <2>; 2505 #size-cells = <2>; 2506 ranges; 2507 2508 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2509 <&rpmhcc RPMH_CXO_CLK>, 2510 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2511 clock-names = "aux", "ref_clk_src", "com_aux"; 2512 2513 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2514 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2515 reset-names = "phy", "common"; 2516 2517 usb_1_ssphy: usb3-phy@88e9200 { 2518 reg = <0 0x088e9200 0 0x200>, 2519 <0 0x088e9400 0 0x200>, 2520 <0 0x088e9c00 0 0x400>, 2521 <0 0x088e9600 0 0x200>, 2522 <0 0x088e9800 0 0x200>, 2523 <0 0x088e9a00 0 0x100>; 2524 #clock-cells = <0>; 2525 #phy-cells = <0>; 2526 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2527 clock-names = "pipe0"; 2528 clock-output-names = "usb3_phy_pipe_clk_src"; 2529 }; 2530 2531 dp_phy: dp-phy@88ea200 { 2532 reg = <0 0x088ea200 0 0x200>, 2533 <0 0x088ea400 0 0x200>, 2534 <0 0x088eaa00 0 0x200>, 2535 <0 0x088ea600 0 0x200>, 2536 <0 0x088ea800 0 0x200>; 2537 #phy-cells = <0>; 2538 #clock-cells = <1>; 2539 }; 2540 }; 2541 2542 usb_2: usb@8cf8800 { 2543 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2544 reg = <0 0x08cf8800 0 0x400>; 2545 status = "disabled"; 2546 #address-cells = <2>; 2547 #size-cells = <2>; 2548 ranges; 2549 dma-ranges; 2550 2551 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2552 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2553 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2554 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2555 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2556 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2557 "sleep"; 2558 2559 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2560 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2561 assigned-clock-rates = <19200000>, <200000000>; 2562 2563 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2564 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2565 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2566 interrupt-names = "hs_phy_irq", 2567 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2568 2569 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2570 2571 resets = <&gcc GCC_USB30_SEC_BCR>; 2572 2573 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2574 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2575 interconnect-names = "usb-ddr", "apps-usb"; 2576 2577 usb_2_dwc3: usb@8c00000 { 2578 compatible = "snps,dwc3"; 2579 reg = <0 0x08c00000 0 0xe000>; 2580 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2581 iommus = <&apps_smmu 0xa0 0x0>; 2582 snps,dis_u2_susphy_quirk; 2583 snps,dis_enblslpm_quirk; 2584 phys = <&usb_2_hsphy>; 2585 phy-names = "usb2-phy"; 2586 maximum-speed = "high-speed"; 2587 }; 2588 }; 2589 2590 qspi: spi@88dc000 { 2591 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2592 reg = <0 0x088dc000 0 0x1000>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2597 <&gcc GCC_QSPI_CORE_CLK>; 2598 clock-names = "iface", "core"; 2599 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2600 &cnoc2 SLAVE_QSPI_0 0>; 2601 interconnect-names = "qspi-config"; 2602 power-domains = <&rpmhpd SC7280_CX>; 2603 operating-points-v2 = <&qspi_opp_table>; 2604 status = "disabled"; 2605 }; 2606 2607 dc_noc: interconnect@90e0000 { 2608 reg = <0 0x090e0000 0 0x5080>; 2609 compatible = "qcom,sc7280-dc-noc"; 2610 #interconnect-cells = <2>; 2611 qcom,bcm-voters = <&apps_bcm_voter>; 2612 }; 2613 2614 gem_noc: interconnect@9100000 { 2615 reg = <0 0x9100000 0 0xe2200>; 2616 compatible = "qcom,sc7280-gem-noc"; 2617 #interconnect-cells = <2>; 2618 qcom,bcm-voters = <&apps_bcm_voter>; 2619 }; 2620 2621 system-cache-controller@9200000 { 2622 compatible = "qcom,sc7280-llcc"; 2623 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2624 reg-names = "llcc_base", "llcc_broadcast_base"; 2625 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2626 }; 2627 2628 nsp_noc: interconnect@a0c0000 { 2629 reg = <0 0x0a0c0000 0 0x10000>; 2630 compatible = "qcom,sc7280-nsp-noc"; 2631 #interconnect-cells = <2>; 2632 qcom,bcm-voters = <&apps_bcm_voter>; 2633 }; 2634 2635 usb_1: usb@a6f8800 { 2636 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2637 reg = <0 0x0a6f8800 0 0x400>; 2638 status = "disabled"; 2639 #address-cells = <2>; 2640 #size-cells = <2>; 2641 ranges; 2642 dma-ranges; 2643 2644 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2645 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2646 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2647 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2648 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2649 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2650 "sleep"; 2651 2652 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2653 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2654 assigned-clock-rates = <19200000>, <200000000>; 2655 2656 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2657 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2658 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2659 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2660 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2661 "dm_hs_phy_irq", "ss_phy_irq"; 2662 2663 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2664 2665 resets = <&gcc GCC_USB30_PRIM_BCR>; 2666 2667 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2669 interconnect-names = "usb-ddr", "apps-usb"; 2670 2671 usb_1_dwc3: usb@a600000 { 2672 compatible = "snps,dwc3"; 2673 reg = <0 0x0a600000 0 0xe000>; 2674 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2675 iommus = <&apps_smmu 0xe0 0x0>; 2676 snps,dis_u2_susphy_quirk; 2677 snps,dis_enblslpm_quirk; 2678 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2679 phy-names = "usb2-phy", "usb3-phy"; 2680 maximum-speed = "super-speed"; 2681 }; 2682 }; 2683 2684 venus: video-codec@aa00000 { 2685 compatible = "qcom,sc7280-venus"; 2686 reg = <0 0x0aa00000 0 0xd0600>; 2687 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2688 2689 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2690 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2691 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2692 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2693 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2694 clock-names = "core", "bus", "iface", 2695 "vcodec_core", "vcodec_bus"; 2696 2697 power-domains = <&videocc MVSC_GDSC>, 2698 <&videocc MVS0_GDSC>, 2699 <&rpmhpd SC7280_CX>; 2700 power-domain-names = "venus", "vcodec0", "cx"; 2701 operating-points-v2 = <&venus_opp_table>; 2702 2703 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2704 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2705 interconnect-names = "cpu-cfg", "video-mem"; 2706 2707 iommus = <&apps_smmu 0x2180 0x20>, 2708 <&apps_smmu 0x2184 0x20>; 2709 memory-region = <&video_mem>; 2710 2711 video-decoder { 2712 compatible = "venus-decoder"; 2713 }; 2714 2715 video-encoder { 2716 compatible = "venus-encoder"; 2717 }; 2718 2719 video-firmware { 2720 iommus = <&apps_smmu 0x21a2 0x0>; 2721 }; 2722 2723 venus_opp_table: venus-opp-table { 2724 compatible = "operating-points-v2"; 2725 2726 opp-133330000 { 2727 opp-hz = /bits/ 64 <133330000>; 2728 required-opps = <&rpmhpd_opp_low_svs>; 2729 }; 2730 2731 opp-240000000 { 2732 opp-hz = /bits/ 64 <240000000>; 2733 required-opps = <&rpmhpd_opp_svs>; 2734 }; 2735 2736 opp-335000000 { 2737 opp-hz = /bits/ 64 <335000000>; 2738 required-opps = <&rpmhpd_opp_svs_l1>; 2739 }; 2740 2741 opp-424000000 { 2742 opp-hz = /bits/ 64 <424000000>; 2743 required-opps = <&rpmhpd_opp_nom>; 2744 }; 2745 2746 opp-460000048 { 2747 opp-hz = /bits/ 64 <460000048>; 2748 required-opps = <&rpmhpd_opp_turbo>; 2749 }; 2750 }; 2751 2752 }; 2753 2754 videocc: clock-controller@aaf0000 { 2755 compatible = "qcom,sc7280-videocc"; 2756 reg = <0 0xaaf0000 0 0x10000>; 2757 clocks = <&rpmhcc RPMH_CXO_CLK>, 2758 <&rpmhcc RPMH_CXO_CLK_A>; 2759 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2760 #clock-cells = <1>; 2761 #reset-cells = <1>; 2762 #power-domain-cells = <1>; 2763 }; 2764 2765 camcc: clock-controller@ad00000 { 2766 compatible = "qcom,sc7280-camcc"; 2767 reg = <0 0x0ad00000 0 0x10000>; 2768 clocks = <&rpmhcc RPMH_CXO_CLK>, 2769 <&rpmhcc RPMH_CXO_CLK_A>, 2770 <&sleep_clk>; 2771 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 2772 #clock-cells = <1>; 2773 #reset-cells = <1>; 2774 #power-domain-cells = <1>; 2775 }; 2776 2777 dispcc: clock-controller@af00000 { 2778 compatible = "qcom,sc7280-dispcc"; 2779 reg = <0 0xaf00000 0 0x20000>; 2780 clocks = <&rpmhcc RPMH_CXO_CLK>, 2781 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2782 <&mdss_dsi_phy 0>, 2783 <&mdss_dsi_phy 1>, 2784 <&dp_phy 0>, 2785 <&dp_phy 1>, 2786 <&mdss_edp_phy 0>, 2787 <&mdss_edp_phy 1>; 2788 clock-names = "bi_tcxo", 2789 "gcc_disp_gpll0_clk", 2790 "dsi0_phy_pll_out_byteclk", 2791 "dsi0_phy_pll_out_dsiclk", 2792 "dp_phy_pll_link_clk", 2793 "dp_phy_pll_vco_div_clk", 2794 "edp_phy_pll_link_clk", 2795 "edp_phy_pll_vco_div_clk"; 2796 #clock-cells = <1>; 2797 #reset-cells = <1>; 2798 #power-domain-cells = <1>; 2799 }; 2800 2801 mdss: display-subsystem@ae00000 { 2802 compatible = "qcom,sc7280-mdss"; 2803 reg = <0 0x0ae00000 0 0x1000>; 2804 reg-names = "mdss"; 2805 2806 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 2807 2808 clocks = <&gcc GCC_DISP_AHB_CLK>, 2809 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2810 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2811 clock-names = "iface", 2812 "ahb", 2813 "core"; 2814 2815 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2816 assigned-clock-rates = <300000000>; 2817 2818 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2819 interrupt-controller; 2820 #interrupt-cells = <1>; 2821 2822 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2823 interconnect-names = "mdp0-mem"; 2824 2825 iommus = <&apps_smmu 0x900 0x402>; 2826 2827 #address-cells = <2>; 2828 #size-cells = <2>; 2829 ranges; 2830 2831 status = "disabled"; 2832 2833 mdss_mdp: display-controller@ae01000 { 2834 compatible = "qcom,sc7280-dpu"; 2835 reg = <0 0x0ae01000 0 0x8f030>, 2836 <0 0x0aeb0000 0 0x2008>; 2837 reg-names = "mdp", "vbif"; 2838 2839 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2840 <&gcc GCC_DISP_SF_AXI_CLK>, 2841 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2842 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2843 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2844 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2845 clock-names = "bus", 2846 "nrt_bus", 2847 "iface", 2848 "lut", 2849 "core", 2850 "vsync"; 2851 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2852 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2853 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2854 assigned-clock-rates = <300000000>, 2855 <19200000>, 2856 <19200000>; 2857 operating-points-v2 = <&mdp_opp_table>; 2858 power-domains = <&rpmhpd SC7280_CX>; 2859 2860 interrupt-parent = <&mdss>; 2861 interrupts = <0>; 2862 2863 status = "disabled"; 2864 2865 ports { 2866 #address-cells = <1>; 2867 #size-cells = <0>; 2868 2869 port@0 { 2870 reg = <0>; 2871 dpu_intf1_out: endpoint { 2872 remote-endpoint = <&dsi0_in>; 2873 }; 2874 }; 2875 2876 port@1 { 2877 reg = <1>; 2878 dpu_intf5_out: endpoint { 2879 remote-endpoint = <&edp_in>; 2880 }; 2881 }; 2882 2883 port@2 { 2884 reg = <2>; 2885 dpu_intf0_out: endpoint { 2886 remote-endpoint = <&dp_in>; 2887 }; 2888 }; 2889 }; 2890 2891 mdp_opp_table: opp-table { 2892 compatible = "operating-points-v2"; 2893 2894 opp-200000000 { 2895 opp-hz = /bits/ 64 <200000000>; 2896 required-opps = <&rpmhpd_opp_low_svs>; 2897 }; 2898 2899 opp-300000000 { 2900 opp-hz = /bits/ 64 <300000000>; 2901 required-opps = <&rpmhpd_opp_svs>; 2902 }; 2903 2904 opp-380000000 { 2905 opp-hz = /bits/ 64 <380000000>; 2906 required-opps = <&rpmhpd_opp_svs_l1>; 2907 }; 2908 2909 opp-506666667 { 2910 opp-hz = /bits/ 64 <506666667>; 2911 required-opps = <&rpmhpd_opp_nom>; 2912 }; 2913 }; 2914 }; 2915 2916 mdss_dsi: dsi@ae94000 { 2917 compatible = "qcom,mdss-dsi-ctrl"; 2918 reg = <0 0x0ae94000 0 0x400>; 2919 reg-names = "dsi_ctrl"; 2920 2921 interrupt-parent = <&mdss>; 2922 interrupts = <4>; 2923 2924 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2925 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2926 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2927 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2928 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2929 <&gcc GCC_DISP_HF_AXI_CLK>; 2930 clock-names = "byte", 2931 "byte_intf", 2932 "pixel", 2933 "core", 2934 "iface", 2935 "bus"; 2936 2937 operating-points-v2 = <&dsi_opp_table>; 2938 power-domains = <&rpmhpd SC7280_CX>; 2939 2940 phys = <&mdss_dsi_phy>; 2941 phy-names = "dsi"; 2942 2943 #address-cells = <1>; 2944 #size-cells = <0>; 2945 2946 status = "disabled"; 2947 2948 ports { 2949 #address-cells = <1>; 2950 #size-cells = <0>; 2951 2952 port@0 { 2953 reg = <0>; 2954 dsi0_in: endpoint { 2955 remote-endpoint = <&dpu_intf1_out>; 2956 }; 2957 }; 2958 2959 port@1 { 2960 reg = <1>; 2961 dsi0_out: endpoint { 2962 }; 2963 }; 2964 }; 2965 2966 dsi_opp_table: opp-table { 2967 compatible = "operating-points-v2"; 2968 2969 opp-187500000 { 2970 opp-hz = /bits/ 64 <187500000>; 2971 required-opps = <&rpmhpd_opp_low_svs>; 2972 }; 2973 2974 opp-300000000 { 2975 opp-hz = /bits/ 64 <300000000>; 2976 required-opps = <&rpmhpd_opp_svs>; 2977 }; 2978 2979 opp-358000000 { 2980 opp-hz = /bits/ 64 <358000000>; 2981 required-opps = <&rpmhpd_opp_svs_l1>; 2982 }; 2983 }; 2984 }; 2985 2986 mdss_dsi_phy: phy@ae94400 { 2987 compatible = "qcom,sc7280-dsi-phy-7nm"; 2988 reg = <0 0x0ae94400 0 0x200>, 2989 <0 0x0ae94600 0 0x280>, 2990 <0 0x0ae94900 0 0x280>; 2991 reg-names = "dsi_phy", 2992 "dsi_phy_lane", 2993 "dsi_pll"; 2994 2995 #clock-cells = <1>; 2996 #phy-cells = <0>; 2997 2998 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2999 <&rpmhcc RPMH_CXO_CLK>; 3000 clock-names = "iface", "ref"; 3001 3002 status = "disabled"; 3003 }; 3004 3005 mdss_edp: edp@aea0000 { 3006 compatible = "qcom,sc7280-edp"; 3007 3008 reg = <0 0xaea0000 0 0x200>, 3009 <0 0xaea0200 0 0x200>, 3010 <0 0xaea0400 0 0xc00>, 3011 <0 0xaea1000 0 0x400>; 3012 3013 interrupt-parent = <&mdss>; 3014 interrupts = <14>; 3015 3016 clocks = <&rpmhcc RPMH_CXO_CLK>, 3017 <&gcc GCC_EDP_CLKREF_EN>, 3018 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3019 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3020 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3021 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3022 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3023 clock-names = "core_xo", 3024 "core_ref", 3025 "core_iface", 3026 "core_aux", 3027 "ctrl_link", 3028 "ctrl_link_iface", 3029 "stream_pixel"; 3030 #clock-cells = <1>; 3031 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3032 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3033 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3034 3035 phys = <&mdss_edp_phy>; 3036 phy-names = "dp"; 3037 3038 operating-points-v2 = <&edp_opp_table>; 3039 power-domains = <&rpmhpd SC7280_CX>; 3040 3041 #address-cells = <1>; 3042 #size-cells = <0>; 3043 3044 status = "disabled"; 3045 3046 ports { 3047 #address-cells = <1>; 3048 #size-cells = <0>; 3049 port@0 { 3050 reg = <0>; 3051 edp_in: endpoint { 3052 remote-endpoint = <&dpu_intf5_out>; 3053 }; 3054 }; 3055 }; 3056 3057 edp_opp_table: opp-table { 3058 compatible = "operating-points-v2"; 3059 3060 opp-160000000 { 3061 opp-hz = /bits/ 64 <160000000>; 3062 required-opps = <&rpmhpd_opp_low_svs>; 3063 }; 3064 3065 opp-270000000 { 3066 opp-hz = /bits/ 64 <270000000>; 3067 required-opps = <&rpmhpd_opp_svs>; 3068 }; 3069 3070 opp-540000000 { 3071 opp-hz = /bits/ 64 <540000000>; 3072 required-opps = <&rpmhpd_opp_nom>; 3073 }; 3074 3075 opp-810000000 { 3076 opp-hz = /bits/ 64 <810000000>; 3077 required-opps = <&rpmhpd_opp_nom>; 3078 }; 3079 }; 3080 }; 3081 3082 mdss_edp_phy: phy@aec2a00 { 3083 compatible = "qcom,sc7280-edp-phy"; 3084 3085 reg = <0 0xaec2a00 0 0x19c>, 3086 <0 0xaec2200 0 0xa0>, 3087 <0 0xaec2600 0 0xa0>, 3088 <0 0xaec2000 0 0x1c0>; 3089 3090 clocks = <&rpmhcc RPMH_CXO_CLK>, 3091 <&gcc GCC_EDP_CLKREF_EN>; 3092 clock-names = "aux", 3093 "cfg_ahb"; 3094 3095 #clock-cells = <1>; 3096 #phy-cells = <0>; 3097 3098 status = "disabled"; 3099 }; 3100 3101 mdss_dp: displayport-controller@ae90000 { 3102 compatible = "qcom,sc7280-dp"; 3103 3104 reg = <0 0x0ae90000 0 0x1400>; 3105 3106 interrupt-parent = <&mdss>; 3107 interrupts = <12>; 3108 3109 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3110 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3111 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3112 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3113 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3114 clock-names = "core_iface", 3115 "core_aux", 3116 "ctrl_link", 3117 "ctrl_link_iface", 3118 "stream_pixel"; 3119 #clock-cells = <1>; 3120 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3121 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3122 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3123 phys = <&dp_phy>; 3124 phy-names = "dp"; 3125 3126 operating-points-v2 = <&dp_opp_table>; 3127 power-domains = <&rpmhpd SC7280_CX>; 3128 3129 #sound-dai-cells = <0>; 3130 3131 status = "disabled"; 3132 3133 ports { 3134 #address-cells = <1>; 3135 #size-cells = <0>; 3136 port@0 { 3137 reg = <0>; 3138 dp_in: endpoint { 3139 remote-endpoint = <&dpu_intf0_out>; 3140 }; 3141 }; 3142 3143 port@1 { 3144 reg = <1>; 3145 dp_out: endpoint { }; 3146 }; 3147 }; 3148 3149 dp_opp_table: opp-table { 3150 compatible = "operating-points-v2"; 3151 3152 opp-160000000 { 3153 opp-hz = /bits/ 64 <160000000>; 3154 required-opps = <&rpmhpd_opp_low_svs>; 3155 }; 3156 3157 opp-270000000 { 3158 opp-hz = /bits/ 64 <270000000>; 3159 required-opps = <&rpmhpd_opp_svs>; 3160 }; 3161 3162 opp-540000000 { 3163 opp-hz = /bits/ 64 <540000000>; 3164 required-opps = <&rpmhpd_opp_svs_l1>; 3165 }; 3166 3167 opp-810000000 { 3168 opp-hz = /bits/ 64 <810000000>; 3169 required-opps = <&rpmhpd_opp_nom>; 3170 }; 3171 }; 3172 }; 3173 }; 3174 3175 pdc: interrupt-controller@b220000 { 3176 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3177 reg = <0 0x0b220000 0 0x30000>; 3178 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3179 <55 306 4>, <59 312 3>, <62 374 2>, 3180 <64 434 2>, <66 438 3>, <69 86 1>, 3181 <70 520 54>, <124 609 31>, <155 63 1>, 3182 <156 716 12>; 3183 #interrupt-cells = <2>; 3184 interrupt-parent = <&intc>; 3185 interrupt-controller; 3186 }; 3187 3188 pdc_reset: reset-controller@b5e0000 { 3189 compatible = "qcom,sc7280-pdc-global"; 3190 reg = <0 0x0b5e0000 0 0x20000>; 3191 #reset-cells = <1>; 3192 }; 3193 3194 tsens0: thermal-sensor@c263000 { 3195 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3196 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3197 <0 0x0c222000 0 0x1ff>; /* SROT */ 3198 #qcom,sensors = <15>; 3199 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3201 interrupt-names = "uplow","critical"; 3202 #thermal-sensor-cells = <1>; 3203 }; 3204 3205 tsens1: thermal-sensor@c265000 { 3206 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3207 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3208 <0 0x0c223000 0 0x1ff>; /* SROT */ 3209 #qcom,sensors = <12>; 3210 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3212 interrupt-names = "uplow","critical"; 3213 #thermal-sensor-cells = <1>; 3214 }; 3215 3216 aoss_reset: reset-controller@c2a0000 { 3217 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3218 reg = <0 0x0c2a0000 0 0x31000>; 3219 #reset-cells = <1>; 3220 }; 3221 3222 aoss_qmp: power-controller@c300000 { 3223 compatible = "qcom,sc7280-aoss-qmp"; 3224 reg = <0 0x0c300000 0 0x400>; 3225 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3226 IPCC_MPROC_SIGNAL_GLINK_QMP 3227 IRQ_TYPE_EDGE_RISING>; 3228 mboxes = <&ipcc IPCC_CLIENT_AOP 3229 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3230 3231 #clock-cells = <0>; 3232 }; 3233 3234 sram@c3f0000 { 3235 compatible = "qcom,rpmh-stats"; 3236 reg = <0 0x0c3f0000 0 0x400>; 3237 }; 3238 3239 spmi_bus: spmi@c440000 { 3240 compatible = "qcom,spmi-pmic-arb"; 3241 reg = <0 0x0c440000 0 0x1100>, 3242 <0 0x0c600000 0 0x2000000>, 3243 <0 0x0e600000 0 0x100000>, 3244 <0 0x0e700000 0 0xa0000>, 3245 <0 0x0c40a000 0 0x26000>; 3246 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3247 interrupt-names = "periph_irq"; 3248 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3249 qcom,ee = <0>; 3250 qcom,channel = <0>; 3251 #address-cells = <1>; 3252 #size-cells = <1>; 3253 interrupt-controller; 3254 #interrupt-cells = <4>; 3255 }; 3256 3257 tlmm: pinctrl@f100000 { 3258 compatible = "qcom,sc7280-pinctrl"; 3259 reg = <0 0x0f100000 0 0x300000>; 3260 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3261 gpio-controller; 3262 #gpio-cells = <2>; 3263 interrupt-controller; 3264 #interrupt-cells = <2>; 3265 gpio-ranges = <&tlmm 0 0 175>; 3266 wakeup-parent = <&pdc>; 3267 3268 pcie1_clkreq_n: pcie1-clkreq-n { 3269 pins = "gpio79"; 3270 function = "pcie1_clkreqn"; 3271 drive-strength = <2>; 3272 bias-pull-up; 3273 }; 3274 3275 dp_hot_plug_det: dp-hot-plug-det { 3276 pins = "gpio47"; 3277 function = "dp_hot"; 3278 bias-disable; 3279 }; 3280 3281 qspi_clk: qspi-clk { 3282 pins = "gpio14"; 3283 function = "qspi_clk"; 3284 }; 3285 3286 qspi_cs0: qspi-cs0 { 3287 pins = "gpio15"; 3288 function = "qspi_cs"; 3289 }; 3290 3291 qspi_cs1: qspi-cs1 { 3292 pins = "gpio19"; 3293 function = "qspi_cs"; 3294 }; 3295 3296 qspi_data01: qspi-data01 { 3297 pins = "gpio12", "gpio13"; 3298 function = "qspi_data"; 3299 }; 3300 3301 qspi_data12: qspi-data12 { 3302 pins = "gpio16", "gpio17"; 3303 function = "qspi_data"; 3304 }; 3305 3306 qup_i2c0_data_clk: qup-i2c0-data-clk { 3307 pins = "gpio0", "gpio1"; 3308 function = "qup00"; 3309 }; 3310 3311 qup_i2c1_data_clk: qup-i2c1-data-clk { 3312 pins = "gpio4", "gpio5"; 3313 function = "qup01"; 3314 }; 3315 3316 qup_i2c2_data_clk: qup-i2c2-data-clk { 3317 pins = "gpio8", "gpio9"; 3318 function = "qup02"; 3319 }; 3320 3321 qup_i2c3_data_clk: qup-i2c3-data-clk { 3322 pins = "gpio12", "gpio13"; 3323 function = "qup03"; 3324 }; 3325 3326 qup_i2c4_data_clk: qup-i2c4-data-clk { 3327 pins = "gpio16", "gpio17"; 3328 function = "qup04"; 3329 }; 3330 3331 qup_i2c5_data_clk: qup-i2c5-data-clk { 3332 pins = "gpio20", "gpio21"; 3333 function = "qup05"; 3334 }; 3335 3336 qup_i2c6_data_clk: qup-i2c6-data-clk { 3337 pins = "gpio24", "gpio25"; 3338 function = "qup06"; 3339 }; 3340 3341 qup_i2c7_data_clk: qup-i2c7-data-clk { 3342 pins = "gpio28", "gpio29"; 3343 function = "qup07"; 3344 }; 3345 3346 qup_i2c8_data_clk: qup-i2c8-data-clk { 3347 pins = "gpio32", "gpio33"; 3348 function = "qup10"; 3349 }; 3350 3351 qup_i2c9_data_clk: qup-i2c9-data-clk { 3352 pins = "gpio36", "gpio37"; 3353 function = "qup11"; 3354 }; 3355 3356 qup_i2c10_data_clk: qup-i2c10-data-clk { 3357 pins = "gpio40", "gpio41"; 3358 function = "qup12"; 3359 }; 3360 3361 qup_i2c11_data_clk: qup-i2c11-data-clk { 3362 pins = "gpio44", "gpio45"; 3363 function = "qup13"; 3364 }; 3365 3366 qup_i2c12_data_clk: qup-i2c12-data-clk { 3367 pins = "gpio48", "gpio49"; 3368 function = "qup14"; 3369 }; 3370 3371 qup_i2c13_data_clk: qup-i2c13-data-clk { 3372 pins = "gpio52", "gpio53"; 3373 function = "qup15"; 3374 }; 3375 3376 qup_i2c14_data_clk: qup-i2c14-data-clk { 3377 pins = "gpio56", "gpio57"; 3378 function = "qup16"; 3379 }; 3380 3381 qup_i2c15_data_clk: qup-i2c15-data-clk { 3382 pins = "gpio60", "gpio61"; 3383 function = "qup17"; 3384 }; 3385 3386 qup_spi0_data_clk: qup-spi0-data-clk { 3387 pins = "gpio0", "gpio1", "gpio2"; 3388 function = "qup00"; 3389 }; 3390 3391 qup_spi0_cs: qup-spi0-cs { 3392 pins = "gpio3"; 3393 function = "qup00"; 3394 }; 3395 3396 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3397 pins = "gpio3"; 3398 function = "gpio"; 3399 }; 3400 3401 qup_spi1_data_clk: qup-spi1-data-clk { 3402 pins = "gpio4", "gpio5", "gpio6"; 3403 function = "qup01"; 3404 }; 3405 3406 qup_spi1_cs: qup-spi1-cs { 3407 pins = "gpio7"; 3408 function = "qup01"; 3409 }; 3410 3411 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3412 pins = "gpio7"; 3413 function = "gpio"; 3414 }; 3415 3416 qup_spi2_data_clk: qup-spi2-data-clk { 3417 pins = "gpio8", "gpio9", "gpio10"; 3418 function = "qup02"; 3419 }; 3420 3421 qup_spi2_cs: qup-spi2-cs { 3422 pins = "gpio11"; 3423 function = "qup02"; 3424 }; 3425 3426 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3427 pins = "gpio11"; 3428 function = "gpio"; 3429 }; 3430 3431 qup_spi3_data_clk: qup-spi3-data-clk { 3432 pins = "gpio12", "gpio13", "gpio14"; 3433 function = "qup03"; 3434 }; 3435 3436 qup_spi3_cs: qup-spi3-cs { 3437 pins = "gpio15"; 3438 function = "qup03"; 3439 }; 3440 3441 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3442 pins = "gpio15"; 3443 function = "gpio"; 3444 }; 3445 3446 qup_spi4_data_clk: qup-spi4-data-clk { 3447 pins = "gpio16", "gpio17", "gpio18"; 3448 function = "qup04"; 3449 }; 3450 3451 qup_spi4_cs: qup-spi4-cs { 3452 pins = "gpio19"; 3453 function = "qup04"; 3454 }; 3455 3456 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3457 pins = "gpio19"; 3458 function = "gpio"; 3459 }; 3460 3461 qup_spi5_data_clk: qup-spi5-data-clk { 3462 pins = "gpio20", "gpio21", "gpio22"; 3463 function = "qup05"; 3464 }; 3465 3466 qup_spi5_cs: qup-spi5-cs { 3467 pins = "gpio23"; 3468 function = "qup05"; 3469 }; 3470 3471 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3472 pins = "gpio23"; 3473 function = "gpio"; 3474 }; 3475 3476 qup_spi6_data_clk: qup-spi6-data-clk { 3477 pins = "gpio24", "gpio25", "gpio26"; 3478 function = "qup06"; 3479 }; 3480 3481 qup_spi6_cs: qup-spi6-cs { 3482 pins = "gpio27"; 3483 function = "qup06"; 3484 }; 3485 3486 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3487 pins = "gpio27"; 3488 function = "gpio"; 3489 }; 3490 3491 qup_spi7_data_clk: qup-spi7-data-clk { 3492 pins = "gpio28", "gpio29", "gpio30"; 3493 function = "qup07"; 3494 }; 3495 3496 qup_spi7_cs: qup-spi7-cs { 3497 pins = "gpio31"; 3498 function = "qup07"; 3499 }; 3500 3501 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3502 pins = "gpio31"; 3503 function = "gpio"; 3504 }; 3505 3506 qup_spi8_data_clk: qup-spi8-data-clk { 3507 pins = "gpio32", "gpio33", "gpio34"; 3508 function = "qup10"; 3509 }; 3510 3511 qup_spi8_cs: qup-spi8-cs { 3512 pins = "gpio35"; 3513 function = "qup10"; 3514 }; 3515 3516 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3517 pins = "gpio35"; 3518 function = "gpio"; 3519 }; 3520 3521 qup_spi9_data_clk: qup-spi9-data-clk { 3522 pins = "gpio36", "gpio37", "gpio38"; 3523 function = "qup11"; 3524 }; 3525 3526 qup_spi9_cs: qup-spi9-cs { 3527 pins = "gpio39"; 3528 function = "qup11"; 3529 }; 3530 3531 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3532 pins = "gpio39"; 3533 function = "gpio"; 3534 }; 3535 3536 qup_spi10_data_clk: qup-spi10-data-clk { 3537 pins = "gpio40", "gpio41", "gpio42"; 3538 function = "qup12"; 3539 }; 3540 3541 qup_spi10_cs: qup-spi10-cs { 3542 pins = "gpio43"; 3543 function = "qup12"; 3544 }; 3545 3546 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3547 pins = "gpio43"; 3548 function = "gpio"; 3549 }; 3550 3551 qup_spi11_data_clk: qup-spi11-data-clk { 3552 pins = "gpio44", "gpio45", "gpio46"; 3553 function = "qup13"; 3554 }; 3555 3556 qup_spi11_cs: qup-spi11-cs { 3557 pins = "gpio47"; 3558 function = "qup13"; 3559 }; 3560 3561 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3562 pins = "gpio47"; 3563 function = "gpio"; 3564 }; 3565 3566 qup_spi12_data_clk: qup-spi12-data-clk { 3567 pins = "gpio48", "gpio49", "gpio50"; 3568 function = "qup14"; 3569 }; 3570 3571 qup_spi12_cs: qup-spi12-cs { 3572 pins = "gpio51"; 3573 function = "qup14"; 3574 }; 3575 3576 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3577 pins = "gpio51"; 3578 function = "gpio"; 3579 }; 3580 3581 qup_spi13_data_clk: qup-spi13-data-clk { 3582 pins = "gpio52", "gpio53", "gpio54"; 3583 function = "qup15"; 3584 }; 3585 3586 qup_spi13_cs: qup-spi13-cs { 3587 pins = "gpio55"; 3588 function = "qup15"; 3589 }; 3590 3591 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3592 pins = "gpio55"; 3593 function = "gpio"; 3594 }; 3595 3596 qup_spi14_data_clk: qup-spi14-data-clk { 3597 pins = "gpio56", "gpio57", "gpio58"; 3598 function = "qup16"; 3599 }; 3600 3601 qup_spi14_cs: qup-spi14-cs { 3602 pins = "gpio59"; 3603 function = "qup16"; 3604 }; 3605 3606 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3607 pins = "gpio59"; 3608 function = "gpio"; 3609 }; 3610 3611 qup_spi15_data_clk: qup-spi15-data-clk { 3612 pins = "gpio60", "gpio61", "gpio62"; 3613 function = "qup17"; 3614 }; 3615 3616 qup_spi15_cs: qup-spi15-cs { 3617 pins = "gpio63"; 3618 function = "qup17"; 3619 }; 3620 3621 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3622 pins = "gpio63"; 3623 function = "gpio"; 3624 }; 3625 3626 qup_uart0_cts: qup-uart0-cts { 3627 pins = "gpio0"; 3628 function = "qup00"; 3629 }; 3630 3631 qup_uart0_rts: qup-uart0-rts { 3632 pins = "gpio1"; 3633 function = "qup00"; 3634 }; 3635 3636 qup_uart0_tx: qup-uart0-tx { 3637 pins = "gpio2"; 3638 function = "qup00"; 3639 }; 3640 3641 qup_uart0_rx: qup-uart0-rx { 3642 pins = "gpio3"; 3643 function = "qup00"; 3644 }; 3645 3646 qup_uart1_cts: qup-uart1-cts { 3647 pins = "gpio4"; 3648 function = "qup01"; 3649 }; 3650 3651 qup_uart1_rts: qup-uart1-rts { 3652 pins = "gpio5"; 3653 function = "qup01"; 3654 }; 3655 3656 qup_uart1_tx: qup-uart1-tx { 3657 pins = "gpio6"; 3658 function = "qup01"; 3659 }; 3660 3661 qup_uart1_rx: qup-uart1-rx { 3662 pins = "gpio7"; 3663 function = "qup01"; 3664 }; 3665 3666 qup_uart2_cts: qup-uart2-cts { 3667 pins = "gpio8"; 3668 function = "qup02"; 3669 }; 3670 3671 qup_uart2_rts: qup-uart2-rts { 3672 pins = "gpio9"; 3673 function = "qup02"; 3674 }; 3675 3676 qup_uart2_tx: qup-uart2-tx { 3677 pins = "gpio10"; 3678 function = "qup02"; 3679 }; 3680 3681 qup_uart2_rx: qup-uart2-rx { 3682 pins = "gpio11"; 3683 function = "qup02"; 3684 }; 3685 3686 qup_uart3_cts: qup-uart3-cts { 3687 pins = "gpio12"; 3688 function = "qup03"; 3689 }; 3690 3691 qup_uart3_rts: qup-uart3-rts { 3692 pins = "gpio13"; 3693 function = "qup03"; 3694 }; 3695 3696 qup_uart3_tx: qup-uart3-tx { 3697 pins = "gpio14"; 3698 function = "qup03"; 3699 }; 3700 3701 qup_uart3_rx: qup-uart3-rx { 3702 pins = "gpio15"; 3703 function = "qup03"; 3704 }; 3705 3706 qup_uart4_cts: qup-uart4-cts { 3707 pins = "gpio16"; 3708 function = "qup04"; 3709 }; 3710 3711 qup_uart4_rts: qup-uart4-rts { 3712 pins = "gpio17"; 3713 function = "qup04"; 3714 }; 3715 3716 qup_uart4_tx: qup-uart4-tx { 3717 pins = "gpio18"; 3718 function = "qup04"; 3719 }; 3720 3721 qup_uart4_rx: qup-uart4-rx { 3722 pins = "gpio19"; 3723 function = "qup04"; 3724 }; 3725 3726 qup_uart5_cts: qup-uart5-cts { 3727 pins = "gpio20"; 3728 function = "qup05"; 3729 }; 3730 3731 qup_uart5_rts: qup-uart5-rts { 3732 pins = "gpio21"; 3733 function = "qup05"; 3734 }; 3735 3736 qup_uart5_tx: qup-uart5-tx { 3737 pins = "gpio22"; 3738 function = "qup05"; 3739 }; 3740 3741 qup_uart5_rx: qup-uart5-rx { 3742 pins = "gpio23"; 3743 function = "qup05"; 3744 }; 3745 3746 qup_uart6_cts: qup-uart6-cts { 3747 pins = "gpio24"; 3748 function = "qup06"; 3749 }; 3750 3751 qup_uart6_rts: qup-uart6-rts { 3752 pins = "gpio25"; 3753 function = "qup06"; 3754 }; 3755 3756 qup_uart6_tx: qup-uart6-tx { 3757 pins = "gpio26"; 3758 function = "qup06"; 3759 }; 3760 3761 qup_uart6_rx: qup-uart6-rx { 3762 pins = "gpio27"; 3763 function = "qup06"; 3764 }; 3765 3766 qup_uart7_cts: qup-uart7-cts { 3767 pins = "gpio28"; 3768 function = "qup07"; 3769 }; 3770 3771 qup_uart7_rts: qup-uart7-rts { 3772 pins = "gpio29"; 3773 function = "qup07"; 3774 }; 3775 3776 qup_uart7_tx: qup-uart7-tx { 3777 pins = "gpio30"; 3778 function = "qup07"; 3779 }; 3780 3781 qup_uart7_rx: qup-uart7-rx { 3782 pins = "gpio31"; 3783 function = "qup07"; 3784 }; 3785 3786 sdc1_on: sdc1-on { 3787 clk { 3788 pins = "sdc1_clk"; 3789 }; 3790 3791 cmd { 3792 pins = "sdc1_cmd"; 3793 }; 3794 3795 data { 3796 pins = "sdc1_data"; 3797 }; 3798 3799 rclk { 3800 pins = "sdc1_rclk"; 3801 }; 3802 }; 3803 3804 sdc1_off: sdc1-off { 3805 clk { 3806 pins = "sdc1_clk"; 3807 drive-strength = <2>; 3808 bias-bus-hold; 3809 }; 3810 3811 cmd { 3812 pins = "sdc1_cmd"; 3813 drive-strength = <2>; 3814 bias-bus-hold; 3815 }; 3816 3817 data { 3818 pins = "sdc1_data"; 3819 drive-strength = <2>; 3820 bias-bus-hold; 3821 }; 3822 3823 rclk { 3824 pins = "sdc1_rclk"; 3825 bias-bus-hold; 3826 }; 3827 }; 3828 3829 sdc2_on: sdc2-on { 3830 clk { 3831 pins = "sdc2_clk"; 3832 }; 3833 3834 cmd { 3835 pins = "sdc2_cmd"; 3836 }; 3837 3838 data { 3839 pins = "sdc2_data"; 3840 }; 3841 }; 3842 3843 sdc2_off: sdc2-off { 3844 clk { 3845 pins = "sdc2_clk"; 3846 drive-strength = <2>; 3847 bias-bus-hold; 3848 }; 3849 3850 cmd { 3851 pins ="sdc2_cmd"; 3852 drive-strength = <2>; 3853 bias-bus-hold; 3854 }; 3855 3856 data { 3857 pins ="sdc2_data"; 3858 drive-strength = <2>; 3859 bias-bus-hold; 3860 }; 3861 }; 3862 3863 qup_uart8_cts: qup-uart8-cts { 3864 pins = "gpio32"; 3865 function = "qup10"; 3866 }; 3867 3868 qup_uart8_rts: qup-uart8-rts { 3869 pins = "gpio33"; 3870 function = "qup10"; 3871 }; 3872 3873 qup_uart8_tx: qup-uart8-tx { 3874 pins = "gpio34"; 3875 function = "qup10"; 3876 }; 3877 3878 qup_uart8_rx: qup-uart8-rx { 3879 pins = "gpio35"; 3880 function = "qup10"; 3881 }; 3882 3883 qup_uart9_cts: qup-uart9-cts { 3884 pins = "gpio36"; 3885 function = "qup11"; 3886 }; 3887 3888 qup_uart9_rts: qup-uart9-rts { 3889 pins = "gpio37"; 3890 function = "qup11"; 3891 }; 3892 3893 qup_uart9_tx: qup-uart9-tx { 3894 pins = "gpio38"; 3895 function = "qup11"; 3896 }; 3897 3898 qup_uart9_rx: qup-uart9-rx { 3899 pins = "gpio39"; 3900 function = "qup11"; 3901 }; 3902 3903 qup_uart10_cts: qup-uart10-cts { 3904 pins = "gpio40"; 3905 function = "qup12"; 3906 }; 3907 3908 qup_uart10_rts: qup-uart10-rts { 3909 pins = "gpio41"; 3910 function = "qup12"; 3911 }; 3912 3913 qup_uart10_tx: qup-uart10-tx { 3914 pins = "gpio42"; 3915 function = "qup12"; 3916 }; 3917 3918 qup_uart10_rx: qup-uart10-rx { 3919 pins = "gpio43"; 3920 function = "qup12"; 3921 }; 3922 3923 qup_uart11_cts: qup-uart11-cts { 3924 pins = "gpio44"; 3925 function = "qup13"; 3926 }; 3927 3928 qup_uart11_rts: qup-uart11-rts { 3929 pins = "gpio45"; 3930 function = "qup13"; 3931 }; 3932 3933 qup_uart11_tx: qup-uart11-tx { 3934 pins = "gpio46"; 3935 function = "qup13"; 3936 }; 3937 3938 qup_uart11_rx: qup-uart11-rx { 3939 pins = "gpio47"; 3940 function = "qup13"; 3941 }; 3942 3943 qup_uart12_cts: qup-uart12-cts { 3944 pins = "gpio48"; 3945 function = "qup14"; 3946 }; 3947 3948 qup_uart12_rts: qup-uart12-rts { 3949 pins = "gpio49"; 3950 function = "qup14"; 3951 }; 3952 3953 qup_uart12_tx: qup-uart12-tx { 3954 pins = "gpio50"; 3955 function = "qup14"; 3956 }; 3957 3958 qup_uart12_rx: qup-uart12-rx { 3959 pins = "gpio51"; 3960 function = "qup14"; 3961 }; 3962 3963 qup_uart13_cts: qup-uart13-cts { 3964 pins = "gpio52"; 3965 function = "qup15"; 3966 }; 3967 3968 qup_uart13_rts: qup-uart13-rts { 3969 pins = "gpio53"; 3970 function = "qup15"; 3971 }; 3972 3973 qup_uart13_tx: qup-uart13-tx { 3974 pins = "gpio54"; 3975 function = "qup15"; 3976 }; 3977 3978 qup_uart13_rx: qup-uart13-rx { 3979 pins = "gpio55"; 3980 function = "qup15"; 3981 }; 3982 3983 qup_uart14_cts: qup-uart14-cts { 3984 pins = "gpio56"; 3985 function = "qup16"; 3986 }; 3987 3988 qup_uart14_rts: qup-uart14-rts { 3989 pins = "gpio57"; 3990 function = "qup16"; 3991 }; 3992 3993 qup_uart14_tx: qup-uart14-tx { 3994 pins = "gpio58"; 3995 function = "qup16"; 3996 }; 3997 3998 qup_uart14_rx: qup-uart14-rx { 3999 pins = "gpio59"; 4000 function = "qup16"; 4001 }; 4002 4003 qup_uart15_cts: qup-uart15-cts { 4004 pins = "gpio60"; 4005 function = "qup17"; 4006 }; 4007 4008 qup_uart15_rts: qup-uart15-rts { 4009 pins = "gpio61"; 4010 function = "qup17"; 4011 }; 4012 4013 qup_uart15_tx: qup-uart15-tx { 4014 pins = "gpio62"; 4015 function = "qup17"; 4016 }; 4017 4018 qup_uart15_rx: qup-uart15-rx { 4019 pins = "gpio63"; 4020 function = "qup17"; 4021 }; 4022 }; 4023 4024 imem@146a5000 { 4025 compatible = "qcom,sc7280-imem", "syscon"; 4026 reg = <0 0x146a5000 0 0x6000>; 4027 4028 #address-cells = <1>; 4029 #size-cells = <1>; 4030 4031 ranges = <0 0 0x146a5000 0x6000>; 4032 4033 pil-reloc@594c { 4034 compatible = "qcom,pil-reloc-info"; 4035 reg = <0x594c 0xc8>; 4036 }; 4037 }; 4038 4039 apps_smmu: iommu@15000000 { 4040 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4041 reg = <0 0x15000000 0 0x100000>; 4042 #iommu-cells = <2>; 4043 #global-interrupts = <1>; 4044 dma-coherent; 4045 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4126 }; 4127 4128 intc: interrupt-controller@17a00000 { 4129 compatible = "arm,gic-v3"; 4130 #address-cells = <2>; 4131 #size-cells = <2>; 4132 ranges; 4133 #interrupt-cells = <3>; 4134 interrupt-controller; 4135 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4136 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4138 4139 gic-its@17a40000 { 4140 compatible = "arm,gic-v3-its"; 4141 msi-controller; 4142 #msi-cells = <1>; 4143 reg = <0 0x17a40000 0 0x20000>; 4144 status = "disabled"; 4145 }; 4146 }; 4147 4148 watchdog@17c10000 { 4149 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4150 reg = <0 0x17c10000 0 0x1000>; 4151 clocks = <&sleep_clk>; 4152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4153 }; 4154 4155 timer@17c20000 { 4156 #address-cells = <2>; 4157 #size-cells = <2>; 4158 ranges; 4159 compatible = "arm,armv7-timer-mem"; 4160 reg = <0 0x17c20000 0 0x1000>; 4161 4162 frame@17c21000 { 4163 frame-number = <0>; 4164 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4166 reg = <0 0x17c21000 0 0x1000>, 4167 <0 0x17c22000 0 0x1000>; 4168 }; 4169 4170 frame@17c23000 { 4171 frame-number = <1>; 4172 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4173 reg = <0 0x17c23000 0 0x1000>; 4174 status = "disabled"; 4175 }; 4176 4177 frame@17c25000 { 4178 frame-number = <2>; 4179 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4180 reg = <0 0x17c25000 0 0x1000>; 4181 status = "disabled"; 4182 }; 4183 4184 frame@17c27000 { 4185 frame-number = <3>; 4186 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4187 reg = <0 0x17c27000 0 0x1000>; 4188 status = "disabled"; 4189 }; 4190 4191 frame@17c29000 { 4192 frame-number = <4>; 4193 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4194 reg = <0 0x17c29000 0 0x1000>; 4195 status = "disabled"; 4196 }; 4197 4198 frame@17c2b000 { 4199 frame-number = <5>; 4200 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4201 reg = <0 0x17c2b000 0 0x1000>; 4202 status = "disabled"; 4203 }; 4204 4205 frame@17c2d000 { 4206 frame-number = <6>; 4207 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4208 reg = <0 0x17c2d000 0 0x1000>; 4209 status = "disabled"; 4210 }; 4211 }; 4212 4213 apps_rsc: rsc@18200000 { 4214 compatible = "qcom,rpmh-rsc"; 4215 reg = <0 0x18200000 0 0x10000>, 4216 <0 0x18210000 0 0x10000>, 4217 <0 0x18220000 0 0x10000>; 4218 reg-names = "drv-0", "drv-1", "drv-2"; 4219 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4222 qcom,tcs-offset = <0xd00>; 4223 qcom,drv-id = <2>; 4224 qcom,tcs-config = <ACTIVE_TCS 2>, 4225 <SLEEP_TCS 3>, 4226 <WAKE_TCS 3>, 4227 <CONTROL_TCS 1>; 4228 4229 apps_bcm_voter: bcm-voter { 4230 compatible = "qcom,bcm-voter"; 4231 }; 4232 4233 rpmhpd: power-controller { 4234 compatible = "qcom,sc7280-rpmhpd"; 4235 #power-domain-cells = <1>; 4236 operating-points-v2 = <&rpmhpd_opp_table>; 4237 4238 rpmhpd_opp_table: opp-table { 4239 compatible = "operating-points-v2"; 4240 4241 rpmhpd_opp_ret: opp1 { 4242 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4243 }; 4244 4245 rpmhpd_opp_low_svs: opp2 { 4246 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4247 }; 4248 4249 rpmhpd_opp_svs: opp3 { 4250 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4251 }; 4252 4253 rpmhpd_opp_svs_l1: opp4 { 4254 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4255 }; 4256 4257 rpmhpd_opp_svs_l2: opp5 { 4258 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4259 }; 4260 4261 rpmhpd_opp_nom: opp6 { 4262 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4263 }; 4264 4265 rpmhpd_opp_nom_l1: opp7 { 4266 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4267 }; 4268 4269 rpmhpd_opp_turbo: opp8 { 4270 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4271 }; 4272 4273 rpmhpd_opp_turbo_l1: opp9 { 4274 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4275 }; 4276 }; 4277 }; 4278 4279 rpmhcc: clock-controller { 4280 compatible = "qcom,sc7280-rpmh-clk"; 4281 clocks = <&xo_board>; 4282 clock-names = "xo"; 4283 #clock-cells = <1>; 4284 }; 4285 }; 4286 4287 cpufreq_hw: cpufreq@18591000 { 4288 compatible = "qcom,cpufreq-epss"; 4289 reg = <0 0x18591000 0 0x1000>, 4290 <0 0x18592000 0 0x1000>, 4291 <0 0x18593000 0 0x1000>; 4292 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4293 clock-names = "xo", "alternate"; 4294 #freq-domain-cells = <1>; 4295 }; 4296 }; 4297 4298 thermal_zones: thermal-zones { 4299 cpu0-thermal { 4300 polling-delay-passive = <250>; 4301 polling-delay = <0>; 4302 4303 thermal-sensors = <&tsens0 1>; 4304 4305 trips { 4306 cpu0_alert0: trip-point0 { 4307 temperature = <90000>; 4308 hysteresis = <2000>; 4309 type = "passive"; 4310 }; 4311 4312 cpu0_alert1: trip-point1 { 4313 temperature = <95000>; 4314 hysteresis = <2000>; 4315 type = "passive"; 4316 }; 4317 4318 cpu0_crit: cpu-crit { 4319 temperature = <110000>; 4320 hysteresis = <0>; 4321 type = "critical"; 4322 }; 4323 }; 4324 4325 cooling-maps { 4326 map0 { 4327 trip = <&cpu0_alert0>; 4328 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4331 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4332 }; 4333 map1 { 4334 trip = <&cpu0_alert1>; 4335 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4338 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4339 }; 4340 }; 4341 }; 4342 4343 cpu1-thermal { 4344 polling-delay-passive = <250>; 4345 polling-delay = <0>; 4346 4347 thermal-sensors = <&tsens0 2>; 4348 4349 trips { 4350 cpu1_alert0: trip-point0 { 4351 temperature = <90000>; 4352 hysteresis = <2000>; 4353 type = "passive"; 4354 }; 4355 4356 cpu1_alert1: trip-point1 { 4357 temperature = <95000>; 4358 hysteresis = <2000>; 4359 type = "passive"; 4360 }; 4361 4362 cpu1_crit: cpu-crit { 4363 temperature = <110000>; 4364 hysteresis = <0>; 4365 type = "critical"; 4366 }; 4367 }; 4368 4369 cooling-maps { 4370 map0 { 4371 trip = <&cpu1_alert0>; 4372 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4375 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4376 }; 4377 map1 { 4378 trip = <&cpu1_alert1>; 4379 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4382 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4383 }; 4384 }; 4385 }; 4386 4387 cpu2-thermal { 4388 polling-delay-passive = <250>; 4389 polling-delay = <0>; 4390 4391 thermal-sensors = <&tsens0 3>; 4392 4393 trips { 4394 cpu2_alert0: trip-point0 { 4395 temperature = <90000>; 4396 hysteresis = <2000>; 4397 type = "passive"; 4398 }; 4399 4400 cpu2_alert1: trip-point1 { 4401 temperature = <95000>; 4402 hysteresis = <2000>; 4403 type = "passive"; 4404 }; 4405 4406 cpu2_crit: cpu-crit { 4407 temperature = <110000>; 4408 hysteresis = <0>; 4409 type = "critical"; 4410 }; 4411 }; 4412 4413 cooling-maps { 4414 map0 { 4415 trip = <&cpu2_alert0>; 4416 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4419 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4420 }; 4421 map1 { 4422 trip = <&cpu2_alert1>; 4423 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4426 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4427 }; 4428 }; 4429 }; 4430 4431 cpu3-thermal { 4432 polling-delay-passive = <250>; 4433 polling-delay = <0>; 4434 4435 thermal-sensors = <&tsens0 4>; 4436 4437 trips { 4438 cpu3_alert0: trip-point0 { 4439 temperature = <90000>; 4440 hysteresis = <2000>; 4441 type = "passive"; 4442 }; 4443 4444 cpu3_alert1: trip-point1 { 4445 temperature = <95000>; 4446 hysteresis = <2000>; 4447 type = "passive"; 4448 }; 4449 4450 cpu3_crit: cpu-crit { 4451 temperature = <110000>; 4452 hysteresis = <0>; 4453 type = "critical"; 4454 }; 4455 }; 4456 4457 cooling-maps { 4458 map0 { 4459 trip = <&cpu3_alert0>; 4460 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4464 }; 4465 map1 { 4466 trip = <&cpu3_alert1>; 4467 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4470 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4471 }; 4472 }; 4473 }; 4474 4475 cpu4-thermal { 4476 polling-delay-passive = <250>; 4477 polling-delay = <0>; 4478 4479 thermal-sensors = <&tsens0 7>; 4480 4481 trips { 4482 cpu4_alert0: trip-point0 { 4483 temperature = <90000>; 4484 hysteresis = <2000>; 4485 type = "passive"; 4486 }; 4487 4488 cpu4_alert1: trip-point1 { 4489 temperature = <95000>; 4490 hysteresis = <2000>; 4491 type = "passive"; 4492 }; 4493 4494 cpu4_crit: cpu-crit { 4495 temperature = <110000>; 4496 hysteresis = <0>; 4497 type = "critical"; 4498 }; 4499 }; 4500 4501 cooling-maps { 4502 map0 { 4503 trip = <&cpu4_alert0>; 4504 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4508 }; 4509 map1 { 4510 trip = <&cpu4_alert1>; 4511 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4514 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4515 }; 4516 }; 4517 }; 4518 4519 cpu5-thermal { 4520 polling-delay-passive = <250>; 4521 polling-delay = <0>; 4522 4523 thermal-sensors = <&tsens0 8>; 4524 4525 trips { 4526 cpu5_alert0: trip-point0 { 4527 temperature = <90000>; 4528 hysteresis = <2000>; 4529 type = "passive"; 4530 }; 4531 4532 cpu5_alert1: trip-point1 { 4533 temperature = <95000>; 4534 hysteresis = <2000>; 4535 type = "passive"; 4536 }; 4537 4538 cpu5_crit: cpu-crit { 4539 temperature = <110000>; 4540 hysteresis = <0>; 4541 type = "critical"; 4542 }; 4543 }; 4544 4545 cooling-maps { 4546 map0 { 4547 trip = <&cpu5_alert0>; 4548 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4552 }; 4553 map1 { 4554 trip = <&cpu5_alert1>; 4555 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4558 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4559 }; 4560 }; 4561 }; 4562 4563 cpu6-thermal { 4564 polling-delay-passive = <250>; 4565 polling-delay = <0>; 4566 4567 thermal-sensors = <&tsens0 9>; 4568 4569 trips { 4570 cpu6_alert0: trip-point0 { 4571 temperature = <90000>; 4572 hysteresis = <2000>; 4573 type = "passive"; 4574 }; 4575 4576 cpu6_alert1: trip-point1 { 4577 temperature = <95000>; 4578 hysteresis = <2000>; 4579 type = "passive"; 4580 }; 4581 4582 cpu6_crit: cpu-crit { 4583 temperature = <110000>; 4584 hysteresis = <0>; 4585 type = "critical"; 4586 }; 4587 }; 4588 4589 cooling-maps { 4590 map0 { 4591 trip = <&cpu6_alert0>; 4592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4596 }; 4597 map1 { 4598 trip = <&cpu6_alert1>; 4599 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4601 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4602 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4603 }; 4604 }; 4605 }; 4606 4607 cpu7-thermal { 4608 polling-delay-passive = <250>; 4609 polling-delay = <0>; 4610 4611 thermal-sensors = <&tsens0 10>; 4612 4613 trips { 4614 cpu7_alert0: trip-point0 { 4615 temperature = <90000>; 4616 hysteresis = <2000>; 4617 type = "passive"; 4618 }; 4619 4620 cpu7_alert1: trip-point1 { 4621 temperature = <95000>; 4622 hysteresis = <2000>; 4623 type = "passive"; 4624 }; 4625 4626 cpu7_crit: cpu-crit { 4627 temperature = <110000>; 4628 hysteresis = <0>; 4629 type = "critical"; 4630 }; 4631 }; 4632 4633 cooling-maps { 4634 map0 { 4635 trip = <&cpu7_alert0>; 4636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4640 }; 4641 map1 { 4642 trip = <&cpu7_alert1>; 4643 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4645 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4646 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4647 }; 4648 }; 4649 }; 4650 4651 cpu8-thermal { 4652 polling-delay-passive = <250>; 4653 polling-delay = <0>; 4654 4655 thermal-sensors = <&tsens0 11>; 4656 4657 trips { 4658 cpu8_alert0: trip-point0 { 4659 temperature = <90000>; 4660 hysteresis = <2000>; 4661 type = "passive"; 4662 }; 4663 4664 cpu8_alert1: trip-point1 { 4665 temperature = <95000>; 4666 hysteresis = <2000>; 4667 type = "passive"; 4668 }; 4669 4670 cpu8_crit: cpu-crit { 4671 temperature = <110000>; 4672 hysteresis = <0>; 4673 type = "critical"; 4674 }; 4675 }; 4676 4677 cooling-maps { 4678 map0 { 4679 trip = <&cpu8_alert0>; 4680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4684 }; 4685 map1 { 4686 trip = <&cpu8_alert1>; 4687 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4688 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4689 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4690 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4691 }; 4692 }; 4693 }; 4694 4695 cpu9-thermal { 4696 polling-delay-passive = <250>; 4697 polling-delay = <0>; 4698 4699 thermal-sensors = <&tsens0 12>; 4700 4701 trips { 4702 cpu9_alert0: trip-point0 { 4703 temperature = <90000>; 4704 hysteresis = <2000>; 4705 type = "passive"; 4706 }; 4707 4708 cpu9_alert1: trip-point1 { 4709 temperature = <95000>; 4710 hysteresis = <2000>; 4711 type = "passive"; 4712 }; 4713 4714 cpu9_crit: cpu-crit { 4715 temperature = <110000>; 4716 hysteresis = <0>; 4717 type = "critical"; 4718 }; 4719 }; 4720 4721 cooling-maps { 4722 map0 { 4723 trip = <&cpu9_alert0>; 4724 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4728 }; 4729 map1 { 4730 trip = <&cpu9_alert1>; 4731 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4734 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4735 }; 4736 }; 4737 }; 4738 4739 cpu10-thermal { 4740 polling-delay-passive = <250>; 4741 polling-delay = <0>; 4742 4743 thermal-sensors = <&tsens0 13>; 4744 4745 trips { 4746 cpu10_alert0: trip-point0 { 4747 temperature = <90000>; 4748 hysteresis = <2000>; 4749 type = "passive"; 4750 }; 4751 4752 cpu10_alert1: trip-point1 { 4753 temperature = <95000>; 4754 hysteresis = <2000>; 4755 type = "passive"; 4756 }; 4757 4758 cpu10_crit: cpu-crit { 4759 temperature = <110000>; 4760 hysteresis = <0>; 4761 type = "critical"; 4762 }; 4763 }; 4764 4765 cooling-maps { 4766 map0 { 4767 trip = <&cpu10_alert0>; 4768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4772 }; 4773 map1 { 4774 trip = <&cpu10_alert1>; 4775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4778 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4779 }; 4780 }; 4781 }; 4782 4783 cpu11-thermal { 4784 polling-delay-passive = <250>; 4785 polling-delay = <0>; 4786 4787 thermal-sensors = <&tsens0 14>; 4788 4789 trips { 4790 cpu11_alert0: trip-point0 { 4791 temperature = <90000>; 4792 hysteresis = <2000>; 4793 type = "passive"; 4794 }; 4795 4796 cpu11_alert1: trip-point1 { 4797 temperature = <95000>; 4798 hysteresis = <2000>; 4799 type = "passive"; 4800 }; 4801 4802 cpu11_crit: cpu-crit { 4803 temperature = <110000>; 4804 hysteresis = <0>; 4805 type = "critical"; 4806 }; 4807 }; 4808 4809 cooling-maps { 4810 map0 { 4811 trip = <&cpu11_alert0>; 4812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4816 }; 4817 map1 { 4818 trip = <&cpu11_alert1>; 4819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4823 }; 4824 }; 4825 }; 4826 4827 aoss0-thermal { 4828 polling-delay-passive = <0>; 4829 polling-delay = <0>; 4830 4831 thermal-sensors = <&tsens0 0>; 4832 4833 trips { 4834 aoss0_alert0: trip-point0 { 4835 temperature = <90000>; 4836 hysteresis = <2000>; 4837 type = "hot"; 4838 }; 4839 4840 aoss0_crit: aoss0-crit { 4841 temperature = <110000>; 4842 hysteresis = <0>; 4843 type = "critical"; 4844 }; 4845 }; 4846 }; 4847 4848 aoss1-thermal { 4849 polling-delay-passive = <0>; 4850 polling-delay = <0>; 4851 4852 thermal-sensors = <&tsens1 0>; 4853 4854 trips { 4855 aoss1_alert0: trip-point0 { 4856 temperature = <90000>; 4857 hysteresis = <2000>; 4858 type = "hot"; 4859 }; 4860 4861 aoss1_crit: aoss1-crit { 4862 temperature = <110000>; 4863 hysteresis = <0>; 4864 type = "critical"; 4865 }; 4866 }; 4867 }; 4868 4869 cpuss0-thermal { 4870 polling-delay-passive = <0>; 4871 polling-delay = <0>; 4872 4873 thermal-sensors = <&tsens0 5>; 4874 4875 trips { 4876 cpuss0_alert0: trip-point0 { 4877 temperature = <90000>; 4878 hysteresis = <2000>; 4879 type = "hot"; 4880 }; 4881 cpuss0_crit: cluster0-crit { 4882 temperature = <110000>; 4883 hysteresis = <0>; 4884 type = "critical"; 4885 }; 4886 }; 4887 }; 4888 4889 cpuss1-thermal { 4890 polling-delay-passive = <0>; 4891 polling-delay = <0>; 4892 4893 thermal-sensors = <&tsens0 6>; 4894 4895 trips { 4896 cpuss1_alert0: trip-point0 { 4897 temperature = <90000>; 4898 hysteresis = <2000>; 4899 type = "hot"; 4900 }; 4901 cpuss1_crit: cluster0-crit { 4902 temperature = <110000>; 4903 hysteresis = <0>; 4904 type = "critical"; 4905 }; 4906 }; 4907 }; 4908 4909 gpuss0-thermal { 4910 polling-delay-passive = <100>; 4911 polling-delay = <0>; 4912 4913 thermal-sensors = <&tsens1 1>; 4914 4915 trips { 4916 gpuss0_alert0: trip-point0 { 4917 temperature = <95000>; 4918 hysteresis = <2000>; 4919 type = "passive"; 4920 }; 4921 4922 gpuss0_crit: gpuss0-crit { 4923 temperature = <110000>; 4924 hysteresis = <0>; 4925 type = "critical"; 4926 }; 4927 }; 4928 4929 cooling-maps { 4930 map0 { 4931 trip = <&gpuss0_alert0>; 4932 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4933 }; 4934 }; 4935 }; 4936 4937 gpuss1-thermal { 4938 polling-delay-passive = <100>; 4939 polling-delay = <0>; 4940 4941 thermal-sensors = <&tsens1 2>; 4942 4943 trips { 4944 gpuss1_alert0: trip-point0 { 4945 temperature = <95000>; 4946 hysteresis = <2000>; 4947 type = "passive"; 4948 }; 4949 4950 gpuss1_crit: gpuss1-crit { 4951 temperature = <110000>; 4952 hysteresis = <0>; 4953 type = "critical"; 4954 }; 4955 }; 4956 4957 cooling-maps { 4958 map0 { 4959 trip = <&gpuss1_alert0>; 4960 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4961 }; 4962 }; 4963 }; 4964 4965 nspss0-thermal { 4966 polling-delay-passive = <0>; 4967 polling-delay = <0>; 4968 4969 thermal-sensors = <&tsens1 3>; 4970 4971 trips { 4972 nspss0_alert0: trip-point0 { 4973 temperature = <90000>; 4974 hysteresis = <2000>; 4975 type = "hot"; 4976 }; 4977 4978 nspss0_crit: nspss0-crit { 4979 temperature = <110000>; 4980 hysteresis = <0>; 4981 type = "critical"; 4982 }; 4983 }; 4984 }; 4985 4986 nspss1-thermal { 4987 polling-delay-passive = <0>; 4988 polling-delay = <0>; 4989 4990 thermal-sensors = <&tsens1 4>; 4991 4992 trips { 4993 nspss1_alert0: trip-point0 { 4994 temperature = <90000>; 4995 hysteresis = <2000>; 4996 type = "hot"; 4997 }; 4998 4999 nspss1_crit: nspss1-crit { 5000 temperature = <110000>; 5001 hysteresis = <0>; 5002 type = "critical"; 5003 }; 5004 }; 5005 }; 5006 5007 video-thermal { 5008 polling-delay-passive = <0>; 5009 polling-delay = <0>; 5010 5011 thermal-sensors = <&tsens1 5>; 5012 5013 trips { 5014 video_alert0: trip-point0 { 5015 temperature = <90000>; 5016 hysteresis = <2000>; 5017 type = "hot"; 5018 }; 5019 5020 video_crit: video-crit { 5021 temperature = <110000>; 5022 hysteresis = <0>; 5023 type = "critical"; 5024 }; 5025 }; 5026 }; 5027 5028 ddr-thermal { 5029 polling-delay-passive = <0>; 5030 polling-delay = <0>; 5031 5032 thermal-sensors = <&tsens1 6>; 5033 5034 trips { 5035 ddr_alert0: trip-point0 { 5036 temperature = <90000>; 5037 hysteresis = <2000>; 5038 type = "hot"; 5039 }; 5040 5041 ddr_crit: ddr-crit { 5042 temperature = <110000>; 5043 hysteresis = <0>; 5044 type = "critical"; 5045 }; 5046 }; 5047 }; 5048 5049 mdmss0-thermal { 5050 polling-delay-passive = <0>; 5051 polling-delay = <0>; 5052 5053 thermal-sensors = <&tsens1 7>; 5054 5055 trips { 5056 mdmss0_alert0: trip-point0 { 5057 temperature = <90000>; 5058 hysteresis = <2000>; 5059 type = "hot"; 5060 }; 5061 5062 mdmss0_crit: mdmss0-crit { 5063 temperature = <110000>; 5064 hysteresis = <0>; 5065 type = "critical"; 5066 }; 5067 }; 5068 }; 5069 5070 mdmss1-thermal { 5071 polling-delay-passive = <0>; 5072 polling-delay = <0>; 5073 5074 thermal-sensors = <&tsens1 8>; 5075 5076 trips { 5077 mdmss1_alert0: trip-point0 { 5078 temperature = <90000>; 5079 hysteresis = <2000>; 5080 type = "hot"; 5081 }; 5082 5083 mdmss1_crit: mdmss1-crit { 5084 temperature = <110000>; 5085 hysteresis = <0>; 5086 type = "critical"; 5087 }; 5088 }; 5089 }; 5090 5091 mdmss2-thermal { 5092 polling-delay-passive = <0>; 5093 polling-delay = <0>; 5094 5095 thermal-sensors = <&tsens1 9>; 5096 5097 trips { 5098 mdmss2_alert0: trip-point0 { 5099 temperature = <90000>; 5100 hysteresis = <2000>; 5101 type = "hot"; 5102 }; 5103 5104 mdmss2_crit: mdmss2-crit { 5105 temperature = <110000>; 5106 hysteresis = <0>; 5107 type = "critical"; 5108 }; 5109 }; 5110 }; 5111 5112 mdmss3-thermal { 5113 polling-delay-passive = <0>; 5114 polling-delay = <0>; 5115 5116 thermal-sensors = <&tsens1 10>; 5117 5118 trips { 5119 mdmss3_alert0: trip-point0 { 5120 temperature = <90000>; 5121 hysteresis = <2000>; 5122 type = "hot"; 5123 }; 5124 5125 mdmss3_crit: mdmss3-crit { 5126 temperature = <110000>; 5127 hysteresis = <0>; 5128 type = "critical"; 5129 }; 5130 }; 5131 }; 5132 5133 camera0-thermal { 5134 polling-delay-passive = <0>; 5135 polling-delay = <0>; 5136 5137 thermal-sensors = <&tsens1 11>; 5138 5139 trips { 5140 camera0_alert0: trip-point0 { 5141 temperature = <90000>; 5142 hysteresis = <2000>; 5143 type = "hot"; 5144 }; 5145 5146 camera0_crit: camera0-crit { 5147 temperature = <110000>; 5148 hysteresis = <0>; 5149 type = "critical"; 5150 }; 5151 }; 5152 }; 5153 }; 5154 5155 timer { 5156 compatible = "arm,armv8-timer"; 5157 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5158 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5159 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5160 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5161 }; 5162}; 5163