1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 video_mem: memory@8b200000 { 133 reg = <0x0 0x8b200000 0x0 0x500000>; 134 no-map; 135 }; 136 137 ipa_fw_mem: memory@8b700000 { 138 reg = <0 0x8b700000 0 0x10000>; 139 no-map; 140 }; 141 142 rmtfs_mem: memory@9c900000 { 143 compatible = "qcom,rmtfs-mem"; 144 reg = <0x0 0x9c900000 0x0 0x280000>; 145 no-map; 146 147 qcom,client-id = <1>; 148 qcom,vmid = <15>; 149 }; 150 }; 151 152 cpus { 153 #address-cells = <2>; 154 #size-cells = <0>; 155 156 CPU0: cpu@0 { 157 device_type = "cpu"; 158 compatible = "arm,kryo"; 159 reg = <0x0 0x0>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 #cooling-cells = <2>; 167 L2_0: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 L3_0: l3-cache { 171 compatible = "cache"; 172 }; 173 }; 174 }; 175 176 CPU1: cpu@100 { 177 device_type = "cpu"; 178 compatible = "arm,kryo"; 179 reg = <0x0 0x100>; 180 enable-method = "psci"; 181 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 182 &LITTLE_CPU_SLEEP_1 183 &CLUSTER_SLEEP_0>; 184 next-level-cache = <&L2_100>; 185 qcom,freq-domain = <&cpufreq_hw 0>; 186 #cooling-cells = <2>; 187 L2_100: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU2: cpu@200 { 194 device_type = "cpu"; 195 compatible = "arm,kryo"; 196 reg = <0x0 0x200>; 197 enable-method = "psci"; 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 199 &LITTLE_CPU_SLEEP_1 200 &CLUSTER_SLEEP_0>; 201 next-level-cache = <&L2_200>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_200: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU3: cpu@300 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x300>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_300>; 219 qcom,freq-domain = <&cpufreq_hw 0>; 220 #cooling-cells = <2>; 221 L2_300: l2-cache { 222 compatible = "cache"; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU4: cpu@400 { 228 device_type = "cpu"; 229 compatible = "arm,kryo"; 230 reg = <0x0 0x400>; 231 enable-method = "psci"; 232 cpu-idle-states = <&BIG_CPU_SLEEP_0 233 &BIG_CPU_SLEEP_1 234 &CLUSTER_SLEEP_0>; 235 next-level-cache = <&L2_400>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 #cooling-cells = <2>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "arm,kryo"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 250 &BIG_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 next-level-cache = <&L2_500>; 253 qcom,freq-domain = <&cpufreq_hw 1>; 254 #cooling-cells = <2>; 255 L2_500: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU6: cpu@600 { 262 device_type = "cpu"; 263 compatible = "arm,kryo"; 264 reg = <0x0 0x600>; 265 enable-method = "psci"; 266 cpu-idle-states = <&BIG_CPU_SLEEP_0 267 &BIG_CPU_SLEEP_1 268 &CLUSTER_SLEEP_0>; 269 next-level-cache = <&L2_600>; 270 qcom,freq-domain = <&cpufreq_hw 1>; 271 #cooling-cells = <2>; 272 L2_600: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "arm,kryo"; 281 reg = <0x0 0x700>; 282 enable-method = "psci"; 283 cpu-idle-states = <&BIG_CPU_SLEEP_0 284 &BIG_CPU_SLEEP_1 285 &CLUSTER_SLEEP_0>; 286 next-level-cache = <&L2_700>; 287 qcom,freq-domain = <&cpufreq_hw 2>; 288 #cooling-cells = <2>; 289 L2_700: l2-cache { 290 compatible = "cache"; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "little-power-down"; 337 arm,psci-suspend-param = <0x40000003>; 338 entry-latency-us = <549>; 339 exit-latency-us = <901>; 340 min-residency-us = <1774>; 341 local-timer-stop; 342 }; 343 344 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "little-rail-power-down"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <915>; 350 min-residency-us = <4001>; 351 local-timer-stop; 352 }; 353 354 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 355 compatible = "arm,idle-state"; 356 idle-state-name = "big-power-down"; 357 arm,psci-suspend-param = <0x40000003>; 358 entry-latency-us = <523>; 359 exit-latency-us = <1244>; 360 min-residency-us = <2207>; 361 local-timer-stop; 362 }; 363 364 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 365 compatible = "arm,idle-state"; 366 idle-state-name = "big-rail-power-down"; 367 arm,psci-suspend-param = <0x40000004>; 368 entry-latency-us = <526>; 369 exit-latency-us = <1854>; 370 min-residency-us = <5555>; 371 local-timer-stop; 372 }; 373 374 CLUSTER_SLEEP_0: cluster-sleep-0 { 375 compatible = "arm,idle-state"; 376 idle-state-name = "cluster-power-down"; 377 arm,psci-suspend-param = <0x40003444>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9926>; 381 local-timer-stop; 382 }; 383 }; 384 }; 385 386 memory@80000000 { 387 device_type = "memory"; 388 /* We expect the bootloader to fill in the size */ 389 reg = <0 0x80000000 0 0>; 390 }; 391 392 firmware { 393 scm { 394 compatible = "qcom,scm-sc7280", "qcom,scm"; 395 }; 396 }; 397 398 clk_virt: interconnect { 399 compatible = "qcom,sc7280-clk-virt"; 400 #interconnect-cells = <2>; 401 qcom,bcm-voters = <&apps_bcm_voter>; 402 }; 403 404 smem { 405 compatible = "qcom,smem"; 406 memory-region = <&smem_mem>; 407 hwlocks = <&tcsr_mutex 3>; 408 }; 409 410 smp2p-adsp { 411 compatible = "qcom,smp2p"; 412 qcom,smem = <443>, <429>; 413 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 414 IPCC_MPROC_SIGNAL_SMP2P 415 IRQ_TYPE_EDGE_RISING>; 416 mboxes = <&ipcc IPCC_CLIENT_LPASS 417 IPCC_MPROC_SIGNAL_SMP2P>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <2>; 421 422 adsp_smp2p_out: master-kernel { 423 qcom,entry-name = "master-kernel"; 424 #qcom,smem-state-cells = <1>; 425 }; 426 427 adsp_smp2p_in: slave-kernel { 428 qcom,entry-name = "slave-kernel"; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 smp2p-cdsp { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <94>, <432>; 437 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 438 IPCC_MPROC_SIGNAL_SMP2P 439 IRQ_TYPE_EDGE_RISING>; 440 mboxes = <&ipcc IPCC_CLIENT_CDSP 441 IPCC_MPROC_SIGNAL_SMP2P>; 442 443 qcom,local-pid = <0>; 444 qcom,remote-pid = <5>; 445 446 cdsp_smp2p_out: master-kernel { 447 qcom,entry-name = "master-kernel"; 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 cdsp_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 smp2p-mpss { 459 compatible = "qcom,smp2p"; 460 qcom,smem = <435>, <428>; 461 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 462 IPCC_MPROC_SIGNAL_SMP2P 463 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&ipcc IPCC_CLIENT_MPSS 465 IPCC_MPROC_SIGNAL_SMP2P>; 466 467 qcom,local-pid = <0>; 468 qcom,remote-pid = <1>; 469 470 modem_smp2p_out: master-kernel { 471 qcom,entry-name = "master-kernel"; 472 #qcom,smem-state-cells = <1>; 473 }; 474 475 modem_smp2p_in: slave-kernel { 476 qcom,entry-name = "slave-kernel"; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 ipa_smp2p_out: ipa-ap-to-modem { 482 qcom,entry-name = "ipa"; 483 #qcom,smem-state-cells = <1>; 484 }; 485 486 ipa_smp2p_in: ipa-modem-to-ap { 487 qcom,entry-name = "ipa"; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 }; 492 493 smp2p-wpss { 494 compatible = "qcom,smp2p"; 495 qcom,smem = <617>, <616>; 496 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 497 IPCC_MPROC_SIGNAL_SMP2P 498 IRQ_TYPE_EDGE_RISING>; 499 mboxes = <&ipcc IPCC_CLIENT_WPSS 500 IPCC_MPROC_SIGNAL_SMP2P>; 501 502 qcom,local-pid = <0>; 503 qcom,remote-pid = <13>; 504 505 wpss_smp2p_out: master-kernel { 506 qcom,entry-name = "master-kernel"; 507 #qcom,smem-state-cells = <1>; 508 }; 509 510 wpss_smp2p_in: slave-kernel { 511 qcom,entry-name = "slave-kernel"; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 }; 516 517 pmu { 518 compatible = "arm,armv8-pmuv3"; 519 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 520 }; 521 522 psci { 523 compatible = "arm,psci-1.0"; 524 method = "smc"; 525 }; 526 527 qspi_opp_table: qspi-opp-table { 528 compatible = "operating-points-v2"; 529 530 opp-75000000 { 531 opp-hz = /bits/ 64 <75000000>; 532 required-opps = <&rpmhpd_opp_low_svs>; 533 }; 534 535 opp-150000000 { 536 opp-hz = /bits/ 64 <150000000>; 537 required-opps = <&rpmhpd_opp_svs>; 538 }; 539 540 opp-200000000 { 541 opp-hz = /bits/ 64 <200000000>; 542 required-opps = <&rpmhpd_opp_svs_l1>; 543 }; 544 545 opp-300000000 { 546 opp-hz = /bits/ 64 <300000000>; 547 required-opps = <&rpmhpd_opp_nom>; 548 }; 549 }; 550 551 qup_opp_table: qup-opp-table { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 564 opp-128000000 { 565 opp-hz = /bits/ 64 <128000000>; 566 required-opps = <&rpmhpd_opp_nom>; 567 }; 568 }; 569 570 soc: soc@0 { 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges = <0 0 0 0 0x10 0>; 574 dma-ranges = <0 0 0 0 0x10 0>; 575 compatible = "simple-bus"; 576 577 gcc: clock-controller@100000 { 578 compatible = "qcom,gcc-sc7280"; 579 reg = <0 0x00100000 0 0x1f0000>; 580 clocks = <&rpmhcc RPMH_CXO_CLK>, 581 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 582 <0>, <&pcie1_lane 0>, 583 <0>, <0>, <0>, <0>; 584 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 585 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 586 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 587 "ufs_phy_tx_symbol_0_clk", 588 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 589 #clock-cells = <1>; 590 #reset-cells = <1>; 591 #power-domain-cells = <1>; 592 }; 593 594 ipcc: mailbox@408000 { 595 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 596 reg = <0 0x00408000 0 0x1000>; 597 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-controller; 599 #interrupt-cells = <3>; 600 #mbox-cells = <2>; 601 }; 602 603 qfprom: efuse@784000 { 604 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 605 reg = <0 0x00784000 0 0xa20>, 606 <0 0x00780000 0 0xa20>, 607 <0 0x00782000 0 0x120>, 608 <0 0x00786000 0 0x1fff>; 609 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 610 clock-names = "core"; 611 power-domains = <&rpmhpd SC7280_MX>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 }; 615 616 sdhc_1: sdhci@7c4000 { 617 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 618 status = "disabled"; 619 620 reg = <0 0x007c4000 0 0x1000>, 621 <0 0x007c5000 0 0x1000>; 622 reg-names = "hc", "cqhci"; 623 624 iommus = <&apps_smmu 0xc0 0x0>; 625 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "hc_irq", "pwr_irq"; 628 629 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 630 <&gcc GCC_SDCC1_AHB_CLK>, 631 <&rpmhcc RPMH_CXO_CLK>; 632 clock-names = "core", "iface", "xo"; 633 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 635 interconnect-names = "sdhc-ddr","cpu-sdhc"; 636 power-domains = <&rpmhpd SC7280_CX>; 637 operating-points-v2 = <&sdhc1_opp_table>; 638 639 bus-width = <8>; 640 supports-cqe; 641 642 qcom,dll-config = <0x0007642c>; 643 qcom,ddr-config = <0x80040868>; 644 645 mmc-ddr-1_8v; 646 mmc-hs200-1_8v; 647 mmc-hs400-1_8v; 648 mmc-hs400-enhanced-strobe; 649 650 sdhc1_opp_table: opp-table { 651 compatible = "operating-points-v2"; 652 653 opp-100000000 { 654 opp-hz = /bits/ 64 <100000000>; 655 required-opps = <&rpmhpd_opp_low_svs>; 656 opp-peak-kBps = <1800000 400000>; 657 opp-avg-kBps = <100000 0>; 658 }; 659 660 opp-384000000 { 661 opp-hz = /bits/ 64 <384000000>; 662 required-opps = <&rpmhpd_opp_nom>; 663 opp-peak-kBps = <5400000 1600000>; 664 opp-avg-kBps = <390000 0>; 665 }; 666 }; 667 668 }; 669 670 qupv3_id_0: geniqup@9c0000 { 671 compatible = "qcom,geni-se-qup"; 672 reg = <0 0x009c0000 0 0x2000>; 673 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 674 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 675 clock-names = "m-ahb", "s-ahb"; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 ranges; 679 iommus = <&apps_smmu 0x123 0x0>; 680 status = "disabled"; 681 682 i2c0: i2c@980000 { 683 compatible = "qcom,geni-i2c"; 684 reg = <0 0x00980000 0 0x4000>; 685 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 686 clock-names = "se"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&qup_i2c0_data_clk>; 689 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 694 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 695 interconnect-names = "qup-core", "qup-config", 696 "qup-memory"; 697 status = "disabled"; 698 }; 699 700 spi0: spi@980000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0 0x00980000 0 0x4000>; 703 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 704 clock-names = "se"; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 707 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 power-domains = <&rpmhpd SC7280_CX>; 711 operating-points-v2 = <&qup_opp_table>; 712 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 714 interconnect-names = "qup-core", "qup-config"; 715 status = "disabled"; 716 }; 717 718 uart0: serial@980000 { 719 compatible = "qcom,geni-uart"; 720 reg = <0 0x00980000 0 0x4000>; 721 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 722 clock-names = "se"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 725 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 726 power-domains = <&rpmhpd SC7280_CX>; 727 operating-points-v2 = <&qup_opp_table>; 728 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 729 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 730 interconnect-names = "qup-core", "qup-config"; 731 status = "disabled"; 732 }; 733 734 i2c1: i2c@984000 { 735 compatible = "qcom,geni-i2c"; 736 reg = <0 0x00984000 0 0x4000>; 737 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 738 clock-names = "se"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&qup_i2c1_data_clk>; 741 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 745 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 746 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 747 interconnect-names = "qup-core", "qup-config", 748 "qup-memory"; 749 status = "disabled"; 750 }; 751 752 spi1: spi@984000 { 753 compatible = "qcom,geni-spi"; 754 reg = <0 0x00984000 0 0x4000>; 755 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 756 clock-names = "se"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 759 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 power-domains = <&rpmhpd SC7280_CX>; 763 operating-points-v2 = <&qup_opp_table>; 764 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 765 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 766 interconnect-names = "qup-core", "qup-config"; 767 status = "disabled"; 768 }; 769 770 uart1: serial@984000 { 771 compatible = "qcom,geni-uart"; 772 reg = <0 0x00984000 0 0x4000>; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 774 clock-names = "se"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 777 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 778 power-domains = <&rpmhpd SC7280_CX>; 779 operating-points-v2 = <&qup_opp_table>; 780 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 781 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 782 interconnect-names = "qup-core", "qup-config"; 783 status = "disabled"; 784 }; 785 786 i2c2: i2c@988000 { 787 compatible = "qcom,geni-i2c"; 788 reg = <0 0x00988000 0 0x4000>; 789 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 790 clock-names = "se"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&qup_i2c2_data_clk>; 793 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 798 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 799 interconnect-names = "qup-core", "qup-config", 800 "qup-memory"; 801 status = "disabled"; 802 }; 803 804 spi2: spi@988000 { 805 compatible = "qcom,geni-spi"; 806 reg = <0 0x00988000 0 0x4000>; 807 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 808 clock-names = "se"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 811 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 power-domains = <&rpmhpd SC7280_CX>; 815 operating-points-v2 = <&qup_opp_table>; 816 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 818 interconnect-names = "qup-core", "qup-config"; 819 status = "disabled"; 820 }; 821 822 uart2: serial@988000 { 823 compatible = "qcom,geni-uart"; 824 reg = <0 0x00988000 0 0x4000>; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 826 clock-names = "se"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 829 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd SC7280_CX>; 831 operating-points-v2 = <&qup_opp_table>; 832 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 833 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 834 interconnect-names = "qup-core", "qup-config"; 835 status = "disabled"; 836 }; 837 838 i2c3: i2c@98c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0098c000 0 0x4000>; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 842 clock-names = "se"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c3_data_clk>; 845 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 849 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 850 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 851 interconnect-names = "qup-core", "qup-config", 852 "qup-memory"; 853 status = "disabled"; 854 }; 855 856 spi3: spi@98c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0098c000 0 0x4000>; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 860 clock-names = "se"; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 863 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 power-domains = <&rpmhpd SC7280_CX>; 867 operating-points-v2 = <&qup_opp_table>; 868 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 870 interconnect-names = "qup-core", "qup-config"; 871 status = "disabled"; 872 }; 873 874 uart3: serial@98c000 { 875 compatible = "qcom,geni-uart"; 876 reg = <0 0x0098c000 0 0x4000>; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 878 clock-names = "se"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 881 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 882 power-domains = <&rpmhpd SC7280_CX>; 883 operating-points-v2 = <&qup_opp_table>; 884 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 886 interconnect-names = "qup-core", "qup-config"; 887 status = "disabled"; 888 }; 889 890 i2c4: i2c@990000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00990000 0 0x4000>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 894 clock-names = "se"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c4_data_clk>; 897 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 901 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 902 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 903 interconnect-names = "qup-core", "qup-config", 904 "qup-memory"; 905 status = "disabled"; 906 }; 907 908 spi4: spi@990000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0 0x00990000 0 0x4000>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 912 clock-names = "se"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 915 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 power-domains = <&rpmhpd SC7280_CX>; 919 operating-points-v2 = <&qup_opp_table>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 922 interconnect-names = "qup-core", "qup-config"; 923 status = "disabled"; 924 }; 925 926 uart4: serial@990000 { 927 compatible = "qcom,geni-uart"; 928 reg = <0 0x00990000 0 0x4000>; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 930 clock-names = "se"; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 933 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC7280_CX>; 935 operating-points-v2 = <&qup_opp_table>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 938 interconnect-names = "qup-core", "qup-config"; 939 status = "disabled"; 940 }; 941 942 i2c5: i2c@994000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0 0x00994000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 946 clock-names = "se"; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_i2c5_data_clk>; 949 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 953 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 954 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 955 interconnect-names = "qup-core", "qup-config", 956 "qup-memory"; 957 status = "disabled"; 958 }; 959 960 spi5: spi@994000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00994000 0 0x4000>; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 964 clock-names = "se"; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 967 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 power-domains = <&rpmhpd SC7280_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 uart5: serial@994000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00994000 0 0x4000>; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 982 clock-names = "se"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 985 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7280_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c6: i2c@998000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00998000 0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 998 clock-names = "se"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c6_data_clk>; 1001 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 status = "disabled"; 1010 }; 1011 1012 spi6: spi@998000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00998000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1016 clock-names = "se"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1019 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 power-domains = <&rpmhpd SC7280_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 uart6: serial@998000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0 0x00998000 0 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1034 clock-names = "se"; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1037 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1038 power-domains = <&rpmhpd SC7280_CX>; 1039 operating-points-v2 = <&qup_opp_table>; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1042 interconnect-names = "qup-core", "qup-config"; 1043 status = "disabled"; 1044 }; 1045 1046 i2c7: i2c@99c000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x0099c000 0 0x4000>; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1050 clock-names = "se"; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c7_data_clk>; 1053 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1057 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1058 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1059 interconnect-names = "qup-core", "qup-config", 1060 "qup-memory"; 1061 status = "disabled"; 1062 }; 1063 1064 spi7: spi@99c000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x0099c000 0 0x4000>; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1068 clock-names = "se"; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1071 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 power-domains = <&rpmhpd SC7280_CX>; 1075 operating-points-v2 = <&qup_opp_table>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 status = "disabled"; 1080 }; 1081 1082 uart7: serial@99c000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x0099c000 0 0x4000>; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1086 clock-names = "se"; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1089 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1090 power-domains = <&rpmhpd SC7280_CX>; 1091 operating-points-v2 = <&qup_opp_table>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 qupv3_id_1: geniqup@ac0000 { 1100 compatible = "qcom,geni-se-qup"; 1101 reg = <0 0x00ac0000 0 0x2000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1103 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1104 clock-names = "m-ahb", "s-ahb"; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 iommus = <&apps_smmu 0x43 0x0>; 1109 status = "disabled"; 1110 1111 i2c8: i2c@a80000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x00a80000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c8_data_clk>; 1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1123 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1124 interconnect-names = "qup-core", "qup-config", 1125 "qup-memory"; 1126 status = "disabled"; 1127 }; 1128 1129 spi8: spi@a80000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0 0x00a80000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1136 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 power-domains = <&rpmhpd SC7280_CX>; 1140 operating-points-v2 = <&qup_opp_table>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1143 interconnect-names = "qup-core", "qup-config"; 1144 status = "disabled"; 1145 }; 1146 1147 uart8: serial@a80000 { 1148 compatible = "qcom,geni-uart"; 1149 reg = <0 0x00a80000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1154 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC7280_CX>; 1156 operating-points-v2 = <&qup_opp_table>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1159 interconnect-names = "qup-core", "qup-config"; 1160 status = "disabled"; 1161 }; 1162 1163 i2c9: i2c@a84000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00a84000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1167 clock-names = "se"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c9_data_clk>; 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", 1177 "qup-memory"; 1178 status = "disabled"; 1179 }; 1180 1181 spi9: spi@a84000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00a84000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1188 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 power-domains = <&rpmhpd SC7280_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 uart9: serial@a84000 { 1200 compatible = "qcom,geni-uart"; 1201 reg = <0 0x00a84000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1203 clock-names = "se"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c10: i2c@a88000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00a88000 0 0x4000>; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1219 clock-names = "se"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_i2c10_data_clk>; 1222 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1227 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1228 interconnect-names = "qup-core", "qup-config", 1229 "qup-memory"; 1230 status = "disabled"; 1231 }; 1232 1233 spi10: spi@a88000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0 0x00a88000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1240 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 power-domains = <&rpmhpd SC7280_CX>; 1244 operating-points-v2 = <&qup_opp_table>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1247 interconnect-names = "qup-core", "qup-config"; 1248 status = "disabled"; 1249 }; 1250 1251 uart10: serial@a88000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0 0x00a88000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1258 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1259 power-domains = <&rpmhpd SC7280_CX>; 1260 operating-points-v2 = <&qup_opp_table>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1262 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1263 interconnect-names = "qup-core", "qup-config"; 1264 status = "disabled"; 1265 }; 1266 1267 i2c11: i2c@a8c000 { 1268 compatible = "qcom,geni-i2c"; 1269 reg = <0 0x00a8c000 0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1271 clock-names = "se"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_i2c11_data_clk>; 1274 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1279 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1280 interconnect-names = "qup-core", "qup-config", 1281 "qup-memory"; 1282 status = "disabled"; 1283 }; 1284 1285 spi11: spi@a8c000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00a8c000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1292 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 uart11: serial@a8c000 { 1304 compatible = "qcom,geni-uart"; 1305 reg = <0 0x00a8c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1310 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1311 power-domains = <&rpmhpd SC7280_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1315 interconnect-names = "qup-core", "qup-config"; 1316 status = "disabled"; 1317 }; 1318 1319 i2c12: i2c@a90000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0 0x00a90000 0 0x4000>; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1323 clock-names = "se"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_i2c12_data_clk>; 1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1331 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", 1333 "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 spi12: spi@a90000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0 0x00a90000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 power-domains = <&rpmhpd SC7280_CX>; 1348 operating-points-v2 = <&qup_opp_table>; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1350 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1351 interconnect-names = "qup-core", "qup-config"; 1352 status = "disabled"; 1353 }; 1354 1355 uart12: serial@a90000 { 1356 compatible = "qcom,geni-uart"; 1357 reg = <0 0x00a90000 0 0x4000>; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1359 clock-names = "se"; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1362 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1363 power-domains = <&rpmhpd SC7280_CX>; 1364 operating-points-v2 = <&qup_opp_table>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1367 interconnect-names = "qup-core", "qup-config"; 1368 status = "disabled"; 1369 }; 1370 1371 i2c13: i2c@a94000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00a94000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1375 clock-names = "se"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_i2c13_data_clk>; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1382 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1383 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1384 interconnect-names = "qup-core", "qup-config", 1385 "qup-memory"; 1386 status = "disabled"; 1387 }; 1388 1389 spi13: spi@a94000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a94000 0 0x4000>; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1393 clock-names = "se"; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1396 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 power-domains = <&rpmhpd SC7280_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 1407 uart13: serial@a94000 { 1408 compatible = "qcom,geni-uart"; 1409 reg = <0 0x00a94000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1414 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC7280_CX>; 1416 operating-points-v2 = <&qup_opp_table>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1419 interconnect-names = "qup-core", "qup-config"; 1420 status = "disabled"; 1421 }; 1422 1423 i2c14: i2c@a98000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x00a98000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1427 clock-names = "se"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_i2c14_data_clk>; 1430 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1435 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", 1437 "qup-memory"; 1438 status = "disabled"; 1439 }; 1440 1441 spi14: spi@a98000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a98000 0 0x4000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1445 clock-names = "se"; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1448 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&rpmhpd SC7280_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1455 interconnect-names = "qup-core", "qup-config"; 1456 status = "disabled"; 1457 }; 1458 1459 uart14: serial@a98000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00a98000 0 0x4000>; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1463 clock-names = "se"; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1466 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SC7280_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 status = "disabled"; 1473 }; 1474 1475 i2c15: i2c@a9c000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a9c000 0 0x4000>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1479 clock-names = "se"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c15_data_clk>; 1482 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", 1489 "qup-memory"; 1490 status = "disabled"; 1491 }; 1492 1493 spi15: spi@a9c000 { 1494 compatible = "qcom,geni-spi"; 1495 reg = <0 0x00a9c000 0 0x4000>; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1497 clock-names = "se"; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1500 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 status = "disabled"; 1509 }; 1510 1511 uart15: serial@a9c000 { 1512 compatible = "qcom,geni-uart"; 1513 reg = <0 0x00a9c000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1518 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC7280_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1523 interconnect-names = "qup-core", "qup-config"; 1524 status = "disabled"; 1525 }; 1526 }; 1527 1528 cnoc2: interconnect@1500000 { 1529 reg = <0 0x01500000 0 0x1000>; 1530 compatible = "qcom,sc7280-cnoc2"; 1531 #interconnect-cells = <2>; 1532 qcom,bcm-voters = <&apps_bcm_voter>; 1533 }; 1534 1535 cnoc3: interconnect@1502000 { 1536 reg = <0 0x01502000 0 0x1000>; 1537 compatible = "qcom,sc7280-cnoc3"; 1538 #interconnect-cells = <2>; 1539 qcom,bcm-voters = <&apps_bcm_voter>; 1540 }; 1541 1542 mc_virt: interconnect@1580000 { 1543 reg = <0 0x01580000 0 0x4>; 1544 compatible = "qcom,sc7280-mc-virt"; 1545 #interconnect-cells = <2>; 1546 qcom,bcm-voters = <&apps_bcm_voter>; 1547 }; 1548 1549 system_noc: interconnect@1680000 { 1550 reg = <0 0x01680000 0 0x15480>; 1551 compatible = "qcom,sc7280-system-noc"; 1552 #interconnect-cells = <2>; 1553 qcom,bcm-voters = <&apps_bcm_voter>; 1554 }; 1555 1556 aggre1_noc: interconnect@16e0000 { 1557 compatible = "qcom,sc7280-aggre1-noc"; 1558 reg = <0 0x016e0000 0 0x1c080>; 1559 #interconnect-cells = <2>; 1560 qcom,bcm-voters = <&apps_bcm_voter>; 1561 }; 1562 1563 aggre2_noc: interconnect@1700000 { 1564 reg = <0 0x01700000 0 0x2b080>; 1565 compatible = "qcom,sc7280-aggre2-noc"; 1566 #interconnect-cells = <2>; 1567 qcom,bcm-voters = <&apps_bcm_voter>; 1568 }; 1569 1570 mmss_noc: interconnect@1740000 { 1571 reg = <0 0x01740000 0 0x1e080>; 1572 compatible = "qcom,sc7280-mmss-noc"; 1573 #interconnect-cells = <2>; 1574 qcom,bcm-voters = <&apps_bcm_voter>; 1575 }; 1576 1577 pcie1: pci@1c08000 { 1578 compatible = "qcom,pcie-sc7280"; 1579 reg = <0 0x01c08000 0 0x3000>, 1580 <0 0x40000000 0 0xf1d>, 1581 <0 0x40000f20 0 0xa8>, 1582 <0 0x40001000 0 0x1000>, 1583 <0 0x40100000 0 0x100000>; 1584 1585 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1586 device_type = "pci"; 1587 linux,pci-domain = <1>; 1588 bus-range = <0x00 0xff>; 1589 num-lanes = <2>; 1590 1591 #address-cells = <3>; 1592 #size-cells = <2>; 1593 1594 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1595 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1596 1597 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1598 interrupt-names = "msi"; 1599 #interrupt-cells = <1>; 1600 interrupt-map-mask = <0 0 0 0x7>; 1601 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1602 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1604 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1605 1606 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1607 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1608 <&pcie1_lane 0>, 1609 <&rpmhcc RPMH_CXO_CLK>, 1610 <&gcc GCC_PCIE_1_AUX_CLK>, 1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1615 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1616 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1617 1618 clock-names = "pipe", 1619 "pipe_mux", 1620 "phy_pipe", 1621 "ref", 1622 "aux", 1623 "cfg", 1624 "bus_master", 1625 "bus_slave", 1626 "slave_q2a", 1627 "tbu", 1628 "ddrss_sf_tbu"; 1629 1630 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1631 assigned-clock-rates = <19200000>; 1632 1633 resets = <&gcc GCC_PCIE_1_BCR>; 1634 reset-names = "pci"; 1635 1636 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1637 1638 phys = <&pcie1_lane>; 1639 phy-names = "pciephy"; 1640 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&pcie1_clkreq_n>; 1643 1644 iommus = <&apps_smmu 0x1c80 0x1>; 1645 1646 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1647 <0x100 &apps_smmu 0x1c81 0x1>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x1c0>; 1655 #address-cells = <2>; 1656 #size-cells = <2>; 1657 ranges; 1658 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1659 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1660 <&gcc GCC_PCIE_CLKREF_EN>, 1661 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1662 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1663 1664 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1665 reset-names = "phy"; 1666 1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1668 assigned-clock-rates = <100000000>; 1669 1670 status = "disabled"; 1671 1672 pcie1_lane: lanes@1c0e200 { 1673 reg = <0 0x01c0e200 0 0x170>, 1674 <0 0x01c0e400 0 0x200>, 1675 <0 0x01c0ea00 0 0x1f0>, 1676 <0 0x01c0e600 0 0x170>, 1677 <0 0x01c0e800 0 0x200>, 1678 <0 0x01c0ee00 0 0xf4>; 1679 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1680 clock-names = "pipe0"; 1681 1682 #phy-cells = <0>; 1683 #clock-cells = <1>; 1684 clock-output-names = "pcie_1_pipe_clk"; 1685 }; 1686 }; 1687 1688 ipa: ipa@1e40000 { 1689 compatible = "qcom,sc7280-ipa"; 1690 1691 iommus = <&apps_smmu 0x480 0x0>, 1692 <&apps_smmu 0x482 0x0>; 1693 reg = <0 0x1e40000 0 0x8000>, 1694 <0 0x1e50000 0 0x4ad0>, 1695 <0 0x1e04000 0 0x23000>; 1696 reg-names = "ipa-reg", 1697 "ipa-shared", 1698 "gsi"; 1699 1700 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1701 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1702 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1703 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1704 interrupt-names = "ipa", 1705 "gsi", 1706 "ipa-clock-query", 1707 "ipa-setup-ready"; 1708 1709 clocks = <&rpmhcc RPMH_IPA_CLK>; 1710 clock-names = "core"; 1711 1712 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1714 interconnect-names = "memory", 1715 "config"; 1716 1717 qcom,smem-states = <&ipa_smp2p_out 0>, 1718 <&ipa_smp2p_out 1>; 1719 qcom,smem-state-names = "ipa-clock-enabled-valid", 1720 "ipa-clock-enabled"; 1721 1722 status = "disabled"; 1723 }; 1724 1725 tcsr_mutex: hwlock@1f40000 { 1726 compatible = "qcom,tcsr-mutex", "syscon"; 1727 reg = <0 0x01f40000 0 0x40000>; 1728 #hwlock-cells = <1>; 1729 }; 1730 1731 tcsr: syscon@1fc0000 { 1732 compatible = "qcom,sc7280-tcsr", "syscon"; 1733 reg = <0 0x01fc0000 0 0x30000>; 1734 }; 1735 1736 lpasscc: lpasscc@3000000 { 1737 compatible = "qcom,sc7280-lpasscc"; 1738 reg = <0 0x03000000 0 0x40>, 1739 <0 0x03c04000 0 0x4>, 1740 <0 0x03389000 0 0x24>; 1741 reg-names = "qdsp6ss", "top_cc", "cc"; 1742 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1743 clock-names = "iface"; 1744 #clock-cells = <1>; 1745 }; 1746 1747 lpass_ag_noc: interconnect@3c40000 { 1748 reg = <0 0x03c40000 0 0xf080>; 1749 compatible = "qcom,sc7280-lpass-ag-noc"; 1750 #interconnect-cells = <2>; 1751 qcom,bcm-voters = <&apps_bcm_voter>; 1752 }; 1753 1754 gpu: gpu@3d00000 { 1755 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1756 #stream-id-cells = <16>; 1757 reg = <0 0x03d00000 0 0x40000>, 1758 <0 0x03d9e000 0 0x1000>, 1759 <0 0x03d61000 0 0x800>; 1760 reg-names = "kgsl_3d0_reg_memory", 1761 "cx_mem", 1762 "cx_dbgc"; 1763 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1764 iommus = <&adreno_smmu 0 0x401>; 1765 operating-points-v2 = <&gpu_opp_table>; 1766 qcom,gmu = <&gmu>; 1767 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1768 interconnect-names = "gfx-mem"; 1769 #cooling-cells = <2>; 1770 1771 gpu_opp_table: opp-table { 1772 compatible = "operating-points-v2"; 1773 1774 opp-315000000 { 1775 opp-hz = /bits/ 64 <315000000>; 1776 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1777 opp-peak-kBps = <1804000>; 1778 }; 1779 1780 opp-450000000 { 1781 opp-hz = /bits/ 64 <450000000>; 1782 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1783 opp-peak-kBps = <4068000>; 1784 }; 1785 1786 opp-550000000 { 1787 opp-hz = /bits/ 64 <550000000>; 1788 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1789 opp-peak-kBps = <6832000>; 1790 }; 1791 }; 1792 }; 1793 1794 gmu: gmu@3d69000 { 1795 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1796 reg = <0 0x03d6a000 0 0x34000>, 1797 <0 0x3de0000 0 0x10000>, 1798 <0 0x0b290000 0 0x10000>; 1799 reg-names = "gmu", "rscc", "gmu_pdc"; 1800 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1802 interrupt-names = "hfi", "gmu"; 1803 clocks = <&gpucc 5>, 1804 <&gpucc 8>, 1805 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1806 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1807 <&gpucc 2>, 1808 <&gpucc 15>, 1809 <&gpucc 11>; 1810 clock-names = "gmu", 1811 "cxo", 1812 "axi", 1813 "memnoc", 1814 "ahb", 1815 "hub", 1816 "smmu_vote"; 1817 power-domains = <&gpucc 0>, 1818 <&gpucc 1>; 1819 power-domain-names = "cx", 1820 "gx"; 1821 iommus = <&adreno_smmu 5 0x400>; 1822 operating-points-v2 = <&gmu_opp_table>; 1823 1824 gmu_opp_table: opp-table { 1825 compatible = "operating-points-v2"; 1826 1827 opp-200000000 { 1828 opp-hz = /bits/ 64 <200000000>; 1829 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1830 }; 1831 }; 1832 }; 1833 1834 gpucc: clock-controller@3d90000 { 1835 compatible = "qcom,sc7280-gpucc"; 1836 reg = <0 0x03d90000 0 0x9000>; 1837 clocks = <&rpmhcc RPMH_CXO_CLK>, 1838 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1839 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1840 clock-names = "bi_tcxo", 1841 "gcc_gpu_gpll0_clk_src", 1842 "gcc_gpu_gpll0_div_clk_src"; 1843 #clock-cells = <1>; 1844 #reset-cells = <1>; 1845 #power-domain-cells = <1>; 1846 }; 1847 1848 adreno_smmu: iommu@3da0000 { 1849 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1850 reg = <0 0x03da0000 0 0x20000>; 1851 #iommu-cells = <2>; 1852 #global-interrupts = <2>; 1853 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1865 1866 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1867 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1868 <&gpucc 2>, 1869 <&gpucc 11>, 1870 <&gpucc 5>, 1871 <&gpucc 15>, 1872 <&gpucc 13>; 1873 clock-names = "gcc_gpu_memnoc_gfx_clk", 1874 "gcc_gpu_snoc_dvm_gfx_clk", 1875 "gpu_cc_ahb_clk", 1876 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1877 "gpu_cc_cx_gmu_clk", 1878 "gpu_cc_hub_cx_int_clk", 1879 "gpu_cc_hub_aon_clk"; 1880 1881 power-domains = <&gpucc 0>; 1882 }; 1883 1884 remoteproc_mpss: remoteproc@4080000 { 1885 compatible = "qcom,sc7280-mpss-pas"; 1886 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1887 reg-names = "qdsp6", "rmb"; 1888 1889 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1890 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1891 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1894 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1895 interrupt-names = "wdog", "fatal", "ready", "handover", 1896 "stop-ack", "shutdown-ack"; 1897 1898 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1899 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1900 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1901 <&rpmhcc RPMH_PKA_CLK>, 1902 <&rpmhcc RPMH_CXO_CLK>; 1903 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1904 1905 power-domains = <&rpmhpd SC7280_CX>, 1906 <&rpmhpd SC7280_MSS>; 1907 power-domain-names = "cx", "mss"; 1908 1909 memory-region = <&mpss_mem>; 1910 1911 qcom,qmp = <&aoss_qmp>; 1912 1913 qcom,smem-states = <&modem_smp2p_out 0>; 1914 qcom,smem-state-names = "stop"; 1915 1916 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1917 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1918 reset-names = "mss_restart", "pdc_reset"; 1919 1920 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1921 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1922 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1923 1924 status = "disabled"; 1925 1926 glink-edge { 1927 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1928 IPCC_MPROC_SIGNAL_GLINK_QMP 1929 IRQ_TYPE_EDGE_RISING>; 1930 mboxes = <&ipcc IPCC_CLIENT_MPSS 1931 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1932 label = "modem"; 1933 qcom,remote-pid = <1>; 1934 }; 1935 }; 1936 1937 stm@6002000 { 1938 compatible = "arm,coresight-stm", "arm,primecell"; 1939 reg = <0 0x06002000 0 0x1000>, 1940 <0 0x16280000 0 0x180000>; 1941 reg-names = "stm-base", "stm-stimulus-base"; 1942 1943 clocks = <&aoss_qmp>; 1944 clock-names = "apb_pclk"; 1945 1946 out-ports { 1947 port { 1948 stm_out: endpoint { 1949 remote-endpoint = <&funnel0_in7>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 1955 funnel@6041000 { 1956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1957 reg = <0 0x06041000 0 0x1000>; 1958 1959 clocks = <&aoss_qmp>; 1960 clock-names = "apb_pclk"; 1961 1962 out-ports { 1963 port { 1964 funnel0_out: endpoint { 1965 remote-endpoint = <&merge_funnel_in0>; 1966 }; 1967 }; 1968 }; 1969 1970 in-ports { 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 port@7 { 1975 reg = <7>; 1976 funnel0_in7: endpoint { 1977 remote-endpoint = <&stm_out>; 1978 }; 1979 }; 1980 }; 1981 }; 1982 1983 funnel@6042000 { 1984 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1985 reg = <0 0x06042000 0 0x1000>; 1986 1987 clocks = <&aoss_qmp>; 1988 clock-names = "apb_pclk"; 1989 1990 out-ports { 1991 port { 1992 funnel1_out: endpoint { 1993 remote-endpoint = <&merge_funnel_in1>; 1994 }; 1995 }; 1996 }; 1997 1998 in-ports { 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 2002 port@4 { 2003 reg = <4>; 2004 funnel1_in4: endpoint { 2005 remote-endpoint = <&apss_merge_funnel_out>; 2006 }; 2007 }; 2008 }; 2009 }; 2010 2011 funnel@6045000 { 2012 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2013 reg = <0 0x06045000 0 0x1000>; 2014 2015 clocks = <&aoss_qmp>; 2016 clock-names = "apb_pclk"; 2017 2018 out-ports { 2019 port { 2020 merge_funnel_out: endpoint { 2021 remote-endpoint = <&swao_funnel_in>; 2022 }; 2023 }; 2024 }; 2025 2026 in-ports { 2027 #address-cells = <1>; 2028 #size-cells = <0>; 2029 2030 port@0 { 2031 reg = <0>; 2032 merge_funnel_in0: endpoint { 2033 remote-endpoint = <&funnel0_out>; 2034 }; 2035 }; 2036 2037 port@1 { 2038 reg = <1>; 2039 merge_funnel_in1: endpoint { 2040 remote-endpoint = <&funnel1_out>; 2041 }; 2042 }; 2043 }; 2044 }; 2045 2046 replicator@6046000 { 2047 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2048 reg = <0 0x06046000 0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 2053 out-ports { 2054 port { 2055 replicator_out: endpoint { 2056 remote-endpoint = <&etr_in>; 2057 }; 2058 }; 2059 }; 2060 2061 in-ports { 2062 port { 2063 replicator_in: endpoint { 2064 remote-endpoint = <&swao_replicator_out>; 2065 }; 2066 }; 2067 }; 2068 }; 2069 2070 etr@6048000 { 2071 compatible = "arm,coresight-tmc", "arm,primecell"; 2072 reg = <0 0x06048000 0 0x1000>; 2073 iommus = <&apps_smmu 0x04c0 0>; 2074 2075 clocks = <&aoss_qmp>; 2076 clock-names = "apb_pclk"; 2077 arm,scatter-gather; 2078 2079 in-ports { 2080 port { 2081 etr_in: endpoint { 2082 remote-endpoint = <&replicator_out>; 2083 }; 2084 }; 2085 }; 2086 }; 2087 2088 funnel@6b04000 { 2089 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2090 reg = <0 0x06b04000 0 0x1000>; 2091 2092 clocks = <&aoss_qmp>; 2093 clock-names = "apb_pclk"; 2094 2095 out-ports { 2096 port { 2097 swao_funnel_out: endpoint { 2098 remote-endpoint = <&etf_in>; 2099 }; 2100 }; 2101 }; 2102 2103 in-ports { 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 port@7 { 2108 reg = <7>; 2109 swao_funnel_in: endpoint { 2110 remote-endpoint = <&merge_funnel_out>; 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 etf@6b05000 { 2117 compatible = "arm,coresight-tmc", "arm,primecell"; 2118 reg = <0 0x06b05000 0 0x1000>; 2119 2120 clocks = <&aoss_qmp>; 2121 clock-names = "apb_pclk"; 2122 2123 out-ports { 2124 port { 2125 etf_out: endpoint { 2126 remote-endpoint = <&swao_replicator_in>; 2127 }; 2128 }; 2129 }; 2130 2131 in-ports { 2132 port { 2133 etf_in: endpoint { 2134 remote-endpoint = <&swao_funnel_out>; 2135 }; 2136 }; 2137 }; 2138 }; 2139 2140 replicator@6b06000 { 2141 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2142 reg = <0 0x06b06000 0 0x1000>; 2143 2144 clocks = <&aoss_qmp>; 2145 clock-names = "apb_pclk"; 2146 qcom,replicator-loses-context; 2147 2148 out-ports { 2149 port { 2150 swao_replicator_out: endpoint { 2151 remote-endpoint = <&replicator_in>; 2152 }; 2153 }; 2154 }; 2155 2156 in-ports { 2157 port { 2158 swao_replicator_in: endpoint { 2159 remote-endpoint = <&etf_out>; 2160 }; 2161 }; 2162 }; 2163 }; 2164 2165 etm@7040000 { 2166 compatible = "arm,coresight-etm4x", "arm,primecell"; 2167 reg = <0 0x07040000 0 0x1000>; 2168 2169 cpu = <&CPU0>; 2170 2171 clocks = <&aoss_qmp>; 2172 clock-names = "apb_pclk"; 2173 arm,coresight-loses-context-with-cpu; 2174 qcom,skip-power-up; 2175 2176 out-ports { 2177 port { 2178 etm0_out: endpoint { 2179 remote-endpoint = <&apss_funnel_in0>; 2180 }; 2181 }; 2182 }; 2183 }; 2184 2185 etm@7140000 { 2186 compatible = "arm,coresight-etm4x", "arm,primecell"; 2187 reg = <0 0x07140000 0 0x1000>; 2188 2189 cpu = <&CPU1>; 2190 2191 clocks = <&aoss_qmp>; 2192 clock-names = "apb_pclk"; 2193 arm,coresight-loses-context-with-cpu; 2194 qcom,skip-power-up; 2195 2196 out-ports { 2197 port { 2198 etm1_out: endpoint { 2199 remote-endpoint = <&apss_funnel_in1>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 etm@7240000 { 2206 compatible = "arm,coresight-etm4x", "arm,primecell"; 2207 reg = <0 0x07240000 0 0x1000>; 2208 2209 cpu = <&CPU2>; 2210 2211 clocks = <&aoss_qmp>; 2212 clock-names = "apb_pclk"; 2213 arm,coresight-loses-context-with-cpu; 2214 qcom,skip-power-up; 2215 2216 out-ports { 2217 port { 2218 etm2_out: endpoint { 2219 remote-endpoint = <&apss_funnel_in2>; 2220 }; 2221 }; 2222 }; 2223 }; 2224 2225 etm@7340000 { 2226 compatible = "arm,coresight-etm4x", "arm,primecell"; 2227 reg = <0 0x07340000 0 0x1000>; 2228 2229 cpu = <&CPU3>; 2230 2231 clocks = <&aoss_qmp>; 2232 clock-names = "apb_pclk"; 2233 arm,coresight-loses-context-with-cpu; 2234 qcom,skip-power-up; 2235 2236 out-ports { 2237 port { 2238 etm3_out: endpoint { 2239 remote-endpoint = <&apss_funnel_in3>; 2240 }; 2241 }; 2242 }; 2243 }; 2244 2245 etm@7440000 { 2246 compatible = "arm,coresight-etm4x", "arm,primecell"; 2247 reg = <0 0x07440000 0 0x1000>; 2248 2249 cpu = <&CPU4>; 2250 2251 clocks = <&aoss_qmp>; 2252 clock-names = "apb_pclk"; 2253 arm,coresight-loses-context-with-cpu; 2254 qcom,skip-power-up; 2255 2256 out-ports { 2257 port { 2258 etm4_out: endpoint { 2259 remote-endpoint = <&apss_funnel_in4>; 2260 }; 2261 }; 2262 }; 2263 }; 2264 2265 etm@7540000 { 2266 compatible = "arm,coresight-etm4x", "arm,primecell"; 2267 reg = <0 0x07540000 0 0x1000>; 2268 2269 cpu = <&CPU5>; 2270 2271 clocks = <&aoss_qmp>; 2272 clock-names = "apb_pclk"; 2273 arm,coresight-loses-context-with-cpu; 2274 qcom,skip-power-up; 2275 2276 out-ports { 2277 port { 2278 etm5_out: endpoint { 2279 remote-endpoint = <&apss_funnel_in5>; 2280 }; 2281 }; 2282 }; 2283 }; 2284 2285 etm@7640000 { 2286 compatible = "arm,coresight-etm4x", "arm,primecell"; 2287 reg = <0 0x07640000 0 0x1000>; 2288 2289 cpu = <&CPU6>; 2290 2291 clocks = <&aoss_qmp>; 2292 clock-names = "apb_pclk"; 2293 arm,coresight-loses-context-with-cpu; 2294 qcom,skip-power-up; 2295 2296 out-ports { 2297 port { 2298 etm6_out: endpoint { 2299 remote-endpoint = <&apss_funnel_in6>; 2300 }; 2301 }; 2302 }; 2303 }; 2304 2305 etm@7740000 { 2306 compatible = "arm,coresight-etm4x", "arm,primecell"; 2307 reg = <0 0x07740000 0 0x1000>; 2308 2309 cpu = <&CPU7>; 2310 2311 clocks = <&aoss_qmp>; 2312 clock-names = "apb_pclk"; 2313 arm,coresight-loses-context-with-cpu; 2314 qcom,skip-power-up; 2315 2316 out-ports { 2317 port { 2318 etm7_out: endpoint { 2319 remote-endpoint = <&apss_funnel_in7>; 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 funnel@7800000 { /* APSS Funnel */ 2326 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2327 reg = <0 0x07800000 0 0x1000>; 2328 2329 clocks = <&aoss_qmp>; 2330 clock-names = "apb_pclk"; 2331 2332 out-ports { 2333 port { 2334 apss_funnel_out: endpoint { 2335 remote-endpoint = <&apss_merge_funnel_in>; 2336 }; 2337 }; 2338 }; 2339 2340 in-ports { 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 2344 port@0 { 2345 reg = <0>; 2346 apss_funnel_in0: endpoint { 2347 remote-endpoint = <&etm0_out>; 2348 }; 2349 }; 2350 2351 port@1 { 2352 reg = <1>; 2353 apss_funnel_in1: endpoint { 2354 remote-endpoint = <&etm1_out>; 2355 }; 2356 }; 2357 2358 port@2 { 2359 reg = <2>; 2360 apss_funnel_in2: endpoint { 2361 remote-endpoint = <&etm2_out>; 2362 }; 2363 }; 2364 2365 port@3 { 2366 reg = <3>; 2367 apss_funnel_in3: endpoint { 2368 remote-endpoint = <&etm3_out>; 2369 }; 2370 }; 2371 2372 port@4 { 2373 reg = <4>; 2374 apss_funnel_in4: endpoint { 2375 remote-endpoint = <&etm4_out>; 2376 }; 2377 }; 2378 2379 port@5 { 2380 reg = <5>; 2381 apss_funnel_in5: endpoint { 2382 remote-endpoint = <&etm5_out>; 2383 }; 2384 }; 2385 2386 port@6 { 2387 reg = <6>; 2388 apss_funnel_in6: endpoint { 2389 remote-endpoint = <&etm6_out>; 2390 }; 2391 }; 2392 2393 port@7 { 2394 reg = <7>; 2395 apss_funnel_in7: endpoint { 2396 remote-endpoint = <&etm7_out>; 2397 }; 2398 }; 2399 }; 2400 }; 2401 2402 funnel@7810000 { 2403 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2404 reg = <0 0x07810000 0 0x1000>; 2405 2406 clocks = <&aoss_qmp>; 2407 clock-names = "apb_pclk"; 2408 2409 out-ports { 2410 port { 2411 apss_merge_funnel_out: endpoint { 2412 remote-endpoint = <&funnel1_in4>; 2413 }; 2414 }; 2415 }; 2416 2417 in-ports { 2418 port { 2419 apss_merge_funnel_in: endpoint { 2420 remote-endpoint = <&apss_funnel_out>; 2421 }; 2422 }; 2423 }; 2424 }; 2425 2426 sdhc_2: sdhci@8804000 { 2427 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2428 status = "disabled"; 2429 2430 reg = <0 0x08804000 0 0x1000>; 2431 2432 iommus = <&apps_smmu 0x100 0x0>; 2433 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2435 interrupt-names = "hc_irq", "pwr_irq"; 2436 2437 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2438 <&gcc GCC_SDCC2_AHB_CLK>, 2439 <&rpmhcc RPMH_CXO_CLK>; 2440 clock-names = "core", "iface", "xo"; 2441 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2442 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2443 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2444 power-domains = <&rpmhpd SC7280_CX>; 2445 operating-points-v2 = <&sdhc2_opp_table>; 2446 2447 bus-width = <4>; 2448 2449 qcom,dll-config = <0x0007642c>; 2450 2451 sdhc2_opp_table: opp-table { 2452 compatible = "operating-points-v2"; 2453 2454 opp-100000000 { 2455 opp-hz = /bits/ 64 <100000000>; 2456 required-opps = <&rpmhpd_opp_low_svs>; 2457 opp-peak-kBps = <1800000 400000>; 2458 opp-avg-kBps = <100000 0>; 2459 }; 2460 2461 opp-202000000 { 2462 opp-hz = /bits/ 64 <202000000>; 2463 required-opps = <&rpmhpd_opp_nom>; 2464 opp-peak-kBps = <5400000 1600000>; 2465 opp-avg-kBps = <200000 0>; 2466 }; 2467 }; 2468 2469 }; 2470 2471 usb_1_hsphy: phy@88e3000 { 2472 compatible = "qcom,sc7280-usb-hs-phy", 2473 "qcom,usb-snps-hs-7nm-phy"; 2474 reg = <0 0x088e3000 0 0x400>; 2475 status = "disabled"; 2476 #phy-cells = <0>; 2477 2478 clocks = <&rpmhcc RPMH_CXO_CLK>; 2479 clock-names = "ref"; 2480 2481 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2482 }; 2483 2484 usb_2_hsphy: phy@88e4000 { 2485 compatible = "qcom,sc7280-usb-hs-phy", 2486 "qcom,usb-snps-hs-7nm-phy"; 2487 reg = <0 0x088e4000 0 0x400>; 2488 status = "disabled"; 2489 #phy-cells = <0>; 2490 2491 clocks = <&rpmhcc RPMH_CXO_CLK>; 2492 clock-names = "ref"; 2493 2494 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2495 }; 2496 2497 usb_1_qmpphy: phy-wrapper@88e9000 { 2498 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2499 "qcom,sm8250-qmp-usb3-dp-phy"; 2500 reg = <0 0x088e9000 0 0x200>, 2501 <0 0x088e8000 0 0x40>, 2502 <0 0x088ea000 0 0x200>; 2503 status = "disabled"; 2504 #address-cells = <2>; 2505 #size-cells = <2>; 2506 ranges; 2507 2508 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2509 <&rpmhcc RPMH_CXO_CLK>, 2510 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2511 clock-names = "aux", "ref_clk_src", "com_aux"; 2512 2513 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2514 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2515 reset-names = "phy", "common"; 2516 2517 usb_1_ssphy: usb3-phy@88e9200 { 2518 reg = <0 0x088e9200 0 0x200>, 2519 <0 0x088e9400 0 0x200>, 2520 <0 0x088e9c00 0 0x400>, 2521 <0 0x088e9600 0 0x200>, 2522 <0 0x088e9800 0 0x200>, 2523 <0 0x088e9a00 0 0x100>; 2524 #clock-cells = <0>; 2525 #phy-cells = <0>; 2526 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2527 clock-names = "pipe0"; 2528 clock-output-names = "usb3_phy_pipe_clk_src"; 2529 }; 2530 2531 dp_phy: dp-phy@88ea200 { 2532 reg = <0 0x088ea200 0 0x200>, 2533 <0 0x088ea400 0 0x200>, 2534 <0 0x088eaa00 0 0x200>, 2535 <0 0x088ea600 0 0x200>, 2536 <0 0x088ea800 0 0x200>; 2537 #phy-cells = <0>; 2538 #clock-cells = <1>; 2539 }; 2540 }; 2541 2542 usb_2: usb@8cf8800 { 2543 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2544 reg = <0 0x08cf8800 0 0x400>; 2545 status = "disabled"; 2546 #address-cells = <2>; 2547 #size-cells = <2>; 2548 ranges; 2549 dma-ranges; 2550 2551 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2552 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2553 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2554 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2555 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2556 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2557 "sleep"; 2558 2559 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2560 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2561 assigned-clock-rates = <19200000>, <200000000>; 2562 2563 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2564 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2565 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2566 interrupt-names = "hs_phy_irq", 2567 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2568 2569 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2570 2571 resets = <&gcc GCC_USB30_SEC_BCR>; 2572 2573 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2574 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2575 interconnect-names = "usb-ddr", "apps-usb"; 2576 2577 usb_2_dwc3: usb@8c00000 { 2578 compatible = "snps,dwc3"; 2579 reg = <0 0x08c00000 0 0xe000>; 2580 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2581 iommus = <&apps_smmu 0xa0 0x0>; 2582 snps,dis_u2_susphy_quirk; 2583 snps,dis_enblslpm_quirk; 2584 phys = <&usb_2_hsphy>; 2585 phy-names = "usb2-phy"; 2586 maximum-speed = "high-speed"; 2587 }; 2588 }; 2589 2590 qspi: spi@88dc000 { 2591 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2592 reg = <0 0x088dc000 0 0x1000>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2597 <&gcc GCC_QSPI_CORE_CLK>; 2598 clock-names = "iface", "core"; 2599 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2600 &cnoc2 SLAVE_QSPI_0 0>; 2601 interconnect-names = "qspi-config"; 2602 power-domains = <&rpmhpd SC7280_CX>; 2603 operating-points-v2 = <&qspi_opp_table>; 2604 status = "disabled"; 2605 }; 2606 2607 dc_noc: interconnect@90e0000 { 2608 reg = <0 0x090e0000 0 0x5080>; 2609 compatible = "qcom,sc7280-dc-noc"; 2610 #interconnect-cells = <2>; 2611 qcom,bcm-voters = <&apps_bcm_voter>; 2612 }; 2613 2614 gem_noc: interconnect@9100000 { 2615 reg = <0 0x9100000 0 0xe2200>; 2616 compatible = "qcom,sc7280-gem-noc"; 2617 #interconnect-cells = <2>; 2618 qcom,bcm-voters = <&apps_bcm_voter>; 2619 }; 2620 2621 system-cache-controller@9200000 { 2622 compatible = "qcom,sc7280-llcc"; 2623 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2624 reg-names = "llcc_base", "llcc_broadcast_base"; 2625 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2626 }; 2627 2628 nsp_noc: interconnect@a0c0000 { 2629 reg = <0 0x0a0c0000 0 0x10000>; 2630 compatible = "qcom,sc7280-nsp-noc"; 2631 #interconnect-cells = <2>; 2632 qcom,bcm-voters = <&apps_bcm_voter>; 2633 }; 2634 2635 usb_1: usb@a6f8800 { 2636 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2637 reg = <0 0x0a6f8800 0 0x400>; 2638 status = "disabled"; 2639 #address-cells = <2>; 2640 #size-cells = <2>; 2641 ranges; 2642 dma-ranges; 2643 2644 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2645 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2646 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2647 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2648 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2649 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2650 "sleep"; 2651 2652 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2653 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2654 assigned-clock-rates = <19200000>, <200000000>; 2655 2656 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2657 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2658 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2659 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2660 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2661 "dm_hs_phy_irq", "ss_phy_irq"; 2662 2663 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2664 2665 resets = <&gcc GCC_USB30_PRIM_BCR>; 2666 2667 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2669 interconnect-names = "usb-ddr", "apps-usb"; 2670 2671 usb_1_dwc3: usb@a600000 { 2672 compatible = "snps,dwc3"; 2673 reg = <0 0x0a600000 0 0xe000>; 2674 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2675 iommus = <&apps_smmu 0xe0 0x0>; 2676 snps,dis_u2_susphy_quirk; 2677 snps,dis_enblslpm_quirk; 2678 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2679 phy-names = "usb2-phy", "usb3-phy"; 2680 maximum-speed = "super-speed"; 2681 }; 2682 }; 2683 2684 venus: video-codec@aa00000 { 2685 compatible = "qcom,sc7280-venus"; 2686 reg = <0 0x0aa00000 0 0xd0600>; 2687 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2688 2689 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2690 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2691 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2692 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2693 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2694 clock-names = "core", "bus", "iface", 2695 "vcodec_core", "vcodec_bus"; 2696 2697 power-domains = <&videocc MVSC_GDSC>, 2698 <&videocc MVS0_GDSC>, 2699 <&rpmhpd SC7280_CX>; 2700 power-domain-names = "venus", "vcodec0", "cx"; 2701 operating-points-v2 = <&venus_opp_table>; 2702 2703 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2704 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2705 interconnect-names = "cpu-cfg", "video-mem"; 2706 2707 iommus = <&apps_smmu 0x2180 0x20>, 2708 <&apps_smmu 0x2184 0x20>; 2709 memory-region = <&video_mem>; 2710 2711 video-decoder { 2712 compatible = "venus-decoder"; 2713 }; 2714 2715 video-encoder { 2716 compatible = "venus-encoder"; 2717 }; 2718 2719 video-firmware { 2720 iommus = <&apps_smmu 0x21a2 0x0>; 2721 }; 2722 2723 venus_opp_table: venus-opp-table { 2724 compatible = "operating-points-v2"; 2725 2726 opp-133330000 { 2727 opp-hz = /bits/ 64 <133330000>; 2728 required-opps = <&rpmhpd_opp_low_svs>; 2729 }; 2730 2731 opp-240000000 { 2732 opp-hz = /bits/ 64 <240000000>; 2733 required-opps = <&rpmhpd_opp_svs>; 2734 }; 2735 2736 opp-335000000 { 2737 opp-hz = /bits/ 64 <335000000>; 2738 required-opps = <&rpmhpd_opp_svs_l1>; 2739 }; 2740 2741 opp-424000000 { 2742 opp-hz = /bits/ 64 <424000000>; 2743 required-opps = <&rpmhpd_opp_nom>; 2744 }; 2745 2746 opp-460000048 { 2747 opp-hz = /bits/ 64 <460000048>; 2748 required-opps = <&rpmhpd_opp_turbo>; 2749 }; 2750 }; 2751 2752 }; 2753 2754 videocc: clock-controller@aaf0000 { 2755 compatible = "qcom,sc7280-videocc"; 2756 reg = <0 0xaaf0000 0 0x10000>; 2757 clocks = <&rpmhcc RPMH_CXO_CLK>, 2758 <&rpmhcc RPMH_CXO_CLK_A>; 2759 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2760 #clock-cells = <1>; 2761 #reset-cells = <1>; 2762 #power-domain-cells = <1>; 2763 }; 2764 2765 dispcc: clock-controller@af00000 { 2766 compatible = "qcom,sc7280-dispcc"; 2767 reg = <0 0xaf00000 0 0x20000>; 2768 clocks = <&rpmhcc RPMH_CXO_CLK>, 2769 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2770 <0>, <0>, <0>, <0>, <0>, <0>; 2771 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2772 "dsi0_phy_pll_out_byteclk", 2773 "dsi0_phy_pll_out_dsiclk", 2774 "dp_phy_pll_link_clk", 2775 "dp_phy_pll_vco_div_clk", 2776 "edp_phy_pll_link_clk", 2777 "edp_phy_pll_vco_div_clk"; 2778 #clock-cells = <1>; 2779 #reset-cells = <1>; 2780 #power-domain-cells = <1>; 2781 }; 2782 2783 pdc: interrupt-controller@b220000 { 2784 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2785 reg = <0 0x0b220000 0 0x30000>; 2786 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2787 <55 306 4>, <59 312 3>, <62 374 2>, 2788 <64 434 2>, <66 438 3>, <69 86 1>, 2789 <70 520 54>, <124 609 31>, <155 63 1>, 2790 <156 716 12>; 2791 #interrupt-cells = <2>; 2792 interrupt-parent = <&intc>; 2793 interrupt-controller; 2794 }; 2795 2796 pdc_reset: reset-controller@b5e0000 { 2797 compatible = "qcom,sc7280-pdc-global"; 2798 reg = <0 0x0b5e0000 0 0x20000>; 2799 #reset-cells = <1>; 2800 }; 2801 2802 tsens0: thermal-sensor@c263000 { 2803 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2804 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2805 <0 0x0c222000 0 0x1ff>; /* SROT */ 2806 #qcom,sensors = <15>; 2807 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2809 interrupt-names = "uplow","critical"; 2810 #thermal-sensor-cells = <1>; 2811 }; 2812 2813 tsens1: thermal-sensor@c265000 { 2814 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2815 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2816 <0 0x0c223000 0 0x1ff>; /* SROT */ 2817 #qcom,sensors = <12>; 2818 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2819 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2820 interrupt-names = "uplow","critical"; 2821 #thermal-sensor-cells = <1>; 2822 }; 2823 2824 aoss_reset: reset-controller@c2a0000 { 2825 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2826 reg = <0 0x0c2a0000 0 0x31000>; 2827 #reset-cells = <1>; 2828 }; 2829 2830 aoss_qmp: power-controller@c300000 { 2831 compatible = "qcom,sc7280-aoss-qmp"; 2832 reg = <0 0x0c300000 0 0x400>; 2833 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2834 IPCC_MPROC_SIGNAL_GLINK_QMP 2835 IRQ_TYPE_EDGE_RISING>; 2836 mboxes = <&ipcc IPCC_CLIENT_AOP 2837 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2838 2839 #clock-cells = <0>; 2840 }; 2841 2842 sram@c3f0000 { 2843 compatible = "qcom,rpmh-stats"; 2844 reg = <0 0x0c3f0000 0 0x400>; 2845 }; 2846 2847 spmi_bus: spmi@c440000 { 2848 compatible = "qcom,spmi-pmic-arb"; 2849 reg = <0 0x0c440000 0 0x1100>, 2850 <0 0x0c600000 0 0x2000000>, 2851 <0 0x0e600000 0 0x100000>, 2852 <0 0x0e700000 0 0xa0000>, 2853 <0 0x0c40a000 0 0x26000>; 2854 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2855 interrupt-names = "periph_irq"; 2856 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2857 qcom,ee = <0>; 2858 qcom,channel = <0>; 2859 #address-cells = <1>; 2860 #size-cells = <1>; 2861 interrupt-controller; 2862 #interrupt-cells = <4>; 2863 }; 2864 2865 tlmm: pinctrl@f100000 { 2866 compatible = "qcom,sc7280-pinctrl"; 2867 reg = <0 0x0f100000 0 0x300000>; 2868 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2869 gpio-controller; 2870 #gpio-cells = <2>; 2871 interrupt-controller; 2872 #interrupt-cells = <2>; 2873 gpio-ranges = <&tlmm 0 0 175>; 2874 wakeup-parent = <&pdc>; 2875 2876 pcie1_clkreq_n: pcie1-clkreq-n { 2877 pins = "gpio79"; 2878 function = "pcie1_clkreqn"; 2879 drive-strength = <2>; 2880 bias-pull-up; 2881 }; 2882 2883 qspi_clk: qspi-clk { 2884 pins = "gpio14"; 2885 function = "qspi_clk"; 2886 }; 2887 2888 qspi_cs0: qspi-cs0 { 2889 pins = "gpio15"; 2890 function = "qspi_cs"; 2891 }; 2892 2893 qspi_cs1: qspi-cs1 { 2894 pins = "gpio19"; 2895 function = "qspi_cs"; 2896 }; 2897 2898 qspi_data01: qspi-data01 { 2899 pins = "gpio12", "gpio13"; 2900 function = "qspi_data"; 2901 }; 2902 2903 qspi_data12: qspi-data12 { 2904 pins = "gpio16", "gpio17"; 2905 function = "qspi_data"; 2906 }; 2907 2908 qup_i2c0_data_clk: qup-i2c0-data-clk { 2909 pins = "gpio0", "gpio1"; 2910 function = "qup00"; 2911 }; 2912 2913 qup_i2c1_data_clk: qup-i2c1-data-clk { 2914 pins = "gpio4", "gpio5"; 2915 function = "qup01"; 2916 }; 2917 2918 qup_i2c2_data_clk: qup-i2c2-data-clk { 2919 pins = "gpio8", "gpio9"; 2920 function = "qup02"; 2921 }; 2922 2923 qup_i2c3_data_clk: qup-i2c3-data-clk { 2924 pins = "gpio12", "gpio13"; 2925 function = "qup03"; 2926 }; 2927 2928 qup_i2c4_data_clk: qup-i2c4-data-clk { 2929 pins = "gpio16", "gpio17"; 2930 function = "qup04"; 2931 }; 2932 2933 qup_i2c5_data_clk: qup-i2c5-data-clk { 2934 pins = "gpio20", "gpio21"; 2935 function = "qup05"; 2936 }; 2937 2938 qup_i2c6_data_clk: qup-i2c6-data-clk { 2939 pins = "gpio24", "gpio25"; 2940 function = "qup06"; 2941 }; 2942 2943 qup_i2c7_data_clk: qup-i2c7-data-clk { 2944 pins = "gpio28", "gpio29"; 2945 function = "qup07"; 2946 }; 2947 2948 qup_i2c8_data_clk: qup-i2c8-data-clk { 2949 pins = "gpio32", "gpio33"; 2950 function = "qup10"; 2951 }; 2952 2953 qup_i2c9_data_clk: qup-i2c9-data-clk { 2954 pins = "gpio36", "gpio37"; 2955 function = "qup11"; 2956 }; 2957 2958 qup_i2c10_data_clk: qup-i2c10-data-clk { 2959 pins = "gpio40", "gpio41"; 2960 function = "qup12"; 2961 }; 2962 2963 qup_i2c11_data_clk: qup-i2c11-data-clk { 2964 pins = "gpio44", "gpio45"; 2965 function = "qup13"; 2966 }; 2967 2968 qup_i2c12_data_clk: qup-i2c12-data-clk { 2969 pins = "gpio48", "gpio49"; 2970 function = "qup14"; 2971 }; 2972 2973 qup_i2c13_data_clk: qup-i2c13-data-clk { 2974 pins = "gpio52", "gpio53"; 2975 function = "qup15"; 2976 }; 2977 2978 qup_i2c14_data_clk: qup-i2c14-data-clk { 2979 pins = "gpio56", "gpio57"; 2980 function = "qup16"; 2981 }; 2982 2983 qup_i2c15_data_clk: qup-i2c15-data-clk { 2984 pins = "gpio60", "gpio61"; 2985 function = "qup17"; 2986 }; 2987 2988 qup_spi0_data_clk: qup-spi0-data-clk { 2989 pins = "gpio0", "gpio1", "gpio2"; 2990 function = "qup00"; 2991 }; 2992 2993 qup_spi0_cs: qup-spi0-cs { 2994 pins = "gpio3"; 2995 function = "qup00"; 2996 }; 2997 2998 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2999 pins = "gpio3"; 3000 function = "gpio"; 3001 }; 3002 3003 qup_spi1_data_clk: qup-spi1-data-clk { 3004 pins = "gpio4", "gpio5", "gpio6"; 3005 function = "qup01"; 3006 }; 3007 3008 qup_spi1_cs: qup-spi1-cs { 3009 pins = "gpio7"; 3010 function = "qup01"; 3011 }; 3012 3013 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3014 pins = "gpio7"; 3015 function = "gpio"; 3016 }; 3017 3018 qup_spi2_data_clk: qup-spi2-data-clk { 3019 pins = "gpio8", "gpio9", "gpio10"; 3020 function = "qup02"; 3021 }; 3022 3023 qup_spi2_cs: qup-spi2-cs { 3024 pins = "gpio11"; 3025 function = "qup02"; 3026 }; 3027 3028 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3029 pins = "gpio11"; 3030 function = "gpio"; 3031 }; 3032 3033 qup_spi3_data_clk: qup-spi3-data-clk { 3034 pins = "gpio12", "gpio13", "gpio14"; 3035 function = "qup03"; 3036 }; 3037 3038 qup_spi3_cs: qup-spi3-cs { 3039 pins = "gpio15"; 3040 function = "qup03"; 3041 }; 3042 3043 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3044 pins = "gpio15"; 3045 function = "gpio"; 3046 }; 3047 3048 qup_spi4_data_clk: qup-spi4-data-clk { 3049 pins = "gpio16", "gpio17", "gpio18"; 3050 function = "qup04"; 3051 }; 3052 3053 qup_spi4_cs: qup-spi4-cs { 3054 pins = "gpio19"; 3055 function = "qup04"; 3056 }; 3057 3058 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3059 pins = "gpio19"; 3060 function = "gpio"; 3061 }; 3062 3063 qup_spi5_data_clk: qup-spi5-data-clk { 3064 pins = "gpio20", "gpio21", "gpio22"; 3065 function = "qup05"; 3066 }; 3067 3068 qup_spi5_cs: qup-spi5-cs { 3069 pins = "gpio23"; 3070 function = "qup05"; 3071 }; 3072 3073 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3074 pins = "gpio23"; 3075 function = "gpio"; 3076 }; 3077 3078 qup_spi6_data_clk: qup-spi6-data-clk { 3079 pins = "gpio24", "gpio25", "gpio26"; 3080 function = "qup06"; 3081 }; 3082 3083 qup_spi6_cs: qup-spi6-cs { 3084 pins = "gpio27"; 3085 function = "qup06"; 3086 }; 3087 3088 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3089 pins = "gpio27"; 3090 function = "gpio"; 3091 }; 3092 3093 qup_spi7_data_clk: qup-spi7-data-clk { 3094 pins = "gpio28", "gpio29", "gpio30"; 3095 function = "qup07"; 3096 }; 3097 3098 qup_spi7_cs: qup-spi7-cs { 3099 pins = "gpio31"; 3100 function = "qup07"; 3101 }; 3102 3103 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3104 pins = "gpio31"; 3105 function = "gpio"; 3106 }; 3107 3108 qup_spi8_data_clk: qup-spi8-data-clk { 3109 pins = "gpio32", "gpio33", "gpio34"; 3110 function = "qup10"; 3111 }; 3112 3113 qup_spi8_cs: qup-spi8-cs { 3114 pins = "gpio35"; 3115 function = "qup10"; 3116 }; 3117 3118 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3119 pins = "gpio35"; 3120 function = "gpio"; 3121 }; 3122 3123 qup_spi9_data_clk: qup-spi9-data-clk { 3124 pins = "gpio36", "gpio37", "gpio38"; 3125 function = "qup11"; 3126 }; 3127 3128 qup_spi9_cs: qup-spi9-cs { 3129 pins = "gpio39"; 3130 function = "qup11"; 3131 }; 3132 3133 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3134 pins = "gpio39"; 3135 function = "gpio"; 3136 }; 3137 3138 qup_spi10_data_clk: qup-spi10-data-clk { 3139 pins = "gpio40", "gpio41", "gpio42"; 3140 function = "qup12"; 3141 }; 3142 3143 qup_spi10_cs: qup-spi10-cs { 3144 pins = "gpio43"; 3145 function = "qup12"; 3146 }; 3147 3148 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3149 pins = "gpio43"; 3150 function = "gpio"; 3151 }; 3152 3153 qup_spi11_data_clk: qup-spi11-data-clk { 3154 pins = "gpio44", "gpio45", "gpio46"; 3155 function = "qup13"; 3156 }; 3157 3158 qup_spi11_cs: qup-spi11-cs { 3159 pins = "gpio47"; 3160 function = "qup13"; 3161 }; 3162 3163 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3164 pins = "gpio47"; 3165 function = "gpio"; 3166 }; 3167 3168 qup_spi12_data_clk: qup-spi12-data-clk { 3169 pins = "gpio48", "gpio49", "gpio50"; 3170 function = "qup14"; 3171 }; 3172 3173 qup_spi12_cs: qup-spi12-cs { 3174 pins = "gpio51"; 3175 function = "qup14"; 3176 }; 3177 3178 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3179 pins = "gpio51"; 3180 function = "gpio"; 3181 }; 3182 3183 qup_spi13_data_clk: qup-spi13-data-clk { 3184 pins = "gpio52", "gpio53", "gpio54"; 3185 function = "qup15"; 3186 }; 3187 3188 qup_spi13_cs: qup-spi13-cs { 3189 pins = "gpio55"; 3190 function = "qup15"; 3191 }; 3192 3193 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3194 pins = "gpio55"; 3195 function = "gpio"; 3196 }; 3197 3198 qup_spi14_data_clk: qup-spi14-data-clk { 3199 pins = "gpio56", "gpio57", "gpio58"; 3200 function = "qup16"; 3201 }; 3202 3203 qup_spi14_cs: qup-spi14-cs { 3204 pins = "gpio59"; 3205 function = "qup16"; 3206 }; 3207 3208 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3209 pins = "gpio59"; 3210 function = "gpio"; 3211 }; 3212 3213 qup_spi15_data_clk: qup-spi15-data-clk { 3214 pins = "gpio60", "gpio61", "gpio62"; 3215 function = "qup17"; 3216 }; 3217 3218 qup_spi15_cs: qup-spi15-cs { 3219 pins = "gpio63"; 3220 function = "qup17"; 3221 }; 3222 3223 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3224 pins = "gpio63"; 3225 function = "gpio"; 3226 }; 3227 3228 qup_uart0_cts: qup-uart0-cts { 3229 pins = "gpio0"; 3230 function = "qup00"; 3231 }; 3232 3233 qup_uart0_rts: qup-uart0-rts { 3234 pins = "gpio1"; 3235 function = "qup00"; 3236 }; 3237 3238 qup_uart0_tx: qup-uart0-tx { 3239 pins = "gpio2"; 3240 function = "qup00"; 3241 }; 3242 3243 qup_uart0_rx: qup-uart0-rx { 3244 pins = "gpio3"; 3245 function = "qup00"; 3246 }; 3247 3248 qup_uart1_cts: qup-uart1-cts { 3249 pins = "gpio4"; 3250 function = "qup01"; 3251 }; 3252 3253 qup_uart1_rts: qup-uart1-rts { 3254 pins = "gpio5"; 3255 function = "qup01"; 3256 }; 3257 3258 qup_uart1_tx: qup-uart1-tx { 3259 pins = "gpio6"; 3260 function = "qup01"; 3261 }; 3262 3263 qup_uart1_rx: qup-uart1-rx { 3264 pins = "gpio7"; 3265 function = "qup01"; 3266 }; 3267 3268 qup_uart2_cts: qup-uart2-cts { 3269 pins = "gpio8"; 3270 function = "qup02"; 3271 }; 3272 3273 qup_uart2_rts: qup-uart2-rts { 3274 pins = "gpio9"; 3275 function = "qup02"; 3276 }; 3277 3278 qup_uart2_tx: qup-uart2-tx { 3279 pins = "gpio10"; 3280 function = "qup02"; 3281 }; 3282 3283 qup_uart2_rx: qup-uart2-rx { 3284 pins = "gpio11"; 3285 function = "qup02"; 3286 }; 3287 3288 qup_uart3_cts: qup-uart3-cts { 3289 pins = "gpio12"; 3290 function = "qup03"; 3291 }; 3292 3293 qup_uart3_rts: qup-uart3-rts { 3294 pins = "gpio13"; 3295 function = "qup03"; 3296 }; 3297 3298 qup_uart3_tx: qup-uart3-tx { 3299 pins = "gpio14"; 3300 function = "qup03"; 3301 }; 3302 3303 qup_uart3_rx: qup-uart3-rx { 3304 pins = "gpio15"; 3305 function = "qup03"; 3306 }; 3307 3308 qup_uart4_cts: qup-uart4-cts { 3309 pins = "gpio16"; 3310 function = "qup04"; 3311 }; 3312 3313 qup_uart4_rts: qup-uart4-rts { 3314 pins = "gpio17"; 3315 function = "qup04"; 3316 }; 3317 3318 qup_uart4_tx: qup-uart4-tx { 3319 pins = "gpio18"; 3320 function = "qup04"; 3321 }; 3322 3323 qup_uart4_rx: qup-uart4-rx { 3324 pins = "gpio19"; 3325 function = "qup04"; 3326 }; 3327 3328 qup_uart5_cts: qup-uart5-cts { 3329 pins = "gpio20"; 3330 function = "qup05"; 3331 }; 3332 3333 qup_uart5_rts: qup-uart5-rts { 3334 pins = "gpio21"; 3335 function = "qup05"; 3336 }; 3337 3338 qup_uart5_tx: qup-uart5-tx { 3339 pins = "gpio22"; 3340 function = "qup05"; 3341 }; 3342 3343 qup_uart5_rx: qup-uart5-rx { 3344 pins = "gpio23"; 3345 function = "qup05"; 3346 }; 3347 3348 qup_uart6_cts: qup-uart6-cts { 3349 pins = "gpio24"; 3350 function = "qup06"; 3351 }; 3352 3353 qup_uart6_rts: qup-uart6-rts { 3354 pins = "gpio25"; 3355 function = "qup06"; 3356 }; 3357 3358 qup_uart6_tx: qup-uart6-tx { 3359 pins = "gpio26"; 3360 function = "qup06"; 3361 }; 3362 3363 qup_uart6_rx: qup-uart6-rx { 3364 pins = "gpio27"; 3365 function = "qup06"; 3366 }; 3367 3368 qup_uart7_cts: qup-uart7-cts { 3369 pins = "gpio28"; 3370 function = "qup07"; 3371 }; 3372 3373 qup_uart7_rts: qup-uart7-rts { 3374 pins = "gpio29"; 3375 function = "qup07"; 3376 }; 3377 3378 qup_uart7_tx: qup-uart7-tx { 3379 pins = "gpio30"; 3380 function = "qup07"; 3381 }; 3382 3383 qup_uart7_rx: qup-uart7-rx { 3384 pins = "gpio31"; 3385 function = "qup07"; 3386 }; 3387 3388 sdc1_on: sdc1-on { 3389 clk { 3390 pins = "sdc1_clk"; 3391 }; 3392 3393 cmd { 3394 pins = "sdc1_cmd"; 3395 }; 3396 3397 data { 3398 pins = "sdc1_data"; 3399 }; 3400 3401 rclk { 3402 pins = "sdc1_rclk"; 3403 }; 3404 }; 3405 3406 sdc1_off: sdc1-off { 3407 clk { 3408 pins = "sdc1_clk"; 3409 drive-strength = <2>; 3410 bias-bus-hold; 3411 }; 3412 3413 cmd { 3414 pins = "sdc1_cmd"; 3415 drive-strength = <2>; 3416 bias-bus-hold; 3417 }; 3418 3419 data { 3420 pins = "sdc1_data"; 3421 drive-strength = <2>; 3422 bias-bus-hold; 3423 }; 3424 3425 rclk { 3426 pins = "sdc1_rclk"; 3427 bias-bus-hold; 3428 }; 3429 }; 3430 3431 sdc2_on: sdc2-on { 3432 clk { 3433 pins = "sdc2_clk"; 3434 }; 3435 3436 cmd { 3437 pins = "sdc2_cmd"; 3438 }; 3439 3440 data { 3441 pins = "sdc2_data"; 3442 }; 3443 }; 3444 3445 sdc2_off: sdc2-off { 3446 clk { 3447 pins = "sdc2_clk"; 3448 drive-strength = <2>; 3449 bias-bus-hold; 3450 }; 3451 3452 cmd { 3453 pins ="sdc2_cmd"; 3454 drive-strength = <2>; 3455 bias-bus-hold; 3456 }; 3457 3458 data { 3459 pins ="sdc2_data"; 3460 drive-strength = <2>; 3461 bias-bus-hold; 3462 }; 3463 }; 3464 3465 qup_uart8_cts: qup-uart8-cts { 3466 pins = "gpio32"; 3467 function = "qup10"; 3468 }; 3469 3470 qup_uart8_rts: qup-uart8-rts { 3471 pins = "gpio33"; 3472 function = "qup10"; 3473 }; 3474 3475 qup_uart8_tx: qup-uart8-tx { 3476 pins = "gpio34"; 3477 function = "qup10"; 3478 }; 3479 3480 qup_uart8_rx: qup-uart8-rx { 3481 pins = "gpio35"; 3482 function = "qup10"; 3483 }; 3484 3485 qup_uart9_cts: qup-uart9-cts { 3486 pins = "gpio36"; 3487 function = "qup11"; 3488 }; 3489 3490 qup_uart9_rts: qup-uart9-rts { 3491 pins = "gpio37"; 3492 function = "qup11"; 3493 }; 3494 3495 qup_uart9_tx: qup-uart9-tx { 3496 pins = "gpio38"; 3497 function = "qup11"; 3498 }; 3499 3500 qup_uart9_rx: qup-uart9-rx { 3501 pins = "gpio39"; 3502 function = "qup11"; 3503 }; 3504 3505 qup_uart10_cts: qup-uart10-cts { 3506 pins = "gpio40"; 3507 function = "qup12"; 3508 }; 3509 3510 qup_uart10_rts: qup-uart10-rts { 3511 pins = "gpio41"; 3512 function = "qup12"; 3513 }; 3514 3515 qup_uart10_tx: qup-uart10-tx { 3516 pins = "gpio42"; 3517 function = "qup12"; 3518 }; 3519 3520 qup_uart10_rx: qup-uart10-rx { 3521 pins = "gpio43"; 3522 function = "qup12"; 3523 }; 3524 3525 qup_uart11_cts: qup-uart11-cts { 3526 pins = "gpio44"; 3527 function = "qup13"; 3528 }; 3529 3530 qup_uart11_rts: qup-uart11-rts { 3531 pins = "gpio45"; 3532 function = "qup13"; 3533 }; 3534 3535 qup_uart11_tx: qup-uart11-tx { 3536 pins = "gpio46"; 3537 function = "qup13"; 3538 }; 3539 3540 qup_uart11_rx: qup-uart11-rx { 3541 pins = "gpio47"; 3542 function = "qup13"; 3543 }; 3544 3545 qup_uart12_cts: qup-uart12-cts { 3546 pins = "gpio48"; 3547 function = "qup14"; 3548 }; 3549 3550 qup_uart12_rts: qup-uart12-rts { 3551 pins = "gpio49"; 3552 function = "qup14"; 3553 }; 3554 3555 qup_uart12_tx: qup-uart12-tx { 3556 pins = "gpio50"; 3557 function = "qup14"; 3558 }; 3559 3560 qup_uart12_rx: qup-uart12-rx { 3561 pins = "gpio51"; 3562 function = "qup14"; 3563 }; 3564 3565 qup_uart13_cts: qup-uart13-cts { 3566 pins = "gpio52"; 3567 function = "qup15"; 3568 }; 3569 3570 qup_uart13_rts: qup-uart13-rts { 3571 pins = "gpio53"; 3572 function = "qup15"; 3573 }; 3574 3575 qup_uart13_tx: qup-uart13-tx { 3576 pins = "gpio54"; 3577 function = "qup15"; 3578 }; 3579 3580 qup_uart13_rx: qup-uart13-rx { 3581 pins = "gpio55"; 3582 function = "qup15"; 3583 }; 3584 3585 qup_uart14_cts: qup-uart14-cts { 3586 pins = "gpio56"; 3587 function = "qup16"; 3588 }; 3589 3590 qup_uart14_rts: qup-uart14-rts { 3591 pins = "gpio57"; 3592 function = "qup16"; 3593 }; 3594 3595 qup_uart14_tx: qup-uart14-tx { 3596 pins = "gpio58"; 3597 function = "qup16"; 3598 }; 3599 3600 qup_uart14_rx: qup-uart14-rx { 3601 pins = "gpio59"; 3602 function = "qup16"; 3603 }; 3604 3605 qup_uart15_cts: qup-uart15-cts { 3606 pins = "gpio60"; 3607 function = "qup17"; 3608 }; 3609 3610 qup_uart15_rts: qup-uart15-rts { 3611 pins = "gpio61"; 3612 function = "qup17"; 3613 }; 3614 3615 qup_uart15_tx: qup-uart15-tx { 3616 pins = "gpio62"; 3617 function = "qup17"; 3618 }; 3619 3620 qup_uart15_rx: qup-uart15-rx { 3621 pins = "gpio63"; 3622 function = "qup17"; 3623 }; 3624 }; 3625 3626 imem@146a5000 { 3627 compatible = "qcom,sc7280-imem", "syscon"; 3628 reg = <0 0x146a5000 0 0x6000>; 3629 3630 #address-cells = <1>; 3631 #size-cells = <1>; 3632 3633 ranges = <0 0 0x146a5000 0x6000>; 3634 3635 pil-reloc@594c { 3636 compatible = "qcom,pil-reloc-info"; 3637 reg = <0x594c 0xc8>; 3638 }; 3639 }; 3640 3641 apps_smmu: iommu@15000000 { 3642 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3643 reg = <0 0x15000000 0 0x100000>; 3644 #iommu-cells = <2>; 3645 #global-interrupts = <1>; 3646 dma-coherent; 3647 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3728 }; 3729 3730 intc: interrupt-controller@17a00000 { 3731 compatible = "arm,gic-v3"; 3732 #address-cells = <2>; 3733 #size-cells = <2>; 3734 ranges; 3735 #interrupt-cells = <3>; 3736 interrupt-controller; 3737 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3738 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3739 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3740 3741 gic-its@17a40000 { 3742 compatible = "arm,gic-v3-its"; 3743 msi-controller; 3744 #msi-cells = <1>; 3745 reg = <0 0x17a40000 0 0x20000>; 3746 status = "disabled"; 3747 }; 3748 }; 3749 3750 watchdog@17c10000 { 3751 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3752 reg = <0 0x17c10000 0 0x1000>; 3753 clocks = <&sleep_clk>; 3754 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3755 }; 3756 3757 timer@17c20000 { 3758 #address-cells = <2>; 3759 #size-cells = <2>; 3760 ranges; 3761 compatible = "arm,armv7-timer-mem"; 3762 reg = <0 0x17c20000 0 0x1000>; 3763 3764 frame@17c21000 { 3765 frame-number = <0>; 3766 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3768 reg = <0 0x17c21000 0 0x1000>, 3769 <0 0x17c22000 0 0x1000>; 3770 }; 3771 3772 frame@17c23000 { 3773 frame-number = <1>; 3774 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3775 reg = <0 0x17c23000 0 0x1000>; 3776 status = "disabled"; 3777 }; 3778 3779 frame@17c25000 { 3780 frame-number = <2>; 3781 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3782 reg = <0 0x17c25000 0 0x1000>; 3783 status = "disabled"; 3784 }; 3785 3786 frame@17c27000 { 3787 frame-number = <3>; 3788 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3789 reg = <0 0x17c27000 0 0x1000>; 3790 status = "disabled"; 3791 }; 3792 3793 frame@17c29000 { 3794 frame-number = <4>; 3795 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3796 reg = <0 0x17c29000 0 0x1000>; 3797 status = "disabled"; 3798 }; 3799 3800 frame@17c2b000 { 3801 frame-number = <5>; 3802 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3803 reg = <0 0x17c2b000 0 0x1000>; 3804 status = "disabled"; 3805 }; 3806 3807 frame@17c2d000 { 3808 frame-number = <6>; 3809 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3810 reg = <0 0x17c2d000 0 0x1000>; 3811 status = "disabled"; 3812 }; 3813 }; 3814 3815 apps_rsc: rsc@18200000 { 3816 compatible = "qcom,rpmh-rsc"; 3817 reg = <0 0x18200000 0 0x10000>, 3818 <0 0x18210000 0 0x10000>, 3819 <0 0x18220000 0 0x10000>; 3820 reg-names = "drv-0", "drv-1", "drv-2"; 3821 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3824 qcom,tcs-offset = <0xd00>; 3825 qcom,drv-id = <2>; 3826 qcom,tcs-config = <ACTIVE_TCS 2>, 3827 <SLEEP_TCS 3>, 3828 <WAKE_TCS 3>, 3829 <CONTROL_TCS 1>; 3830 3831 apps_bcm_voter: bcm-voter { 3832 compatible = "qcom,bcm-voter"; 3833 }; 3834 3835 rpmhpd: power-controller { 3836 compatible = "qcom,sc7280-rpmhpd"; 3837 #power-domain-cells = <1>; 3838 operating-points-v2 = <&rpmhpd_opp_table>; 3839 3840 rpmhpd_opp_table: opp-table { 3841 compatible = "operating-points-v2"; 3842 3843 rpmhpd_opp_ret: opp1 { 3844 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3845 }; 3846 3847 rpmhpd_opp_low_svs: opp2 { 3848 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3849 }; 3850 3851 rpmhpd_opp_svs: opp3 { 3852 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3853 }; 3854 3855 rpmhpd_opp_svs_l1: opp4 { 3856 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3857 }; 3858 3859 rpmhpd_opp_svs_l2: opp5 { 3860 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3861 }; 3862 3863 rpmhpd_opp_nom: opp6 { 3864 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3865 }; 3866 3867 rpmhpd_opp_nom_l1: opp7 { 3868 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3869 }; 3870 3871 rpmhpd_opp_turbo: opp8 { 3872 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3873 }; 3874 3875 rpmhpd_opp_turbo_l1: opp9 { 3876 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3877 }; 3878 }; 3879 }; 3880 3881 rpmhcc: clock-controller { 3882 compatible = "qcom,sc7280-rpmh-clk"; 3883 clocks = <&xo_board>; 3884 clock-names = "xo"; 3885 #clock-cells = <1>; 3886 }; 3887 }; 3888 3889 cpufreq_hw: cpufreq@18591000 { 3890 compatible = "qcom,cpufreq-epss"; 3891 reg = <0 0x18591000 0 0x1000>, 3892 <0 0x18592000 0 0x1000>, 3893 <0 0x18593000 0 0x1000>; 3894 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3895 clock-names = "xo", "alternate"; 3896 #freq-domain-cells = <1>; 3897 }; 3898 }; 3899 3900 thermal_zones: thermal-zones { 3901 cpu0-thermal { 3902 polling-delay-passive = <250>; 3903 polling-delay = <0>; 3904 3905 thermal-sensors = <&tsens0 1>; 3906 3907 trips { 3908 cpu0_alert0: trip-point0 { 3909 temperature = <90000>; 3910 hysteresis = <2000>; 3911 type = "passive"; 3912 }; 3913 3914 cpu0_alert1: trip-point1 { 3915 temperature = <95000>; 3916 hysteresis = <2000>; 3917 type = "passive"; 3918 }; 3919 3920 cpu0_crit: cpu-crit { 3921 temperature = <110000>; 3922 hysteresis = <0>; 3923 type = "critical"; 3924 }; 3925 }; 3926 3927 cooling-maps { 3928 map0 { 3929 trip = <&cpu0_alert0>; 3930 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3934 }; 3935 map1 { 3936 trip = <&cpu0_alert1>; 3937 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3941 }; 3942 }; 3943 }; 3944 3945 cpu1-thermal { 3946 polling-delay-passive = <250>; 3947 polling-delay = <0>; 3948 3949 thermal-sensors = <&tsens0 2>; 3950 3951 trips { 3952 cpu1_alert0: trip-point0 { 3953 temperature = <90000>; 3954 hysteresis = <2000>; 3955 type = "passive"; 3956 }; 3957 3958 cpu1_alert1: trip-point1 { 3959 temperature = <95000>; 3960 hysteresis = <2000>; 3961 type = "passive"; 3962 }; 3963 3964 cpu1_crit: cpu-crit { 3965 temperature = <110000>; 3966 hysteresis = <0>; 3967 type = "critical"; 3968 }; 3969 }; 3970 3971 cooling-maps { 3972 map0 { 3973 trip = <&cpu1_alert0>; 3974 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3978 }; 3979 map1 { 3980 trip = <&cpu1_alert1>; 3981 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3985 }; 3986 }; 3987 }; 3988 3989 cpu2-thermal { 3990 polling-delay-passive = <250>; 3991 polling-delay = <0>; 3992 3993 thermal-sensors = <&tsens0 3>; 3994 3995 trips { 3996 cpu2_alert0: trip-point0 { 3997 temperature = <90000>; 3998 hysteresis = <2000>; 3999 type = "passive"; 4000 }; 4001 4002 cpu2_alert1: trip-point1 { 4003 temperature = <95000>; 4004 hysteresis = <2000>; 4005 type = "passive"; 4006 }; 4007 4008 cpu2_crit: cpu-crit { 4009 temperature = <110000>; 4010 hysteresis = <0>; 4011 type = "critical"; 4012 }; 4013 }; 4014 4015 cooling-maps { 4016 map0 { 4017 trip = <&cpu2_alert0>; 4018 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4022 }; 4023 map1 { 4024 trip = <&cpu2_alert1>; 4025 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4029 }; 4030 }; 4031 }; 4032 4033 cpu3-thermal { 4034 polling-delay-passive = <250>; 4035 polling-delay = <0>; 4036 4037 thermal-sensors = <&tsens0 4>; 4038 4039 trips { 4040 cpu3_alert0: trip-point0 { 4041 temperature = <90000>; 4042 hysteresis = <2000>; 4043 type = "passive"; 4044 }; 4045 4046 cpu3_alert1: trip-point1 { 4047 temperature = <95000>; 4048 hysteresis = <2000>; 4049 type = "passive"; 4050 }; 4051 4052 cpu3_crit: cpu-crit { 4053 temperature = <110000>; 4054 hysteresis = <0>; 4055 type = "critical"; 4056 }; 4057 }; 4058 4059 cooling-maps { 4060 map0 { 4061 trip = <&cpu3_alert0>; 4062 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4063 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4066 }; 4067 map1 { 4068 trip = <&cpu3_alert1>; 4069 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4073 }; 4074 }; 4075 }; 4076 4077 cpu4-thermal { 4078 polling-delay-passive = <250>; 4079 polling-delay = <0>; 4080 4081 thermal-sensors = <&tsens0 7>; 4082 4083 trips { 4084 cpu4_alert0: trip-point0 { 4085 temperature = <90000>; 4086 hysteresis = <2000>; 4087 type = "passive"; 4088 }; 4089 4090 cpu4_alert1: trip-point1 { 4091 temperature = <95000>; 4092 hysteresis = <2000>; 4093 type = "passive"; 4094 }; 4095 4096 cpu4_crit: cpu-crit { 4097 temperature = <110000>; 4098 hysteresis = <0>; 4099 type = "critical"; 4100 }; 4101 }; 4102 4103 cooling-maps { 4104 map0 { 4105 trip = <&cpu4_alert0>; 4106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4110 }; 4111 map1 { 4112 trip = <&cpu4_alert1>; 4113 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4117 }; 4118 }; 4119 }; 4120 4121 cpu5-thermal { 4122 polling-delay-passive = <250>; 4123 polling-delay = <0>; 4124 4125 thermal-sensors = <&tsens0 8>; 4126 4127 trips { 4128 cpu5_alert0: trip-point0 { 4129 temperature = <90000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 cpu5_alert1: trip-point1 { 4135 temperature = <95000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu5_crit: cpu-crit { 4141 temperature = <110000>; 4142 hysteresis = <0>; 4143 type = "critical"; 4144 }; 4145 }; 4146 4147 cooling-maps { 4148 map0 { 4149 trip = <&cpu5_alert0>; 4150 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 map1 { 4156 trip = <&cpu5_alert1>; 4157 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4161 }; 4162 }; 4163 }; 4164 4165 cpu6-thermal { 4166 polling-delay-passive = <250>; 4167 polling-delay = <0>; 4168 4169 thermal-sensors = <&tsens0 9>; 4170 4171 trips { 4172 cpu6_alert0: trip-point0 { 4173 temperature = <90000>; 4174 hysteresis = <2000>; 4175 type = "passive"; 4176 }; 4177 4178 cpu6_alert1: trip-point1 { 4179 temperature = <95000>; 4180 hysteresis = <2000>; 4181 type = "passive"; 4182 }; 4183 4184 cpu6_crit: cpu-crit { 4185 temperature = <110000>; 4186 hysteresis = <0>; 4187 type = "critical"; 4188 }; 4189 }; 4190 4191 cooling-maps { 4192 map0 { 4193 trip = <&cpu6_alert0>; 4194 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4198 }; 4199 map1 { 4200 trip = <&cpu6_alert1>; 4201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4205 }; 4206 }; 4207 }; 4208 4209 cpu7-thermal { 4210 polling-delay-passive = <250>; 4211 polling-delay = <0>; 4212 4213 thermal-sensors = <&tsens0 10>; 4214 4215 trips { 4216 cpu7_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "passive"; 4220 }; 4221 4222 cpu7_alert1: trip-point1 { 4223 temperature = <95000>; 4224 hysteresis = <2000>; 4225 type = "passive"; 4226 }; 4227 4228 cpu7_crit: cpu-crit { 4229 temperature = <110000>; 4230 hysteresis = <0>; 4231 type = "critical"; 4232 }; 4233 }; 4234 4235 cooling-maps { 4236 map0 { 4237 trip = <&cpu7_alert0>; 4238 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242 }; 4243 map1 { 4244 trip = <&cpu7_alert1>; 4245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4249 }; 4250 }; 4251 }; 4252 4253 cpu8-thermal { 4254 polling-delay-passive = <250>; 4255 polling-delay = <0>; 4256 4257 thermal-sensors = <&tsens0 11>; 4258 4259 trips { 4260 cpu8_alert0: trip-point0 { 4261 temperature = <90000>; 4262 hysteresis = <2000>; 4263 type = "passive"; 4264 }; 4265 4266 cpu8_alert1: trip-point1 { 4267 temperature = <95000>; 4268 hysteresis = <2000>; 4269 type = "passive"; 4270 }; 4271 4272 cpu8_crit: cpu-crit { 4273 temperature = <110000>; 4274 hysteresis = <0>; 4275 type = "critical"; 4276 }; 4277 }; 4278 4279 cooling-maps { 4280 map0 { 4281 trip = <&cpu8_alert0>; 4282 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 map1 { 4288 trip = <&cpu8_alert1>; 4289 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4293 }; 4294 }; 4295 }; 4296 4297 cpu9-thermal { 4298 polling-delay-passive = <250>; 4299 polling-delay = <0>; 4300 4301 thermal-sensors = <&tsens0 12>; 4302 4303 trips { 4304 cpu9_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <2000>; 4307 type = "passive"; 4308 }; 4309 4310 cpu9_alert1: trip-point1 { 4311 temperature = <95000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu9_crit: cpu-crit { 4317 temperature = <110000>; 4318 hysteresis = <0>; 4319 type = "critical"; 4320 }; 4321 }; 4322 4323 cooling-maps { 4324 map0 { 4325 trip = <&cpu9_alert0>; 4326 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4327 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4330 }; 4331 map1 { 4332 trip = <&cpu9_alert1>; 4333 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4337 }; 4338 }; 4339 }; 4340 4341 cpu10-thermal { 4342 polling-delay-passive = <250>; 4343 polling-delay = <0>; 4344 4345 thermal-sensors = <&tsens0 13>; 4346 4347 trips { 4348 cpu10_alert0: trip-point0 { 4349 temperature = <90000>; 4350 hysteresis = <2000>; 4351 type = "passive"; 4352 }; 4353 4354 cpu10_alert1: trip-point1 { 4355 temperature = <95000>; 4356 hysteresis = <2000>; 4357 type = "passive"; 4358 }; 4359 4360 cpu10_crit: cpu-crit { 4361 temperature = <110000>; 4362 hysteresis = <0>; 4363 type = "critical"; 4364 }; 4365 }; 4366 4367 cooling-maps { 4368 map0 { 4369 trip = <&cpu10_alert0>; 4370 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4374 }; 4375 map1 { 4376 trip = <&cpu10_alert1>; 4377 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4381 }; 4382 }; 4383 }; 4384 4385 cpu11-thermal { 4386 polling-delay-passive = <250>; 4387 polling-delay = <0>; 4388 4389 thermal-sensors = <&tsens0 14>; 4390 4391 trips { 4392 cpu11_alert0: trip-point0 { 4393 temperature = <90000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu11_alert1: trip-point1 { 4399 temperature = <95000>; 4400 hysteresis = <2000>; 4401 type = "passive"; 4402 }; 4403 4404 cpu11_crit: cpu-crit { 4405 temperature = <110000>; 4406 hysteresis = <0>; 4407 type = "critical"; 4408 }; 4409 }; 4410 4411 cooling-maps { 4412 map0 { 4413 trip = <&cpu11_alert0>; 4414 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4418 }; 4419 map1 { 4420 trip = <&cpu11_alert1>; 4421 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4425 }; 4426 }; 4427 }; 4428 4429 aoss0-thermal { 4430 polling-delay-passive = <0>; 4431 polling-delay = <0>; 4432 4433 thermal-sensors = <&tsens0 0>; 4434 4435 trips { 4436 aoss0_alert0: trip-point0 { 4437 temperature = <90000>; 4438 hysteresis = <2000>; 4439 type = "hot"; 4440 }; 4441 4442 aoss0_crit: aoss0-crit { 4443 temperature = <110000>; 4444 hysteresis = <0>; 4445 type = "critical"; 4446 }; 4447 }; 4448 }; 4449 4450 aoss1-thermal { 4451 polling-delay-passive = <0>; 4452 polling-delay = <0>; 4453 4454 thermal-sensors = <&tsens1 0>; 4455 4456 trips { 4457 aoss1_alert0: trip-point0 { 4458 temperature = <90000>; 4459 hysteresis = <2000>; 4460 type = "hot"; 4461 }; 4462 4463 aoss1_crit: aoss1-crit { 4464 temperature = <110000>; 4465 hysteresis = <0>; 4466 type = "critical"; 4467 }; 4468 }; 4469 }; 4470 4471 cpuss0-thermal { 4472 polling-delay-passive = <0>; 4473 polling-delay = <0>; 4474 4475 thermal-sensors = <&tsens0 5>; 4476 4477 trips { 4478 cpuss0_alert0: trip-point0 { 4479 temperature = <90000>; 4480 hysteresis = <2000>; 4481 type = "hot"; 4482 }; 4483 cpuss0_crit: cluster0-crit { 4484 temperature = <110000>; 4485 hysteresis = <0>; 4486 type = "critical"; 4487 }; 4488 }; 4489 }; 4490 4491 cpuss1-thermal { 4492 polling-delay-passive = <0>; 4493 polling-delay = <0>; 4494 4495 thermal-sensors = <&tsens0 6>; 4496 4497 trips { 4498 cpuss1_alert0: trip-point0 { 4499 temperature = <90000>; 4500 hysteresis = <2000>; 4501 type = "hot"; 4502 }; 4503 cpuss1_crit: cluster0-crit { 4504 temperature = <110000>; 4505 hysteresis = <0>; 4506 type = "critical"; 4507 }; 4508 }; 4509 }; 4510 4511 gpuss0-thermal { 4512 polling-delay-passive = <100>; 4513 polling-delay = <0>; 4514 4515 thermal-sensors = <&tsens1 1>; 4516 4517 trips { 4518 gpuss0_alert0: trip-point0 { 4519 temperature = <95000>; 4520 hysteresis = <2000>; 4521 type = "passive"; 4522 }; 4523 4524 gpuss0_crit: gpuss0-crit { 4525 temperature = <110000>; 4526 hysteresis = <0>; 4527 type = "critical"; 4528 }; 4529 }; 4530 4531 cooling-maps { 4532 map0 { 4533 trip = <&gpuss0_alert0>; 4534 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4535 }; 4536 }; 4537 }; 4538 4539 gpuss1-thermal { 4540 polling-delay-passive = <100>; 4541 polling-delay = <0>; 4542 4543 thermal-sensors = <&tsens1 2>; 4544 4545 trips { 4546 gpuss1_alert0: trip-point0 { 4547 temperature = <95000>; 4548 hysteresis = <2000>; 4549 type = "passive"; 4550 }; 4551 4552 gpuss1_crit: gpuss1-crit { 4553 temperature = <110000>; 4554 hysteresis = <0>; 4555 type = "critical"; 4556 }; 4557 }; 4558 4559 cooling-maps { 4560 map0 { 4561 trip = <&gpuss1_alert0>; 4562 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4563 }; 4564 }; 4565 }; 4566 4567 nspss0-thermal { 4568 polling-delay-passive = <0>; 4569 polling-delay = <0>; 4570 4571 thermal-sensors = <&tsens1 3>; 4572 4573 trips { 4574 nspss0_alert0: trip-point0 { 4575 temperature = <90000>; 4576 hysteresis = <2000>; 4577 type = "hot"; 4578 }; 4579 4580 nspss0_crit: nspss0-crit { 4581 temperature = <110000>; 4582 hysteresis = <0>; 4583 type = "critical"; 4584 }; 4585 }; 4586 }; 4587 4588 nspss1-thermal { 4589 polling-delay-passive = <0>; 4590 polling-delay = <0>; 4591 4592 thermal-sensors = <&tsens1 4>; 4593 4594 trips { 4595 nspss1_alert0: trip-point0 { 4596 temperature = <90000>; 4597 hysteresis = <2000>; 4598 type = "hot"; 4599 }; 4600 4601 nspss1_crit: nspss1-crit { 4602 temperature = <110000>; 4603 hysteresis = <0>; 4604 type = "critical"; 4605 }; 4606 }; 4607 }; 4608 4609 video-thermal { 4610 polling-delay-passive = <0>; 4611 polling-delay = <0>; 4612 4613 thermal-sensors = <&tsens1 5>; 4614 4615 trips { 4616 video_alert0: trip-point0 { 4617 temperature = <90000>; 4618 hysteresis = <2000>; 4619 type = "hot"; 4620 }; 4621 4622 video_crit: video-crit { 4623 temperature = <110000>; 4624 hysteresis = <0>; 4625 type = "critical"; 4626 }; 4627 }; 4628 }; 4629 4630 ddr-thermal { 4631 polling-delay-passive = <0>; 4632 polling-delay = <0>; 4633 4634 thermal-sensors = <&tsens1 6>; 4635 4636 trips { 4637 ddr_alert0: trip-point0 { 4638 temperature = <90000>; 4639 hysteresis = <2000>; 4640 type = "hot"; 4641 }; 4642 4643 ddr_crit: ddr-crit { 4644 temperature = <110000>; 4645 hysteresis = <0>; 4646 type = "critical"; 4647 }; 4648 }; 4649 }; 4650 4651 mdmss0-thermal { 4652 polling-delay-passive = <0>; 4653 polling-delay = <0>; 4654 4655 thermal-sensors = <&tsens1 7>; 4656 4657 trips { 4658 mdmss0_alert0: trip-point0 { 4659 temperature = <90000>; 4660 hysteresis = <2000>; 4661 type = "hot"; 4662 }; 4663 4664 mdmss0_crit: mdmss0-crit { 4665 temperature = <110000>; 4666 hysteresis = <0>; 4667 type = "critical"; 4668 }; 4669 }; 4670 }; 4671 4672 mdmss1-thermal { 4673 polling-delay-passive = <0>; 4674 polling-delay = <0>; 4675 4676 thermal-sensors = <&tsens1 8>; 4677 4678 trips { 4679 mdmss1_alert0: trip-point0 { 4680 temperature = <90000>; 4681 hysteresis = <2000>; 4682 type = "hot"; 4683 }; 4684 4685 mdmss1_crit: mdmss1-crit { 4686 temperature = <110000>; 4687 hysteresis = <0>; 4688 type = "critical"; 4689 }; 4690 }; 4691 }; 4692 4693 mdmss2-thermal { 4694 polling-delay-passive = <0>; 4695 polling-delay = <0>; 4696 4697 thermal-sensors = <&tsens1 9>; 4698 4699 trips { 4700 mdmss2_alert0: trip-point0 { 4701 temperature = <90000>; 4702 hysteresis = <2000>; 4703 type = "hot"; 4704 }; 4705 4706 mdmss2_crit: mdmss2-crit { 4707 temperature = <110000>; 4708 hysteresis = <0>; 4709 type = "critical"; 4710 }; 4711 }; 4712 }; 4713 4714 mdmss3-thermal { 4715 polling-delay-passive = <0>; 4716 polling-delay = <0>; 4717 4718 thermal-sensors = <&tsens1 10>; 4719 4720 trips { 4721 mdmss3_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "hot"; 4725 }; 4726 4727 mdmss3_crit: mdmss3-crit { 4728 temperature = <110000>; 4729 hysteresis = <0>; 4730 type = "critical"; 4731 }; 4732 }; 4733 }; 4734 4735 camera0-thermal { 4736 polling-delay-passive = <0>; 4737 polling-delay = <0>; 4738 4739 thermal-sensors = <&tsens1 11>; 4740 4741 trips { 4742 camera0_alert0: trip-point0 { 4743 temperature = <90000>; 4744 hysteresis = <2000>; 4745 type = "hot"; 4746 }; 4747 4748 camera0_crit: camera0-crit { 4749 temperature = <110000>; 4750 hysteresis = <0>; 4751 type = "critical"; 4752 }; 4753 }; 4754 }; 4755 }; 4756 4757 timer { 4758 compatible = "arm,armv8-timer"; 4759 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4760 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4761 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4762 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4763 }; 4764}; 4765