1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 video_mem: memory@8b200000 { 133 reg = <0x0 0x8b200000 0x0 0x500000>; 134 no-map; 135 }; 136 137 ipa_fw_mem: memory@8b700000 { 138 reg = <0 0x8b700000 0 0x10000>; 139 no-map; 140 }; 141 142 rmtfs_mem: memory@9c900000 { 143 compatible = "qcom,rmtfs-mem"; 144 reg = <0x0 0x9c900000 0x0 0x280000>; 145 no-map; 146 147 qcom,client-id = <1>; 148 qcom,vmid = <15>; 149 }; 150 }; 151 152 cpus { 153 #address-cells = <2>; 154 #size-cells = <0>; 155 156 CPU0: cpu@0 { 157 device_type = "cpu"; 158 compatible = "arm,kryo"; 159 reg = <0x0 0x0>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 #cooling-cells = <2>; 167 L2_0: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 L3_0: l3-cache { 171 compatible = "cache"; 172 }; 173 }; 174 }; 175 176 CPU1: cpu@100 { 177 device_type = "cpu"; 178 compatible = "arm,kryo"; 179 reg = <0x0 0x100>; 180 enable-method = "psci"; 181 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 182 &LITTLE_CPU_SLEEP_1 183 &CLUSTER_SLEEP_0>; 184 next-level-cache = <&L2_100>; 185 qcom,freq-domain = <&cpufreq_hw 0>; 186 #cooling-cells = <2>; 187 L2_100: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU2: cpu@200 { 194 device_type = "cpu"; 195 compatible = "arm,kryo"; 196 reg = <0x0 0x200>; 197 enable-method = "psci"; 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 199 &LITTLE_CPU_SLEEP_1 200 &CLUSTER_SLEEP_0>; 201 next-level-cache = <&L2_200>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_200: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU3: cpu@300 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x300>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_300>; 219 qcom,freq-domain = <&cpufreq_hw 0>; 220 #cooling-cells = <2>; 221 L2_300: l2-cache { 222 compatible = "cache"; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU4: cpu@400 { 228 device_type = "cpu"; 229 compatible = "arm,kryo"; 230 reg = <0x0 0x400>; 231 enable-method = "psci"; 232 cpu-idle-states = <&BIG_CPU_SLEEP_0 233 &BIG_CPU_SLEEP_1 234 &CLUSTER_SLEEP_0>; 235 next-level-cache = <&L2_400>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 #cooling-cells = <2>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "arm,kryo"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 250 &BIG_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 next-level-cache = <&L2_500>; 253 qcom,freq-domain = <&cpufreq_hw 1>; 254 #cooling-cells = <2>; 255 L2_500: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU6: cpu@600 { 262 device_type = "cpu"; 263 compatible = "arm,kryo"; 264 reg = <0x0 0x600>; 265 enable-method = "psci"; 266 cpu-idle-states = <&BIG_CPU_SLEEP_0 267 &BIG_CPU_SLEEP_1 268 &CLUSTER_SLEEP_0>; 269 next-level-cache = <&L2_600>; 270 qcom,freq-domain = <&cpufreq_hw 1>; 271 #cooling-cells = <2>; 272 L2_600: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "arm,kryo"; 281 reg = <0x0 0x700>; 282 enable-method = "psci"; 283 cpu-idle-states = <&BIG_CPU_SLEEP_0 284 &BIG_CPU_SLEEP_1 285 &CLUSTER_SLEEP_0>; 286 next-level-cache = <&L2_700>; 287 qcom,freq-domain = <&cpufreq_hw 2>; 288 #cooling-cells = <2>; 289 L2_700: l2-cache { 290 compatible = "cache"; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "little-power-down"; 337 arm,psci-suspend-param = <0x40000003>; 338 entry-latency-us = <549>; 339 exit-latency-us = <901>; 340 min-residency-us = <1774>; 341 local-timer-stop; 342 }; 343 344 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "little-rail-power-down"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <915>; 350 min-residency-us = <4001>; 351 local-timer-stop; 352 }; 353 354 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 355 compatible = "arm,idle-state"; 356 idle-state-name = "big-power-down"; 357 arm,psci-suspend-param = <0x40000003>; 358 entry-latency-us = <523>; 359 exit-latency-us = <1244>; 360 min-residency-us = <2207>; 361 local-timer-stop; 362 }; 363 364 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 365 compatible = "arm,idle-state"; 366 idle-state-name = "big-rail-power-down"; 367 arm,psci-suspend-param = <0x40000004>; 368 entry-latency-us = <526>; 369 exit-latency-us = <1854>; 370 min-residency-us = <5555>; 371 local-timer-stop; 372 }; 373 374 CLUSTER_SLEEP_0: cluster-sleep-0 { 375 compatible = "arm,idle-state"; 376 idle-state-name = "cluster-power-down"; 377 arm,psci-suspend-param = <0x40003444>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9926>; 381 local-timer-stop; 382 }; 383 }; 384 }; 385 386 memory@80000000 { 387 device_type = "memory"; 388 /* We expect the bootloader to fill in the size */ 389 reg = <0 0x80000000 0 0>; 390 }; 391 392 firmware { 393 scm { 394 compatible = "qcom,scm-sc7280", "qcom,scm"; 395 }; 396 }; 397 398 clk_virt: interconnect { 399 compatible = "qcom,sc7280-clk-virt"; 400 #interconnect-cells = <2>; 401 qcom,bcm-voters = <&apps_bcm_voter>; 402 }; 403 404 smem { 405 compatible = "qcom,smem"; 406 memory-region = <&smem_mem>; 407 hwlocks = <&tcsr_mutex 3>; 408 }; 409 410 smp2p-adsp { 411 compatible = "qcom,smp2p"; 412 qcom,smem = <443>, <429>; 413 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 414 IPCC_MPROC_SIGNAL_SMP2P 415 IRQ_TYPE_EDGE_RISING>; 416 mboxes = <&ipcc IPCC_CLIENT_LPASS 417 IPCC_MPROC_SIGNAL_SMP2P>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <2>; 421 422 adsp_smp2p_out: master-kernel { 423 qcom,entry-name = "master-kernel"; 424 #qcom,smem-state-cells = <1>; 425 }; 426 427 adsp_smp2p_in: slave-kernel { 428 qcom,entry-name = "slave-kernel"; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 smp2p-cdsp { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <94>, <432>; 437 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 438 IPCC_MPROC_SIGNAL_SMP2P 439 IRQ_TYPE_EDGE_RISING>; 440 mboxes = <&ipcc IPCC_CLIENT_CDSP 441 IPCC_MPROC_SIGNAL_SMP2P>; 442 443 qcom,local-pid = <0>; 444 qcom,remote-pid = <5>; 445 446 cdsp_smp2p_out: master-kernel { 447 qcom,entry-name = "master-kernel"; 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 cdsp_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 smp2p-mpss { 459 compatible = "qcom,smp2p"; 460 qcom,smem = <435>, <428>; 461 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 462 IPCC_MPROC_SIGNAL_SMP2P 463 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&ipcc IPCC_CLIENT_MPSS 465 IPCC_MPROC_SIGNAL_SMP2P>; 466 467 qcom,local-pid = <0>; 468 qcom,remote-pid = <1>; 469 470 modem_smp2p_out: master-kernel { 471 qcom,entry-name = "master-kernel"; 472 #qcom,smem-state-cells = <1>; 473 }; 474 475 modem_smp2p_in: slave-kernel { 476 qcom,entry-name = "slave-kernel"; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 ipa_smp2p_out: ipa-ap-to-modem { 482 qcom,entry-name = "ipa"; 483 #qcom,smem-state-cells = <1>; 484 }; 485 486 ipa_smp2p_in: ipa-modem-to-ap { 487 qcom,entry-name = "ipa"; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 }; 492 493 smp2p-wpss { 494 compatible = "qcom,smp2p"; 495 qcom,smem = <617>, <616>; 496 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 497 IPCC_MPROC_SIGNAL_SMP2P 498 IRQ_TYPE_EDGE_RISING>; 499 mboxes = <&ipcc IPCC_CLIENT_WPSS 500 IPCC_MPROC_SIGNAL_SMP2P>; 501 502 qcom,local-pid = <0>; 503 qcom,remote-pid = <13>; 504 505 wpss_smp2p_out: master-kernel { 506 qcom,entry-name = "master-kernel"; 507 #qcom,smem-state-cells = <1>; 508 }; 509 510 wpss_smp2p_in: slave-kernel { 511 qcom,entry-name = "slave-kernel"; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 }; 516 517 pmu { 518 compatible = "arm,armv8-pmuv3"; 519 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 520 }; 521 522 psci { 523 compatible = "arm,psci-1.0"; 524 method = "smc"; 525 }; 526 527 qspi_opp_table: qspi-opp-table { 528 compatible = "operating-points-v2"; 529 530 opp-75000000 { 531 opp-hz = /bits/ 64 <75000000>; 532 required-opps = <&rpmhpd_opp_low_svs>; 533 }; 534 535 opp-150000000 { 536 opp-hz = /bits/ 64 <150000000>; 537 required-opps = <&rpmhpd_opp_svs>; 538 }; 539 540 opp-200000000 { 541 opp-hz = /bits/ 64 <200000000>; 542 required-opps = <&rpmhpd_opp_svs_l1>; 543 }; 544 545 opp-300000000 { 546 opp-hz = /bits/ 64 <300000000>; 547 required-opps = <&rpmhpd_opp_nom>; 548 }; 549 }; 550 551 qup_opp_table: qup-opp-table { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 564 opp-128000000 { 565 opp-hz = /bits/ 64 <128000000>; 566 required-opps = <&rpmhpd_opp_nom>; 567 }; 568 }; 569 570 soc: soc@0 { 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges = <0 0 0 0 0x10 0>; 574 dma-ranges = <0 0 0 0 0x10 0>; 575 compatible = "simple-bus"; 576 577 gcc: clock-controller@100000 { 578 compatible = "qcom,gcc-sc7280"; 579 reg = <0 0x00100000 0 0x1f0000>; 580 clocks = <&rpmhcc RPMH_CXO_CLK>, 581 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 582 <0>, <&pcie1_lane 0>, 583 <0>, <0>, <0>, <0>; 584 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 585 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 586 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 587 "ufs_phy_tx_symbol_0_clk", 588 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 589 #clock-cells = <1>; 590 #reset-cells = <1>; 591 #power-domain-cells = <1>; 592 }; 593 594 ipcc: mailbox@408000 { 595 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 596 reg = <0 0x00408000 0 0x1000>; 597 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-controller; 599 #interrupt-cells = <3>; 600 #mbox-cells = <2>; 601 }; 602 603 qfprom: efuse@784000 { 604 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 605 reg = <0 0x00784000 0 0xa20>, 606 <0 0x00780000 0 0xa20>, 607 <0 0x00782000 0 0x120>, 608 <0 0x00786000 0 0x1fff>; 609 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 610 clock-names = "core"; 611 power-domains = <&rpmhpd SC7280_MX>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 }; 615 616 sdhc_1: sdhci@7c4000 { 617 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 618 status = "disabled"; 619 620 reg = <0 0x007c4000 0 0x1000>, 621 <0 0x007c5000 0 0x1000>; 622 reg-names = "hc", "cqhci"; 623 624 iommus = <&apps_smmu 0xc0 0x0>; 625 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "hc_irq", "pwr_irq"; 628 629 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 630 <&gcc GCC_SDCC1_AHB_CLK>, 631 <&rpmhcc RPMH_CXO_CLK>; 632 clock-names = "core", "iface", "xo"; 633 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 635 interconnect-names = "sdhc-ddr","cpu-sdhc"; 636 power-domains = <&rpmhpd SC7280_CX>; 637 operating-points-v2 = <&sdhc1_opp_table>; 638 639 bus-width = <8>; 640 supports-cqe; 641 642 qcom,dll-config = <0x0007642c>; 643 qcom,ddr-config = <0x80040868>; 644 645 mmc-ddr-1_8v; 646 mmc-hs200-1_8v; 647 mmc-hs400-1_8v; 648 mmc-hs400-enhanced-strobe; 649 650 sdhc1_opp_table: opp-table { 651 compatible = "operating-points-v2"; 652 653 opp-100000000 { 654 opp-hz = /bits/ 64 <100000000>; 655 required-opps = <&rpmhpd_opp_low_svs>; 656 opp-peak-kBps = <1800000 400000>; 657 opp-avg-kBps = <100000 0>; 658 }; 659 660 opp-384000000 { 661 opp-hz = /bits/ 64 <384000000>; 662 required-opps = <&rpmhpd_opp_nom>; 663 opp-peak-kBps = <5400000 1600000>; 664 opp-avg-kBps = <390000 0>; 665 }; 666 }; 667 668 }; 669 670 qupv3_id_0: geniqup@9c0000 { 671 compatible = "qcom,geni-se-qup"; 672 reg = <0 0x009c0000 0 0x2000>; 673 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 674 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 675 clock-names = "m-ahb", "s-ahb"; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 ranges; 679 iommus = <&apps_smmu 0x123 0x0>; 680 status = "disabled"; 681 682 i2c0: i2c@980000 { 683 compatible = "qcom,geni-i2c"; 684 reg = <0 0x00980000 0 0x4000>; 685 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 686 clock-names = "se"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&qup_i2c0_data_clk>; 689 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 694 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 695 interconnect-names = "qup-core", "qup-config", 696 "qup-memory"; 697 status = "disabled"; 698 }; 699 700 spi0: spi@980000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0 0x00980000 0 0x4000>; 703 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 704 clock-names = "se"; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 707 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 power-domains = <&rpmhpd SC7280_CX>; 711 operating-points-v2 = <&qup_opp_table>; 712 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 714 interconnect-names = "qup-core", "qup-config"; 715 status = "disabled"; 716 }; 717 718 uart0: serial@980000 { 719 compatible = "qcom,geni-uart"; 720 reg = <0 0x00980000 0 0x4000>; 721 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 722 clock-names = "se"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 725 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 726 power-domains = <&rpmhpd SC7280_CX>; 727 operating-points-v2 = <&qup_opp_table>; 728 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 729 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 730 interconnect-names = "qup-core", "qup-config"; 731 status = "disabled"; 732 }; 733 734 i2c1: i2c@984000 { 735 compatible = "qcom,geni-i2c"; 736 reg = <0 0x00984000 0 0x4000>; 737 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 738 clock-names = "se"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&qup_i2c1_data_clk>; 741 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 745 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 746 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 747 interconnect-names = "qup-core", "qup-config", 748 "qup-memory"; 749 status = "disabled"; 750 }; 751 752 spi1: spi@984000 { 753 compatible = "qcom,geni-spi"; 754 reg = <0 0x00984000 0 0x4000>; 755 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 756 clock-names = "se"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 759 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 power-domains = <&rpmhpd SC7280_CX>; 763 operating-points-v2 = <&qup_opp_table>; 764 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 765 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 766 interconnect-names = "qup-core", "qup-config"; 767 status = "disabled"; 768 }; 769 770 uart1: serial@984000 { 771 compatible = "qcom,geni-uart"; 772 reg = <0 0x00984000 0 0x4000>; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 774 clock-names = "se"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 777 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 778 power-domains = <&rpmhpd SC7280_CX>; 779 operating-points-v2 = <&qup_opp_table>; 780 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 781 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 782 interconnect-names = "qup-core", "qup-config"; 783 status = "disabled"; 784 }; 785 786 i2c2: i2c@988000 { 787 compatible = "qcom,geni-i2c"; 788 reg = <0 0x00988000 0 0x4000>; 789 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 790 clock-names = "se"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&qup_i2c2_data_clk>; 793 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 798 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 799 interconnect-names = "qup-core", "qup-config", 800 "qup-memory"; 801 status = "disabled"; 802 }; 803 804 spi2: spi@988000 { 805 compatible = "qcom,geni-spi"; 806 reg = <0 0x00988000 0 0x4000>; 807 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 808 clock-names = "se"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 811 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 power-domains = <&rpmhpd SC7280_CX>; 815 operating-points-v2 = <&qup_opp_table>; 816 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 818 interconnect-names = "qup-core", "qup-config"; 819 status = "disabled"; 820 }; 821 822 uart2: serial@988000 { 823 compatible = "qcom,geni-uart"; 824 reg = <0 0x00988000 0 0x4000>; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 826 clock-names = "se"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 829 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd SC7280_CX>; 831 operating-points-v2 = <&qup_opp_table>; 832 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 833 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 834 interconnect-names = "qup-core", "qup-config"; 835 status = "disabled"; 836 }; 837 838 i2c3: i2c@98c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0098c000 0 0x4000>; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 842 clock-names = "se"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c3_data_clk>; 845 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 849 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 850 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 851 interconnect-names = "qup-core", "qup-config", 852 "qup-memory"; 853 status = "disabled"; 854 }; 855 856 spi3: spi@98c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0098c000 0 0x4000>; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 860 clock-names = "se"; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 863 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 power-domains = <&rpmhpd SC7280_CX>; 867 operating-points-v2 = <&qup_opp_table>; 868 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 870 interconnect-names = "qup-core", "qup-config"; 871 status = "disabled"; 872 }; 873 874 uart3: serial@98c000 { 875 compatible = "qcom,geni-uart"; 876 reg = <0 0x0098c000 0 0x4000>; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 878 clock-names = "se"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 881 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 882 power-domains = <&rpmhpd SC7280_CX>; 883 operating-points-v2 = <&qup_opp_table>; 884 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 886 interconnect-names = "qup-core", "qup-config"; 887 status = "disabled"; 888 }; 889 890 i2c4: i2c@990000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00990000 0 0x4000>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 894 clock-names = "se"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c4_data_clk>; 897 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 901 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 902 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 903 interconnect-names = "qup-core", "qup-config", 904 "qup-memory"; 905 status = "disabled"; 906 }; 907 908 spi4: spi@990000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0 0x00990000 0 0x4000>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 912 clock-names = "se"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 915 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 power-domains = <&rpmhpd SC7280_CX>; 919 operating-points-v2 = <&qup_opp_table>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 922 interconnect-names = "qup-core", "qup-config"; 923 status = "disabled"; 924 }; 925 926 uart4: serial@990000 { 927 compatible = "qcom,geni-uart"; 928 reg = <0 0x00990000 0 0x4000>; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 930 clock-names = "se"; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 933 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC7280_CX>; 935 operating-points-v2 = <&qup_opp_table>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 938 interconnect-names = "qup-core", "qup-config"; 939 status = "disabled"; 940 }; 941 942 i2c5: i2c@994000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0 0x00994000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 946 clock-names = "se"; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_i2c5_data_clk>; 949 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 953 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 954 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 955 interconnect-names = "qup-core", "qup-config", 956 "qup-memory"; 957 status = "disabled"; 958 }; 959 960 spi5: spi@994000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00994000 0 0x4000>; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 964 clock-names = "se"; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 967 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 power-domains = <&rpmhpd SC7280_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 uart5: serial@994000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00994000 0 0x4000>; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 982 clock-names = "se"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 985 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7280_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c6: i2c@998000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00998000 0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 998 clock-names = "se"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c6_data_clk>; 1001 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 status = "disabled"; 1010 }; 1011 1012 spi6: spi@998000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00998000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1016 clock-names = "se"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1019 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 power-domains = <&rpmhpd SC7280_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 uart6: serial@998000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0 0x00998000 0 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1034 clock-names = "se"; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1037 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1038 power-domains = <&rpmhpd SC7280_CX>; 1039 operating-points-v2 = <&qup_opp_table>; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1042 interconnect-names = "qup-core", "qup-config"; 1043 status = "disabled"; 1044 }; 1045 1046 i2c7: i2c@99c000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x0099c000 0 0x4000>; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1050 clock-names = "se"; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c7_data_clk>; 1053 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1057 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1058 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1059 interconnect-names = "qup-core", "qup-config", 1060 "qup-memory"; 1061 status = "disabled"; 1062 }; 1063 1064 spi7: spi@99c000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x0099c000 0 0x4000>; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1068 clock-names = "se"; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1071 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 power-domains = <&rpmhpd SC7280_CX>; 1075 operating-points-v2 = <&qup_opp_table>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 status = "disabled"; 1080 }; 1081 1082 uart7: serial@99c000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x0099c000 0 0x4000>; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1086 clock-names = "se"; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1089 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1090 power-domains = <&rpmhpd SC7280_CX>; 1091 operating-points-v2 = <&qup_opp_table>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 qupv3_id_1: geniqup@ac0000 { 1100 compatible = "qcom,geni-se-qup"; 1101 reg = <0 0x00ac0000 0 0x2000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1103 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1104 clock-names = "m-ahb", "s-ahb"; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 iommus = <&apps_smmu 0x43 0x0>; 1109 status = "disabled"; 1110 1111 i2c8: i2c@a80000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x00a80000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c8_data_clk>; 1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1123 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1124 interconnect-names = "qup-core", "qup-config", 1125 "qup-memory"; 1126 status = "disabled"; 1127 }; 1128 1129 spi8: spi@a80000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0 0x00a80000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1136 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 power-domains = <&rpmhpd SC7280_CX>; 1140 operating-points-v2 = <&qup_opp_table>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1143 interconnect-names = "qup-core", "qup-config"; 1144 status = "disabled"; 1145 }; 1146 1147 uart8: serial@a80000 { 1148 compatible = "qcom,geni-uart"; 1149 reg = <0 0x00a80000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1154 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC7280_CX>; 1156 operating-points-v2 = <&qup_opp_table>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1159 interconnect-names = "qup-core", "qup-config"; 1160 status = "disabled"; 1161 }; 1162 1163 i2c9: i2c@a84000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00a84000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1167 clock-names = "se"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c9_data_clk>; 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", 1177 "qup-memory"; 1178 status = "disabled"; 1179 }; 1180 1181 spi9: spi@a84000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00a84000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1188 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 power-domains = <&rpmhpd SC7280_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 uart9: serial@a84000 { 1200 compatible = "qcom,geni-uart"; 1201 reg = <0 0x00a84000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1203 clock-names = "se"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c10: i2c@a88000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00a88000 0 0x4000>; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1219 clock-names = "se"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_i2c10_data_clk>; 1222 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1227 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1228 interconnect-names = "qup-core", "qup-config", 1229 "qup-memory"; 1230 status = "disabled"; 1231 }; 1232 1233 spi10: spi@a88000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0 0x00a88000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1240 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 power-domains = <&rpmhpd SC7280_CX>; 1244 operating-points-v2 = <&qup_opp_table>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1247 interconnect-names = "qup-core", "qup-config"; 1248 status = "disabled"; 1249 }; 1250 1251 uart10: serial@a88000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0 0x00a88000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1258 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1259 power-domains = <&rpmhpd SC7280_CX>; 1260 operating-points-v2 = <&qup_opp_table>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1262 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1263 interconnect-names = "qup-core", "qup-config"; 1264 status = "disabled"; 1265 }; 1266 1267 i2c11: i2c@a8c000 { 1268 compatible = "qcom,geni-i2c"; 1269 reg = <0 0x00a8c000 0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1271 clock-names = "se"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_i2c11_data_clk>; 1274 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1279 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1280 interconnect-names = "qup-core", "qup-config", 1281 "qup-memory"; 1282 status = "disabled"; 1283 }; 1284 1285 spi11: spi@a8c000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00a8c000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1292 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 uart11: serial@a8c000 { 1304 compatible = "qcom,geni-uart"; 1305 reg = <0 0x00a8c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1310 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1311 power-domains = <&rpmhpd SC7280_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1315 interconnect-names = "qup-core", "qup-config"; 1316 status = "disabled"; 1317 }; 1318 1319 i2c12: i2c@a90000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0 0x00a90000 0 0x4000>; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1323 clock-names = "se"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_i2c12_data_clk>; 1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1331 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", 1333 "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 spi12: spi@a90000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0 0x00a90000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 power-domains = <&rpmhpd SC7280_CX>; 1348 operating-points-v2 = <&qup_opp_table>; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1350 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1351 interconnect-names = "qup-core", "qup-config"; 1352 status = "disabled"; 1353 }; 1354 1355 uart12: serial@a90000 { 1356 compatible = "qcom,geni-uart"; 1357 reg = <0 0x00a90000 0 0x4000>; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1359 clock-names = "se"; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1362 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1363 power-domains = <&rpmhpd SC7280_CX>; 1364 operating-points-v2 = <&qup_opp_table>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1367 interconnect-names = "qup-core", "qup-config"; 1368 status = "disabled"; 1369 }; 1370 1371 i2c13: i2c@a94000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00a94000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1375 clock-names = "se"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_i2c13_data_clk>; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1382 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1383 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1384 interconnect-names = "qup-core", "qup-config", 1385 "qup-memory"; 1386 status = "disabled"; 1387 }; 1388 1389 spi13: spi@a94000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a94000 0 0x4000>; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1393 clock-names = "se"; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1396 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 power-domains = <&rpmhpd SC7280_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 1407 uart13: serial@a94000 { 1408 compatible = "qcom,geni-uart"; 1409 reg = <0 0x00a94000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1414 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC7280_CX>; 1416 operating-points-v2 = <&qup_opp_table>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1419 interconnect-names = "qup-core", "qup-config"; 1420 status = "disabled"; 1421 }; 1422 1423 i2c14: i2c@a98000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x00a98000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1427 clock-names = "se"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_i2c14_data_clk>; 1430 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1435 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", 1437 "qup-memory"; 1438 status = "disabled"; 1439 }; 1440 1441 spi14: spi@a98000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a98000 0 0x4000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1445 clock-names = "se"; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1448 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&rpmhpd SC7280_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1455 interconnect-names = "qup-core", "qup-config"; 1456 status = "disabled"; 1457 }; 1458 1459 uart14: serial@a98000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00a98000 0 0x4000>; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1463 clock-names = "se"; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1466 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SC7280_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 status = "disabled"; 1473 }; 1474 1475 i2c15: i2c@a9c000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a9c000 0 0x4000>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1479 clock-names = "se"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c15_data_clk>; 1482 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", 1489 "qup-memory"; 1490 status = "disabled"; 1491 }; 1492 1493 spi15: spi@a9c000 { 1494 compatible = "qcom,geni-spi"; 1495 reg = <0 0x00a9c000 0 0x4000>; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1497 clock-names = "se"; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1500 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 status = "disabled"; 1509 }; 1510 1511 uart15: serial@a9c000 { 1512 compatible = "qcom,geni-uart"; 1513 reg = <0 0x00a9c000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1518 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC7280_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1523 interconnect-names = "qup-core", "qup-config"; 1524 status = "disabled"; 1525 }; 1526 }; 1527 1528 cnoc2: interconnect@1500000 { 1529 reg = <0 0x01500000 0 0x1000>; 1530 compatible = "qcom,sc7280-cnoc2"; 1531 #interconnect-cells = <2>; 1532 qcom,bcm-voters = <&apps_bcm_voter>; 1533 }; 1534 1535 cnoc3: interconnect@1502000 { 1536 reg = <0 0x01502000 0 0x1000>; 1537 compatible = "qcom,sc7280-cnoc3"; 1538 #interconnect-cells = <2>; 1539 qcom,bcm-voters = <&apps_bcm_voter>; 1540 }; 1541 1542 mc_virt: interconnect@1580000 { 1543 reg = <0 0x01580000 0 0x4>; 1544 compatible = "qcom,sc7280-mc-virt"; 1545 #interconnect-cells = <2>; 1546 qcom,bcm-voters = <&apps_bcm_voter>; 1547 }; 1548 1549 system_noc: interconnect@1680000 { 1550 reg = <0 0x01680000 0 0x15480>; 1551 compatible = "qcom,sc7280-system-noc"; 1552 #interconnect-cells = <2>; 1553 qcom,bcm-voters = <&apps_bcm_voter>; 1554 }; 1555 1556 aggre1_noc: interconnect@16e0000 { 1557 compatible = "qcom,sc7280-aggre1-noc"; 1558 reg = <0 0x016e0000 0 0x1c080>; 1559 #interconnect-cells = <2>; 1560 qcom,bcm-voters = <&apps_bcm_voter>; 1561 }; 1562 1563 aggre2_noc: interconnect@1700000 { 1564 reg = <0 0x01700000 0 0x2b080>; 1565 compatible = "qcom,sc7280-aggre2-noc"; 1566 #interconnect-cells = <2>; 1567 qcom,bcm-voters = <&apps_bcm_voter>; 1568 }; 1569 1570 mmss_noc: interconnect@1740000 { 1571 reg = <0 0x01740000 0 0x1e080>; 1572 compatible = "qcom,sc7280-mmss-noc"; 1573 #interconnect-cells = <2>; 1574 qcom,bcm-voters = <&apps_bcm_voter>; 1575 }; 1576 1577 pcie1: pci@1c08000 { 1578 compatible = "qcom,pcie-sc7280"; 1579 reg = <0 0x01c08000 0 0x3000>, 1580 <0 0x40000000 0 0xf1d>, 1581 <0 0x40000f20 0 0xa8>, 1582 <0 0x40001000 0 0x1000>, 1583 <0 0x40100000 0 0x100000>; 1584 1585 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1586 device_type = "pci"; 1587 linux,pci-domain = <1>; 1588 bus-range = <0x00 0xff>; 1589 num-lanes = <2>; 1590 1591 #address-cells = <3>; 1592 #size-cells = <2>; 1593 1594 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1595 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1596 1597 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1598 interrupt-names = "msi"; 1599 #interrupt-cells = <1>; 1600 interrupt-map-mask = <0 0 0 0x7>; 1601 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1602 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1604 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1605 1606 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1607 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1608 <&pcie1_lane 0>, 1609 <&rpmhcc RPMH_CXO_CLK>, 1610 <&gcc GCC_PCIE_1_AUX_CLK>, 1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1615 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1616 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1617 1618 clock-names = "pipe", 1619 "pipe_mux", 1620 "phy_pipe", 1621 "ref", 1622 "aux", 1623 "cfg", 1624 "bus_master", 1625 "bus_slave", 1626 "slave_q2a", 1627 "tbu", 1628 "ddrss_sf_tbu"; 1629 1630 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1631 assigned-clock-rates = <19200000>; 1632 1633 resets = <&gcc GCC_PCIE_1_BCR>; 1634 reset-names = "pci"; 1635 1636 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1637 1638 phys = <&pcie1_lane>; 1639 phy-names = "pciephy"; 1640 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&pcie1_clkreq_n>; 1643 1644 iommus = <&apps_smmu 0x1c80 0x1>; 1645 1646 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1647 <0x100 &apps_smmu 0x1c81 0x1>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x1c0>; 1655 #address-cells = <2>; 1656 #size-cells = <2>; 1657 ranges; 1658 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1659 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1660 <&gcc GCC_PCIE_CLKREF_EN>, 1661 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1662 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1663 1664 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1665 reset-names = "phy"; 1666 1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1668 assigned-clock-rates = <100000000>; 1669 1670 status = "disabled"; 1671 1672 pcie1_lane: lanes@1c0e200 { 1673 reg = <0 0x01c0e200 0 0x170>, 1674 <0 0x01c0e400 0 0x200>, 1675 <0 0x01c0ea00 0 0x1f0>, 1676 <0 0x01c0e600 0 0x170>, 1677 <0 0x01c0e800 0 0x200>, 1678 <0 0x01c0ee00 0 0xf4>; 1679 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1680 clock-names = "pipe0"; 1681 1682 #phy-cells = <0>; 1683 #clock-cells = <1>; 1684 clock-output-names = "pcie_1_pipe_clk"; 1685 }; 1686 }; 1687 1688 ipa: ipa@1e40000 { 1689 compatible = "qcom,sc7280-ipa"; 1690 1691 iommus = <&apps_smmu 0x480 0x0>, 1692 <&apps_smmu 0x482 0x0>; 1693 reg = <0 0x1e40000 0 0x8000>, 1694 <0 0x1e50000 0 0x4ad0>, 1695 <0 0x1e04000 0 0x23000>; 1696 reg-names = "ipa-reg", 1697 "ipa-shared", 1698 "gsi"; 1699 1700 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1701 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1702 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1703 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1704 interrupt-names = "ipa", 1705 "gsi", 1706 "ipa-clock-query", 1707 "ipa-setup-ready"; 1708 1709 clocks = <&rpmhcc RPMH_IPA_CLK>; 1710 clock-names = "core"; 1711 1712 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1714 interconnect-names = "memory", 1715 "config"; 1716 1717 qcom,smem-states = <&ipa_smp2p_out 0>, 1718 <&ipa_smp2p_out 1>; 1719 qcom,smem-state-names = "ipa-clock-enabled-valid", 1720 "ipa-clock-enabled"; 1721 1722 status = "disabled"; 1723 }; 1724 1725 tcsr_mutex: hwlock@1f40000 { 1726 compatible = "qcom,tcsr-mutex", "syscon"; 1727 reg = <0 0x01f40000 0 0x40000>; 1728 #hwlock-cells = <1>; 1729 }; 1730 1731 tcsr: syscon@1fc0000 { 1732 compatible = "qcom,sc7280-tcsr", "syscon"; 1733 reg = <0 0x01fc0000 0 0x30000>; 1734 }; 1735 1736 lpasscc: lpasscc@3000000 { 1737 compatible = "qcom,sc7280-lpasscc"; 1738 reg = <0 0x03000000 0 0x40>, 1739 <0 0x03c04000 0 0x4>, 1740 <0 0x03389000 0 0x24>; 1741 reg-names = "qdsp6ss", "top_cc", "cc"; 1742 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1743 clock-names = "iface"; 1744 #clock-cells = <1>; 1745 }; 1746 1747 lpass_ag_noc: interconnect@3c40000 { 1748 reg = <0 0x03c40000 0 0xf080>; 1749 compatible = "qcom,sc7280-lpass-ag-noc"; 1750 #interconnect-cells = <2>; 1751 qcom,bcm-voters = <&apps_bcm_voter>; 1752 }; 1753 1754 gpu: gpu@3d00000 { 1755 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1756 reg = <0 0x03d00000 0 0x40000>, 1757 <0 0x03d9e000 0 0x1000>, 1758 <0 0x03d61000 0 0x800>; 1759 reg-names = "kgsl_3d0_reg_memory", 1760 "cx_mem", 1761 "cx_dbgc"; 1762 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1763 iommus = <&adreno_smmu 0 0x401>; 1764 operating-points-v2 = <&gpu_opp_table>; 1765 qcom,gmu = <&gmu>; 1766 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1767 interconnect-names = "gfx-mem"; 1768 #cooling-cells = <2>; 1769 1770 gpu_opp_table: opp-table { 1771 compatible = "operating-points-v2"; 1772 1773 opp-315000000 { 1774 opp-hz = /bits/ 64 <315000000>; 1775 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1776 opp-peak-kBps = <1804000>; 1777 }; 1778 1779 opp-450000000 { 1780 opp-hz = /bits/ 64 <450000000>; 1781 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1782 opp-peak-kBps = <4068000>; 1783 }; 1784 1785 opp-550000000 { 1786 opp-hz = /bits/ 64 <550000000>; 1787 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1788 opp-peak-kBps = <6832000>; 1789 }; 1790 }; 1791 }; 1792 1793 gmu: gmu@3d69000 { 1794 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1795 reg = <0 0x03d6a000 0 0x34000>, 1796 <0 0x3de0000 0 0x10000>, 1797 <0 0x0b290000 0 0x10000>; 1798 reg-names = "gmu", "rscc", "gmu_pdc"; 1799 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1801 interrupt-names = "hfi", "gmu"; 1802 clocks = <&gpucc 5>, 1803 <&gpucc 8>, 1804 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1805 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1806 <&gpucc 2>, 1807 <&gpucc 15>, 1808 <&gpucc 11>; 1809 clock-names = "gmu", 1810 "cxo", 1811 "axi", 1812 "memnoc", 1813 "ahb", 1814 "hub", 1815 "smmu_vote"; 1816 power-domains = <&gpucc 0>, 1817 <&gpucc 1>; 1818 power-domain-names = "cx", 1819 "gx"; 1820 iommus = <&adreno_smmu 5 0x400>; 1821 operating-points-v2 = <&gmu_opp_table>; 1822 1823 gmu_opp_table: opp-table { 1824 compatible = "operating-points-v2"; 1825 1826 opp-200000000 { 1827 opp-hz = /bits/ 64 <200000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1829 }; 1830 }; 1831 }; 1832 1833 gpucc: clock-controller@3d90000 { 1834 compatible = "qcom,sc7280-gpucc"; 1835 reg = <0 0x03d90000 0 0x9000>; 1836 clocks = <&rpmhcc RPMH_CXO_CLK>, 1837 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1838 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1839 clock-names = "bi_tcxo", 1840 "gcc_gpu_gpll0_clk_src", 1841 "gcc_gpu_gpll0_div_clk_src"; 1842 #clock-cells = <1>; 1843 #reset-cells = <1>; 1844 #power-domain-cells = <1>; 1845 }; 1846 1847 adreno_smmu: iommu@3da0000 { 1848 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1849 reg = <0 0x03da0000 0 0x20000>; 1850 #iommu-cells = <2>; 1851 #global-interrupts = <2>; 1852 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1864 1865 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1866 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1867 <&gpucc 2>, 1868 <&gpucc 11>, 1869 <&gpucc 5>, 1870 <&gpucc 15>, 1871 <&gpucc 13>; 1872 clock-names = "gcc_gpu_memnoc_gfx_clk", 1873 "gcc_gpu_snoc_dvm_gfx_clk", 1874 "gpu_cc_ahb_clk", 1875 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1876 "gpu_cc_cx_gmu_clk", 1877 "gpu_cc_hub_cx_int_clk", 1878 "gpu_cc_hub_aon_clk"; 1879 1880 power-domains = <&gpucc 0>; 1881 }; 1882 1883 remoteproc_mpss: remoteproc@4080000 { 1884 compatible = "qcom,sc7280-mpss-pas"; 1885 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1886 reg-names = "qdsp6", "rmb"; 1887 1888 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1889 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1890 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1891 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1894 interrupt-names = "wdog", "fatal", "ready", "handover", 1895 "stop-ack", "shutdown-ack"; 1896 1897 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1898 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1899 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1900 <&rpmhcc RPMH_PKA_CLK>, 1901 <&rpmhcc RPMH_CXO_CLK>; 1902 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1903 1904 power-domains = <&rpmhpd SC7280_CX>, 1905 <&rpmhpd SC7280_MSS>; 1906 power-domain-names = "cx", "mss"; 1907 1908 memory-region = <&mpss_mem>; 1909 1910 qcom,qmp = <&aoss_qmp>; 1911 1912 qcom,smem-states = <&modem_smp2p_out 0>; 1913 qcom,smem-state-names = "stop"; 1914 1915 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1916 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1917 reset-names = "mss_restart", "pdc_reset"; 1918 1919 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1920 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1921 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1922 1923 status = "disabled"; 1924 1925 glink-edge { 1926 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1927 IPCC_MPROC_SIGNAL_GLINK_QMP 1928 IRQ_TYPE_EDGE_RISING>; 1929 mboxes = <&ipcc IPCC_CLIENT_MPSS 1930 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1931 label = "modem"; 1932 qcom,remote-pid = <1>; 1933 }; 1934 }; 1935 1936 stm@6002000 { 1937 compatible = "arm,coresight-stm", "arm,primecell"; 1938 reg = <0 0x06002000 0 0x1000>, 1939 <0 0x16280000 0 0x180000>; 1940 reg-names = "stm-base", "stm-stimulus-base"; 1941 1942 clocks = <&aoss_qmp>; 1943 clock-names = "apb_pclk"; 1944 1945 out-ports { 1946 port { 1947 stm_out: endpoint { 1948 remote-endpoint = <&funnel0_in7>; 1949 }; 1950 }; 1951 }; 1952 }; 1953 1954 funnel@6041000 { 1955 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1956 reg = <0 0x06041000 0 0x1000>; 1957 1958 clocks = <&aoss_qmp>; 1959 clock-names = "apb_pclk"; 1960 1961 out-ports { 1962 port { 1963 funnel0_out: endpoint { 1964 remote-endpoint = <&merge_funnel_in0>; 1965 }; 1966 }; 1967 }; 1968 1969 in-ports { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 port@7 { 1974 reg = <7>; 1975 funnel0_in7: endpoint { 1976 remote-endpoint = <&stm_out>; 1977 }; 1978 }; 1979 }; 1980 }; 1981 1982 funnel@6042000 { 1983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1984 reg = <0 0x06042000 0 0x1000>; 1985 1986 clocks = <&aoss_qmp>; 1987 clock-names = "apb_pclk"; 1988 1989 out-ports { 1990 port { 1991 funnel1_out: endpoint { 1992 remote-endpoint = <&merge_funnel_in1>; 1993 }; 1994 }; 1995 }; 1996 1997 in-ports { 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 port@4 { 2002 reg = <4>; 2003 funnel1_in4: endpoint { 2004 remote-endpoint = <&apss_merge_funnel_out>; 2005 }; 2006 }; 2007 }; 2008 }; 2009 2010 funnel@6045000 { 2011 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2012 reg = <0 0x06045000 0 0x1000>; 2013 2014 clocks = <&aoss_qmp>; 2015 clock-names = "apb_pclk"; 2016 2017 out-ports { 2018 port { 2019 merge_funnel_out: endpoint { 2020 remote-endpoint = <&swao_funnel_in>; 2021 }; 2022 }; 2023 }; 2024 2025 in-ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 2029 port@0 { 2030 reg = <0>; 2031 merge_funnel_in0: endpoint { 2032 remote-endpoint = <&funnel0_out>; 2033 }; 2034 }; 2035 2036 port@1 { 2037 reg = <1>; 2038 merge_funnel_in1: endpoint { 2039 remote-endpoint = <&funnel1_out>; 2040 }; 2041 }; 2042 }; 2043 }; 2044 2045 replicator@6046000 { 2046 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2047 reg = <0 0x06046000 0 0x1000>; 2048 2049 clocks = <&aoss_qmp>; 2050 clock-names = "apb_pclk"; 2051 2052 out-ports { 2053 port { 2054 replicator_out: endpoint { 2055 remote-endpoint = <&etr_in>; 2056 }; 2057 }; 2058 }; 2059 2060 in-ports { 2061 port { 2062 replicator_in: endpoint { 2063 remote-endpoint = <&swao_replicator_out>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 etr@6048000 { 2070 compatible = "arm,coresight-tmc", "arm,primecell"; 2071 reg = <0 0x06048000 0 0x1000>; 2072 iommus = <&apps_smmu 0x04c0 0>; 2073 2074 clocks = <&aoss_qmp>; 2075 clock-names = "apb_pclk"; 2076 arm,scatter-gather; 2077 2078 in-ports { 2079 port { 2080 etr_in: endpoint { 2081 remote-endpoint = <&replicator_out>; 2082 }; 2083 }; 2084 }; 2085 }; 2086 2087 funnel@6b04000 { 2088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2089 reg = <0 0x06b04000 0 0x1000>; 2090 2091 clocks = <&aoss_qmp>; 2092 clock-names = "apb_pclk"; 2093 2094 out-ports { 2095 port { 2096 swao_funnel_out: endpoint { 2097 remote-endpoint = <&etf_in>; 2098 }; 2099 }; 2100 }; 2101 2102 in-ports { 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 port@7 { 2107 reg = <7>; 2108 swao_funnel_in: endpoint { 2109 remote-endpoint = <&merge_funnel_out>; 2110 }; 2111 }; 2112 }; 2113 }; 2114 2115 etf@6b05000 { 2116 compatible = "arm,coresight-tmc", "arm,primecell"; 2117 reg = <0 0x06b05000 0 0x1000>; 2118 2119 clocks = <&aoss_qmp>; 2120 clock-names = "apb_pclk"; 2121 2122 out-ports { 2123 port { 2124 etf_out: endpoint { 2125 remote-endpoint = <&swao_replicator_in>; 2126 }; 2127 }; 2128 }; 2129 2130 in-ports { 2131 port { 2132 etf_in: endpoint { 2133 remote-endpoint = <&swao_funnel_out>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 replicator@6b06000 { 2140 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2141 reg = <0 0x06b06000 0 0x1000>; 2142 2143 clocks = <&aoss_qmp>; 2144 clock-names = "apb_pclk"; 2145 qcom,replicator-loses-context; 2146 2147 out-ports { 2148 port { 2149 swao_replicator_out: endpoint { 2150 remote-endpoint = <&replicator_in>; 2151 }; 2152 }; 2153 }; 2154 2155 in-ports { 2156 port { 2157 swao_replicator_in: endpoint { 2158 remote-endpoint = <&etf_out>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 etm@7040000 { 2165 compatible = "arm,coresight-etm4x", "arm,primecell"; 2166 reg = <0 0x07040000 0 0x1000>; 2167 2168 cpu = <&CPU0>; 2169 2170 clocks = <&aoss_qmp>; 2171 clock-names = "apb_pclk"; 2172 arm,coresight-loses-context-with-cpu; 2173 qcom,skip-power-up; 2174 2175 out-ports { 2176 port { 2177 etm0_out: endpoint { 2178 remote-endpoint = <&apss_funnel_in0>; 2179 }; 2180 }; 2181 }; 2182 }; 2183 2184 etm@7140000 { 2185 compatible = "arm,coresight-etm4x", "arm,primecell"; 2186 reg = <0 0x07140000 0 0x1000>; 2187 2188 cpu = <&CPU1>; 2189 2190 clocks = <&aoss_qmp>; 2191 clock-names = "apb_pclk"; 2192 arm,coresight-loses-context-with-cpu; 2193 qcom,skip-power-up; 2194 2195 out-ports { 2196 port { 2197 etm1_out: endpoint { 2198 remote-endpoint = <&apss_funnel_in1>; 2199 }; 2200 }; 2201 }; 2202 }; 2203 2204 etm@7240000 { 2205 compatible = "arm,coresight-etm4x", "arm,primecell"; 2206 reg = <0 0x07240000 0 0x1000>; 2207 2208 cpu = <&CPU2>; 2209 2210 clocks = <&aoss_qmp>; 2211 clock-names = "apb_pclk"; 2212 arm,coresight-loses-context-with-cpu; 2213 qcom,skip-power-up; 2214 2215 out-ports { 2216 port { 2217 etm2_out: endpoint { 2218 remote-endpoint = <&apss_funnel_in2>; 2219 }; 2220 }; 2221 }; 2222 }; 2223 2224 etm@7340000 { 2225 compatible = "arm,coresight-etm4x", "arm,primecell"; 2226 reg = <0 0x07340000 0 0x1000>; 2227 2228 cpu = <&CPU3>; 2229 2230 clocks = <&aoss_qmp>; 2231 clock-names = "apb_pclk"; 2232 arm,coresight-loses-context-with-cpu; 2233 qcom,skip-power-up; 2234 2235 out-ports { 2236 port { 2237 etm3_out: endpoint { 2238 remote-endpoint = <&apss_funnel_in3>; 2239 }; 2240 }; 2241 }; 2242 }; 2243 2244 etm@7440000 { 2245 compatible = "arm,coresight-etm4x", "arm,primecell"; 2246 reg = <0 0x07440000 0 0x1000>; 2247 2248 cpu = <&CPU4>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 arm,coresight-loses-context-with-cpu; 2253 qcom,skip-power-up; 2254 2255 out-ports { 2256 port { 2257 etm4_out: endpoint { 2258 remote-endpoint = <&apss_funnel_in4>; 2259 }; 2260 }; 2261 }; 2262 }; 2263 2264 etm@7540000 { 2265 compatible = "arm,coresight-etm4x", "arm,primecell"; 2266 reg = <0 0x07540000 0 0x1000>; 2267 2268 cpu = <&CPU5>; 2269 2270 clocks = <&aoss_qmp>; 2271 clock-names = "apb_pclk"; 2272 arm,coresight-loses-context-with-cpu; 2273 qcom,skip-power-up; 2274 2275 out-ports { 2276 port { 2277 etm5_out: endpoint { 2278 remote-endpoint = <&apss_funnel_in5>; 2279 }; 2280 }; 2281 }; 2282 }; 2283 2284 etm@7640000 { 2285 compatible = "arm,coresight-etm4x", "arm,primecell"; 2286 reg = <0 0x07640000 0 0x1000>; 2287 2288 cpu = <&CPU6>; 2289 2290 clocks = <&aoss_qmp>; 2291 clock-names = "apb_pclk"; 2292 arm,coresight-loses-context-with-cpu; 2293 qcom,skip-power-up; 2294 2295 out-ports { 2296 port { 2297 etm6_out: endpoint { 2298 remote-endpoint = <&apss_funnel_in6>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 etm@7740000 { 2305 compatible = "arm,coresight-etm4x", "arm,primecell"; 2306 reg = <0 0x07740000 0 0x1000>; 2307 2308 cpu = <&CPU7>; 2309 2310 clocks = <&aoss_qmp>; 2311 clock-names = "apb_pclk"; 2312 arm,coresight-loses-context-with-cpu; 2313 qcom,skip-power-up; 2314 2315 out-ports { 2316 port { 2317 etm7_out: endpoint { 2318 remote-endpoint = <&apss_funnel_in7>; 2319 }; 2320 }; 2321 }; 2322 }; 2323 2324 funnel@7800000 { /* APSS Funnel */ 2325 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2326 reg = <0 0x07800000 0 0x1000>; 2327 2328 clocks = <&aoss_qmp>; 2329 clock-names = "apb_pclk"; 2330 2331 out-ports { 2332 port { 2333 apss_funnel_out: endpoint { 2334 remote-endpoint = <&apss_merge_funnel_in>; 2335 }; 2336 }; 2337 }; 2338 2339 in-ports { 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 2343 port@0 { 2344 reg = <0>; 2345 apss_funnel_in0: endpoint { 2346 remote-endpoint = <&etm0_out>; 2347 }; 2348 }; 2349 2350 port@1 { 2351 reg = <1>; 2352 apss_funnel_in1: endpoint { 2353 remote-endpoint = <&etm1_out>; 2354 }; 2355 }; 2356 2357 port@2 { 2358 reg = <2>; 2359 apss_funnel_in2: endpoint { 2360 remote-endpoint = <&etm2_out>; 2361 }; 2362 }; 2363 2364 port@3 { 2365 reg = <3>; 2366 apss_funnel_in3: endpoint { 2367 remote-endpoint = <&etm3_out>; 2368 }; 2369 }; 2370 2371 port@4 { 2372 reg = <4>; 2373 apss_funnel_in4: endpoint { 2374 remote-endpoint = <&etm4_out>; 2375 }; 2376 }; 2377 2378 port@5 { 2379 reg = <5>; 2380 apss_funnel_in5: endpoint { 2381 remote-endpoint = <&etm5_out>; 2382 }; 2383 }; 2384 2385 port@6 { 2386 reg = <6>; 2387 apss_funnel_in6: endpoint { 2388 remote-endpoint = <&etm6_out>; 2389 }; 2390 }; 2391 2392 port@7 { 2393 reg = <7>; 2394 apss_funnel_in7: endpoint { 2395 remote-endpoint = <&etm7_out>; 2396 }; 2397 }; 2398 }; 2399 }; 2400 2401 funnel@7810000 { 2402 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2403 reg = <0 0x07810000 0 0x1000>; 2404 2405 clocks = <&aoss_qmp>; 2406 clock-names = "apb_pclk"; 2407 2408 out-ports { 2409 port { 2410 apss_merge_funnel_out: endpoint { 2411 remote-endpoint = <&funnel1_in4>; 2412 }; 2413 }; 2414 }; 2415 2416 in-ports { 2417 port { 2418 apss_merge_funnel_in: endpoint { 2419 remote-endpoint = <&apss_funnel_out>; 2420 }; 2421 }; 2422 }; 2423 }; 2424 2425 sdhc_2: sdhci@8804000 { 2426 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2427 status = "disabled"; 2428 2429 reg = <0 0x08804000 0 0x1000>; 2430 2431 iommus = <&apps_smmu 0x100 0x0>; 2432 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2434 interrupt-names = "hc_irq", "pwr_irq"; 2435 2436 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2437 <&gcc GCC_SDCC2_AHB_CLK>, 2438 <&rpmhcc RPMH_CXO_CLK>; 2439 clock-names = "core", "iface", "xo"; 2440 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2442 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2443 power-domains = <&rpmhpd SC7280_CX>; 2444 operating-points-v2 = <&sdhc2_opp_table>; 2445 2446 bus-width = <4>; 2447 2448 qcom,dll-config = <0x0007642c>; 2449 2450 sdhc2_opp_table: opp-table { 2451 compatible = "operating-points-v2"; 2452 2453 opp-100000000 { 2454 opp-hz = /bits/ 64 <100000000>; 2455 required-opps = <&rpmhpd_opp_low_svs>; 2456 opp-peak-kBps = <1800000 400000>; 2457 opp-avg-kBps = <100000 0>; 2458 }; 2459 2460 opp-202000000 { 2461 opp-hz = /bits/ 64 <202000000>; 2462 required-opps = <&rpmhpd_opp_nom>; 2463 opp-peak-kBps = <5400000 1600000>; 2464 opp-avg-kBps = <200000 0>; 2465 }; 2466 }; 2467 2468 }; 2469 2470 usb_1_hsphy: phy@88e3000 { 2471 compatible = "qcom,sc7280-usb-hs-phy", 2472 "qcom,usb-snps-hs-7nm-phy"; 2473 reg = <0 0x088e3000 0 0x400>; 2474 status = "disabled"; 2475 #phy-cells = <0>; 2476 2477 clocks = <&rpmhcc RPMH_CXO_CLK>; 2478 clock-names = "ref"; 2479 2480 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2481 }; 2482 2483 usb_2_hsphy: phy@88e4000 { 2484 compatible = "qcom,sc7280-usb-hs-phy", 2485 "qcom,usb-snps-hs-7nm-phy"; 2486 reg = <0 0x088e4000 0 0x400>; 2487 status = "disabled"; 2488 #phy-cells = <0>; 2489 2490 clocks = <&rpmhcc RPMH_CXO_CLK>; 2491 clock-names = "ref"; 2492 2493 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2494 }; 2495 2496 usb_1_qmpphy: phy-wrapper@88e9000 { 2497 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2498 "qcom,sm8250-qmp-usb3-dp-phy"; 2499 reg = <0 0x088e9000 0 0x200>, 2500 <0 0x088e8000 0 0x40>, 2501 <0 0x088ea000 0 0x200>; 2502 status = "disabled"; 2503 #address-cells = <2>; 2504 #size-cells = <2>; 2505 ranges; 2506 2507 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2508 <&rpmhcc RPMH_CXO_CLK>, 2509 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2510 clock-names = "aux", "ref_clk_src", "com_aux"; 2511 2512 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2513 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2514 reset-names = "phy", "common"; 2515 2516 usb_1_ssphy: usb3-phy@88e9200 { 2517 reg = <0 0x088e9200 0 0x200>, 2518 <0 0x088e9400 0 0x200>, 2519 <0 0x088e9c00 0 0x400>, 2520 <0 0x088e9600 0 0x200>, 2521 <0 0x088e9800 0 0x200>, 2522 <0 0x088e9a00 0 0x100>; 2523 #clock-cells = <0>; 2524 #phy-cells = <0>; 2525 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2526 clock-names = "pipe0"; 2527 clock-output-names = "usb3_phy_pipe_clk_src"; 2528 }; 2529 2530 dp_phy: dp-phy@88ea200 { 2531 reg = <0 0x088ea200 0 0x200>, 2532 <0 0x088ea400 0 0x200>, 2533 <0 0x088eaa00 0 0x200>, 2534 <0 0x088ea600 0 0x200>, 2535 <0 0x088ea800 0 0x200>; 2536 #phy-cells = <0>; 2537 #clock-cells = <1>; 2538 }; 2539 }; 2540 2541 usb_2: usb@8cf8800 { 2542 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2543 reg = <0 0x08cf8800 0 0x400>; 2544 status = "disabled"; 2545 #address-cells = <2>; 2546 #size-cells = <2>; 2547 ranges; 2548 dma-ranges; 2549 2550 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2551 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2552 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2553 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2554 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2555 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2556 "sleep"; 2557 2558 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2559 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2560 assigned-clock-rates = <19200000>, <200000000>; 2561 2562 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2563 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2564 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2565 interrupt-names = "hs_phy_irq", 2566 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2567 2568 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2569 2570 resets = <&gcc GCC_USB30_SEC_BCR>; 2571 2572 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2574 interconnect-names = "usb-ddr", "apps-usb"; 2575 2576 usb_2_dwc3: usb@8c00000 { 2577 compatible = "snps,dwc3"; 2578 reg = <0 0x08c00000 0 0xe000>; 2579 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2580 iommus = <&apps_smmu 0xa0 0x0>; 2581 snps,dis_u2_susphy_quirk; 2582 snps,dis_enblslpm_quirk; 2583 phys = <&usb_2_hsphy>; 2584 phy-names = "usb2-phy"; 2585 maximum-speed = "high-speed"; 2586 }; 2587 }; 2588 2589 qspi: spi@88dc000 { 2590 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2591 reg = <0 0x088dc000 0 0x1000>; 2592 #address-cells = <1>; 2593 #size-cells = <0>; 2594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2596 <&gcc GCC_QSPI_CORE_CLK>; 2597 clock-names = "iface", "core"; 2598 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2599 &cnoc2 SLAVE_QSPI_0 0>; 2600 interconnect-names = "qspi-config"; 2601 power-domains = <&rpmhpd SC7280_CX>; 2602 operating-points-v2 = <&qspi_opp_table>; 2603 status = "disabled"; 2604 }; 2605 2606 dc_noc: interconnect@90e0000 { 2607 reg = <0 0x090e0000 0 0x5080>; 2608 compatible = "qcom,sc7280-dc-noc"; 2609 #interconnect-cells = <2>; 2610 qcom,bcm-voters = <&apps_bcm_voter>; 2611 }; 2612 2613 gem_noc: interconnect@9100000 { 2614 reg = <0 0x9100000 0 0xe2200>; 2615 compatible = "qcom,sc7280-gem-noc"; 2616 #interconnect-cells = <2>; 2617 qcom,bcm-voters = <&apps_bcm_voter>; 2618 }; 2619 2620 system-cache-controller@9200000 { 2621 compatible = "qcom,sc7280-llcc"; 2622 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2623 reg-names = "llcc_base", "llcc_broadcast_base"; 2624 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2625 }; 2626 2627 nsp_noc: interconnect@a0c0000 { 2628 reg = <0 0x0a0c0000 0 0x10000>; 2629 compatible = "qcom,sc7280-nsp-noc"; 2630 #interconnect-cells = <2>; 2631 qcom,bcm-voters = <&apps_bcm_voter>; 2632 }; 2633 2634 usb_1: usb@a6f8800 { 2635 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2636 reg = <0 0x0a6f8800 0 0x400>; 2637 status = "disabled"; 2638 #address-cells = <2>; 2639 #size-cells = <2>; 2640 ranges; 2641 dma-ranges; 2642 2643 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2644 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2645 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2646 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2647 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2648 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2649 "sleep"; 2650 2651 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2652 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2653 assigned-clock-rates = <19200000>, <200000000>; 2654 2655 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2656 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2657 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2658 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2659 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2660 "dm_hs_phy_irq", "ss_phy_irq"; 2661 2662 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2663 2664 resets = <&gcc GCC_USB30_PRIM_BCR>; 2665 2666 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2667 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2668 interconnect-names = "usb-ddr", "apps-usb"; 2669 2670 usb_1_dwc3: usb@a600000 { 2671 compatible = "snps,dwc3"; 2672 reg = <0 0x0a600000 0 0xe000>; 2673 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2674 iommus = <&apps_smmu 0xe0 0x0>; 2675 snps,dis_u2_susphy_quirk; 2676 snps,dis_enblslpm_quirk; 2677 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2678 phy-names = "usb2-phy", "usb3-phy"; 2679 maximum-speed = "super-speed"; 2680 }; 2681 }; 2682 2683 venus: video-codec@aa00000 { 2684 compatible = "qcom,sc7280-venus"; 2685 reg = <0 0x0aa00000 0 0xd0600>; 2686 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2689 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2690 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2691 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2692 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2693 clock-names = "core", "bus", "iface", 2694 "vcodec_core", "vcodec_bus"; 2695 2696 power-domains = <&videocc MVSC_GDSC>, 2697 <&videocc MVS0_GDSC>, 2698 <&rpmhpd SC7280_CX>; 2699 power-domain-names = "venus", "vcodec0", "cx"; 2700 operating-points-v2 = <&venus_opp_table>; 2701 2702 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2703 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2704 interconnect-names = "cpu-cfg", "video-mem"; 2705 2706 iommus = <&apps_smmu 0x2180 0x20>, 2707 <&apps_smmu 0x2184 0x20>; 2708 memory-region = <&video_mem>; 2709 2710 video-decoder { 2711 compatible = "venus-decoder"; 2712 }; 2713 2714 video-encoder { 2715 compatible = "venus-encoder"; 2716 }; 2717 2718 video-firmware { 2719 iommus = <&apps_smmu 0x21a2 0x0>; 2720 }; 2721 2722 venus_opp_table: venus-opp-table { 2723 compatible = "operating-points-v2"; 2724 2725 opp-133330000 { 2726 opp-hz = /bits/ 64 <133330000>; 2727 required-opps = <&rpmhpd_opp_low_svs>; 2728 }; 2729 2730 opp-240000000 { 2731 opp-hz = /bits/ 64 <240000000>; 2732 required-opps = <&rpmhpd_opp_svs>; 2733 }; 2734 2735 opp-335000000 { 2736 opp-hz = /bits/ 64 <335000000>; 2737 required-opps = <&rpmhpd_opp_svs_l1>; 2738 }; 2739 2740 opp-424000000 { 2741 opp-hz = /bits/ 64 <424000000>; 2742 required-opps = <&rpmhpd_opp_nom>; 2743 }; 2744 2745 opp-460000048 { 2746 opp-hz = /bits/ 64 <460000048>; 2747 required-opps = <&rpmhpd_opp_turbo>; 2748 }; 2749 }; 2750 2751 }; 2752 2753 videocc: clock-controller@aaf0000 { 2754 compatible = "qcom,sc7280-videocc"; 2755 reg = <0 0xaaf0000 0 0x10000>; 2756 clocks = <&rpmhcc RPMH_CXO_CLK>, 2757 <&rpmhcc RPMH_CXO_CLK_A>; 2758 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2759 #clock-cells = <1>; 2760 #reset-cells = <1>; 2761 #power-domain-cells = <1>; 2762 }; 2763 2764 camcc: clock-controller@ad00000 { 2765 compatible = "qcom,sc7280-camcc"; 2766 reg = <0 0x0ad00000 0 0x10000>; 2767 clocks = <&rpmhcc RPMH_CXO_CLK>, 2768 <&rpmhcc RPMH_CXO_CLK_A>, 2769 <&sleep_clk>; 2770 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 2771 #clock-cells = <1>; 2772 #reset-cells = <1>; 2773 #power-domain-cells = <1>; 2774 }; 2775 2776 dispcc: clock-controller@af00000 { 2777 compatible = "qcom,sc7280-dispcc"; 2778 reg = <0 0xaf00000 0 0x20000>; 2779 clocks = <&rpmhcc RPMH_CXO_CLK>, 2780 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2781 <&mdss_dsi_phy 0>, 2782 <&mdss_dsi_phy 1>, 2783 <&dp_phy 0>, 2784 <&dp_phy 1>, 2785 <&mdss_edp_phy 0>, 2786 <&mdss_edp_phy 1>; 2787 clock-names = "bi_tcxo", 2788 "gcc_disp_gpll0_clk", 2789 "dsi0_phy_pll_out_byteclk", 2790 "dsi0_phy_pll_out_dsiclk", 2791 "dp_phy_pll_link_clk", 2792 "dp_phy_pll_vco_div_clk", 2793 "edp_phy_pll_link_clk", 2794 "edp_phy_pll_vco_div_clk"; 2795 #clock-cells = <1>; 2796 #reset-cells = <1>; 2797 #power-domain-cells = <1>; 2798 }; 2799 2800 mdss: display-subsystem@ae00000 { 2801 compatible = "qcom,sc7280-mdss"; 2802 reg = <0 0x0ae00000 0 0x1000>; 2803 reg-names = "mdss"; 2804 2805 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 2806 2807 clocks = <&gcc GCC_DISP_AHB_CLK>, 2808 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2809 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2810 clock-names = "iface", 2811 "ahb", 2812 "core"; 2813 2814 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2815 assigned-clock-rates = <300000000>; 2816 2817 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2818 interrupt-controller; 2819 #interrupt-cells = <1>; 2820 2821 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2822 interconnect-names = "mdp0-mem"; 2823 2824 iommus = <&apps_smmu 0x900 0x402>; 2825 2826 #address-cells = <2>; 2827 #size-cells = <2>; 2828 ranges; 2829 2830 status = "disabled"; 2831 2832 mdss_mdp: display-controller@ae01000 { 2833 compatible = "qcom,sc7280-dpu"; 2834 reg = <0 0x0ae01000 0 0x8f030>, 2835 <0 0x0aeb0000 0 0x2008>; 2836 reg-names = "mdp", "vbif"; 2837 2838 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2839 <&gcc GCC_DISP_SF_AXI_CLK>, 2840 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2841 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2842 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2843 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2844 clock-names = "bus", 2845 "nrt_bus", 2846 "iface", 2847 "lut", 2848 "core", 2849 "vsync"; 2850 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2851 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2852 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2853 assigned-clock-rates = <300000000>, 2854 <19200000>, 2855 <19200000>; 2856 operating-points-v2 = <&mdp_opp_table>; 2857 power-domains = <&rpmhpd SC7280_CX>; 2858 2859 interrupt-parent = <&mdss>; 2860 interrupts = <0>; 2861 2862 status = "disabled"; 2863 2864 ports { 2865 #address-cells = <1>; 2866 #size-cells = <0>; 2867 2868 port@0 { 2869 reg = <0>; 2870 dpu_intf1_out: endpoint { 2871 remote-endpoint = <&dsi0_in>; 2872 }; 2873 }; 2874 2875 port@1 { 2876 reg = <1>; 2877 dpu_intf5_out: endpoint { 2878 remote-endpoint = <&edp_in>; 2879 }; 2880 }; 2881 2882 port@2 { 2883 reg = <2>; 2884 dpu_intf0_out: endpoint { 2885 remote-endpoint = <&dp_in>; 2886 }; 2887 }; 2888 }; 2889 2890 mdp_opp_table: opp-table { 2891 compatible = "operating-points-v2"; 2892 2893 opp-200000000 { 2894 opp-hz = /bits/ 64 <200000000>; 2895 required-opps = <&rpmhpd_opp_low_svs>; 2896 }; 2897 2898 opp-300000000 { 2899 opp-hz = /bits/ 64 <300000000>; 2900 required-opps = <&rpmhpd_opp_svs>; 2901 }; 2902 2903 opp-380000000 { 2904 opp-hz = /bits/ 64 <380000000>; 2905 required-opps = <&rpmhpd_opp_svs_l1>; 2906 }; 2907 2908 opp-506666667 { 2909 opp-hz = /bits/ 64 <506666667>; 2910 required-opps = <&rpmhpd_opp_nom>; 2911 }; 2912 }; 2913 }; 2914 2915 mdss_dsi: dsi@ae94000 { 2916 compatible = "qcom,mdss-dsi-ctrl"; 2917 reg = <0 0x0ae94000 0 0x400>; 2918 reg-names = "dsi_ctrl"; 2919 2920 interrupt-parent = <&mdss>; 2921 interrupts = <4>; 2922 2923 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2924 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2925 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2926 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2927 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2928 <&gcc GCC_DISP_HF_AXI_CLK>; 2929 clock-names = "byte", 2930 "byte_intf", 2931 "pixel", 2932 "core", 2933 "iface", 2934 "bus"; 2935 2936 operating-points-v2 = <&dsi_opp_table>; 2937 power-domains = <&rpmhpd SC7280_CX>; 2938 2939 phys = <&mdss_dsi_phy>; 2940 phy-names = "dsi"; 2941 2942 #address-cells = <1>; 2943 #size-cells = <0>; 2944 2945 status = "disabled"; 2946 2947 ports { 2948 #address-cells = <1>; 2949 #size-cells = <0>; 2950 2951 port@0 { 2952 reg = <0>; 2953 dsi0_in: endpoint { 2954 remote-endpoint = <&dpu_intf1_out>; 2955 }; 2956 }; 2957 2958 port@1 { 2959 reg = <1>; 2960 dsi0_out: endpoint { 2961 }; 2962 }; 2963 }; 2964 2965 dsi_opp_table: opp-table { 2966 compatible = "operating-points-v2"; 2967 2968 opp-187500000 { 2969 opp-hz = /bits/ 64 <187500000>; 2970 required-opps = <&rpmhpd_opp_low_svs>; 2971 }; 2972 2973 opp-300000000 { 2974 opp-hz = /bits/ 64 <300000000>; 2975 required-opps = <&rpmhpd_opp_svs>; 2976 }; 2977 2978 opp-358000000 { 2979 opp-hz = /bits/ 64 <358000000>; 2980 required-opps = <&rpmhpd_opp_svs_l1>; 2981 }; 2982 }; 2983 }; 2984 2985 mdss_dsi_phy: phy@ae94400 { 2986 compatible = "qcom,sc7280-dsi-phy-7nm"; 2987 reg = <0 0x0ae94400 0 0x200>, 2988 <0 0x0ae94600 0 0x280>, 2989 <0 0x0ae94900 0 0x280>; 2990 reg-names = "dsi_phy", 2991 "dsi_phy_lane", 2992 "dsi_pll"; 2993 2994 #clock-cells = <1>; 2995 #phy-cells = <0>; 2996 2997 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2998 <&rpmhcc RPMH_CXO_CLK>; 2999 clock-names = "iface", "ref"; 3000 3001 status = "disabled"; 3002 }; 3003 3004 mdss_edp: edp@aea0000 { 3005 compatible = "qcom,sc7280-edp"; 3006 3007 reg = <0 0xaea0000 0 0x200>, 3008 <0 0xaea0200 0 0x200>, 3009 <0 0xaea0400 0 0xc00>, 3010 <0 0xaea1000 0 0x400>; 3011 3012 interrupt-parent = <&mdss>; 3013 interrupts = <14>; 3014 3015 clocks = <&rpmhcc RPMH_CXO_CLK>, 3016 <&gcc GCC_EDP_CLKREF_EN>, 3017 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3018 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3019 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3020 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3021 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3022 clock-names = "core_xo", 3023 "core_ref", 3024 "core_iface", 3025 "core_aux", 3026 "ctrl_link", 3027 "ctrl_link_iface", 3028 "stream_pixel"; 3029 #clock-cells = <1>; 3030 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3031 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3032 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3033 3034 phys = <&mdss_edp_phy>; 3035 phy-names = "dp"; 3036 3037 operating-points-v2 = <&edp_opp_table>; 3038 power-domains = <&rpmhpd SC7280_CX>; 3039 3040 #address-cells = <1>; 3041 #size-cells = <0>; 3042 3043 status = "disabled"; 3044 3045 ports { 3046 #address-cells = <1>; 3047 #size-cells = <0>; 3048 port@0 { 3049 reg = <0>; 3050 edp_in: endpoint { 3051 remote-endpoint = <&dpu_intf5_out>; 3052 }; 3053 }; 3054 }; 3055 3056 edp_opp_table: opp-table { 3057 compatible = "operating-points-v2"; 3058 3059 opp-160000000 { 3060 opp-hz = /bits/ 64 <160000000>; 3061 required-opps = <&rpmhpd_opp_low_svs>; 3062 }; 3063 3064 opp-270000000 { 3065 opp-hz = /bits/ 64 <270000000>; 3066 required-opps = <&rpmhpd_opp_svs>; 3067 }; 3068 3069 opp-540000000 { 3070 opp-hz = /bits/ 64 <540000000>; 3071 required-opps = <&rpmhpd_opp_nom>; 3072 }; 3073 3074 opp-810000000 { 3075 opp-hz = /bits/ 64 <810000000>; 3076 required-opps = <&rpmhpd_opp_nom>; 3077 }; 3078 }; 3079 }; 3080 3081 mdss_edp_phy: phy@aec2a00 { 3082 compatible = "qcom,sc7280-edp-phy"; 3083 3084 reg = <0 0xaec2a00 0 0x19c>, 3085 <0 0xaec2200 0 0xa0>, 3086 <0 0xaec2600 0 0xa0>, 3087 <0 0xaec2000 0 0x1c0>; 3088 3089 clocks = <&rpmhcc RPMH_CXO_CLK>, 3090 <&gcc GCC_EDP_CLKREF_EN>; 3091 clock-names = "aux", 3092 "cfg_ahb"; 3093 3094 #clock-cells = <1>; 3095 #phy-cells = <0>; 3096 3097 status = "disabled"; 3098 }; 3099 3100 mdss_dp: displayport-controller@ae90000 { 3101 compatible = "qcom,sc7280-dp"; 3102 3103 reg = <0 0x0ae90000 0 0x1400>; 3104 3105 interrupt-parent = <&mdss>; 3106 interrupts = <12>; 3107 3108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3109 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3110 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3111 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3112 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3113 clock-names = "core_iface", 3114 "core_aux", 3115 "ctrl_link", 3116 "ctrl_link_iface", 3117 "stream_pixel"; 3118 #clock-cells = <1>; 3119 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3120 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3121 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3122 phys = <&dp_phy>; 3123 phy-names = "dp"; 3124 3125 operating-points-v2 = <&dp_opp_table>; 3126 power-domains = <&rpmhpd SC7280_CX>; 3127 3128 #sound-dai-cells = <0>; 3129 3130 status = "disabled"; 3131 3132 ports { 3133 #address-cells = <1>; 3134 #size-cells = <0>; 3135 port@0 { 3136 reg = <0>; 3137 dp_in: endpoint { 3138 remote-endpoint = <&dpu_intf0_out>; 3139 }; 3140 }; 3141 3142 port@1 { 3143 reg = <1>; 3144 dp_out: endpoint { }; 3145 }; 3146 }; 3147 3148 dp_opp_table: opp-table { 3149 compatible = "operating-points-v2"; 3150 3151 opp-160000000 { 3152 opp-hz = /bits/ 64 <160000000>; 3153 required-opps = <&rpmhpd_opp_low_svs>; 3154 }; 3155 3156 opp-270000000 { 3157 opp-hz = /bits/ 64 <270000000>; 3158 required-opps = <&rpmhpd_opp_svs>; 3159 }; 3160 3161 opp-540000000 { 3162 opp-hz = /bits/ 64 <540000000>; 3163 required-opps = <&rpmhpd_opp_svs_l1>; 3164 }; 3165 3166 opp-810000000 { 3167 opp-hz = /bits/ 64 <810000000>; 3168 required-opps = <&rpmhpd_opp_nom>; 3169 }; 3170 }; 3171 }; 3172 }; 3173 3174 pdc: interrupt-controller@b220000 { 3175 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3176 reg = <0 0x0b220000 0 0x30000>; 3177 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3178 <55 306 4>, <59 312 3>, <62 374 2>, 3179 <64 434 2>, <66 438 3>, <69 86 1>, 3180 <70 520 54>, <124 609 31>, <155 63 1>, 3181 <156 716 12>; 3182 #interrupt-cells = <2>; 3183 interrupt-parent = <&intc>; 3184 interrupt-controller; 3185 }; 3186 3187 pdc_reset: reset-controller@b5e0000 { 3188 compatible = "qcom,sc7280-pdc-global"; 3189 reg = <0 0x0b5e0000 0 0x20000>; 3190 #reset-cells = <1>; 3191 }; 3192 3193 tsens0: thermal-sensor@c263000 { 3194 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3195 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3196 <0 0x0c222000 0 0x1ff>; /* SROT */ 3197 #qcom,sensors = <15>; 3198 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3200 interrupt-names = "uplow","critical"; 3201 #thermal-sensor-cells = <1>; 3202 }; 3203 3204 tsens1: thermal-sensor@c265000 { 3205 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3206 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3207 <0 0x0c223000 0 0x1ff>; /* SROT */ 3208 #qcom,sensors = <12>; 3209 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3211 interrupt-names = "uplow","critical"; 3212 #thermal-sensor-cells = <1>; 3213 }; 3214 3215 aoss_reset: reset-controller@c2a0000 { 3216 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3217 reg = <0 0x0c2a0000 0 0x31000>; 3218 #reset-cells = <1>; 3219 }; 3220 3221 aoss_qmp: power-controller@c300000 { 3222 compatible = "qcom,sc7280-aoss-qmp"; 3223 reg = <0 0x0c300000 0 0x400>; 3224 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3225 IPCC_MPROC_SIGNAL_GLINK_QMP 3226 IRQ_TYPE_EDGE_RISING>; 3227 mboxes = <&ipcc IPCC_CLIENT_AOP 3228 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3229 3230 #clock-cells = <0>; 3231 }; 3232 3233 sram@c3f0000 { 3234 compatible = "qcom,rpmh-stats"; 3235 reg = <0 0x0c3f0000 0 0x400>; 3236 }; 3237 3238 spmi_bus: spmi@c440000 { 3239 compatible = "qcom,spmi-pmic-arb"; 3240 reg = <0 0x0c440000 0 0x1100>, 3241 <0 0x0c600000 0 0x2000000>, 3242 <0 0x0e600000 0 0x100000>, 3243 <0 0x0e700000 0 0xa0000>, 3244 <0 0x0c40a000 0 0x26000>; 3245 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3246 interrupt-names = "periph_irq"; 3247 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3248 qcom,ee = <0>; 3249 qcom,channel = <0>; 3250 #address-cells = <1>; 3251 #size-cells = <1>; 3252 interrupt-controller; 3253 #interrupt-cells = <4>; 3254 }; 3255 3256 tlmm: pinctrl@f100000 { 3257 compatible = "qcom,sc7280-pinctrl"; 3258 reg = <0 0x0f100000 0 0x300000>; 3259 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3260 gpio-controller; 3261 #gpio-cells = <2>; 3262 interrupt-controller; 3263 #interrupt-cells = <2>; 3264 gpio-ranges = <&tlmm 0 0 175>; 3265 wakeup-parent = <&pdc>; 3266 3267 pcie1_clkreq_n: pcie1-clkreq-n { 3268 pins = "gpio79"; 3269 function = "pcie1_clkreqn"; 3270 drive-strength = <2>; 3271 bias-pull-up; 3272 }; 3273 3274 dp_hot_plug_det: dp-hot-plug-det { 3275 pins = "gpio47"; 3276 function = "dp_hot"; 3277 bias-disable; 3278 }; 3279 3280 qspi_clk: qspi-clk { 3281 pins = "gpio14"; 3282 function = "qspi_clk"; 3283 }; 3284 3285 qspi_cs0: qspi-cs0 { 3286 pins = "gpio15"; 3287 function = "qspi_cs"; 3288 }; 3289 3290 qspi_cs1: qspi-cs1 { 3291 pins = "gpio19"; 3292 function = "qspi_cs"; 3293 }; 3294 3295 qspi_data01: qspi-data01 { 3296 pins = "gpio12", "gpio13"; 3297 function = "qspi_data"; 3298 }; 3299 3300 qspi_data12: qspi-data12 { 3301 pins = "gpio16", "gpio17"; 3302 function = "qspi_data"; 3303 }; 3304 3305 qup_i2c0_data_clk: qup-i2c0-data-clk { 3306 pins = "gpio0", "gpio1"; 3307 function = "qup00"; 3308 }; 3309 3310 qup_i2c1_data_clk: qup-i2c1-data-clk { 3311 pins = "gpio4", "gpio5"; 3312 function = "qup01"; 3313 }; 3314 3315 qup_i2c2_data_clk: qup-i2c2-data-clk { 3316 pins = "gpio8", "gpio9"; 3317 function = "qup02"; 3318 }; 3319 3320 qup_i2c3_data_clk: qup-i2c3-data-clk { 3321 pins = "gpio12", "gpio13"; 3322 function = "qup03"; 3323 }; 3324 3325 qup_i2c4_data_clk: qup-i2c4-data-clk { 3326 pins = "gpio16", "gpio17"; 3327 function = "qup04"; 3328 }; 3329 3330 qup_i2c5_data_clk: qup-i2c5-data-clk { 3331 pins = "gpio20", "gpio21"; 3332 function = "qup05"; 3333 }; 3334 3335 qup_i2c6_data_clk: qup-i2c6-data-clk { 3336 pins = "gpio24", "gpio25"; 3337 function = "qup06"; 3338 }; 3339 3340 qup_i2c7_data_clk: qup-i2c7-data-clk { 3341 pins = "gpio28", "gpio29"; 3342 function = "qup07"; 3343 }; 3344 3345 qup_i2c8_data_clk: qup-i2c8-data-clk { 3346 pins = "gpio32", "gpio33"; 3347 function = "qup10"; 3348 }; 3349 3350 qup_i2c9_data_clk: qup-i2c9-data-clk { 3351 pins = "gpio36", "gpio37"; 3352 function = "qup11"; 3353 }; 3354 3355 qup_i2c10_data_clk: qup-i2c10-data-clk { 3356 pins = "gpio40", "gpio41"; 3357 function = "qup12"; 3358 }; 3359 3360 qup_i2c11_data_clk: qup-i2c11-data-clk { 3361 pins = "gpio44", "gpio45"; 3362 function = "qup13"; 3363 }; 3364 3365 qup_i2c12_data_clk: qup-i2c12-data-clk { 3366 pins = "gpio48", "gpio49"; 3367 function = "qup14"; 3368 }; 3369 3370 qup_i2c13_data_clk: qup-i2c13-data-clk { 3371 pins = "gpio52", "gpio53"; 3372 function = "qup15"; 3373 }; 3374 3375 qup_i2c14_data_clk: qup-i2c14-data-clk { 3376 pins = "gpio56", "gpio57"; 3377 function = "qup16"; 3378 }; 3379 3380 qup_i2c15_data_clk: qup-i2c15-data-clk { 3381 pins = "gpio60", "gpio61"; 3382 function = "qup17"; 3383 }; 3384 3385 qup_spi0_data_clk: qup-spi0-data-clk { 3386 pins = "gpio0", "gpio1", "gpio2"; 3387 function = "qup00"; 3388 }; 3389 3390 qup_spi0_cs: qup-spi0-cs { 3391 pins = "gpio3"; 3392 function = "qup00"; 3393 }; 3394 3395 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3396 pins = "gpio3"; 3397 function = "gpio"; 3398 }; 3399 3400 qup_spi1_data_clk: qup-spi1-data-clk { 3401 pins = "gpio4", "gpio5", "gpio6"; 3402 function = "qup01"; 3403 }; 3404 3405 qup_spi1_cs: qup-spi1-cs { 3406 pins = "gpio7"; 3407 function = "qup01"; 3408 }; 3409 3410 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3411 pins = "gpio7"; 3412 function = "gpio"; 3413 }; 3414 3415 qup_spi2_data_clk: qup-spi2-data-clk { 3416 pins = "gpio8", "gpio9", "gpio10"; 3417 function = "qup02"; 3418 }; 3419 3420 qup_spi2_cs: qup-spi2-cs { 3421 pins = "gpio11"; 3422 function = "qup02"; 3423 }; 3424 3425 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3426 pins = "gpio11"; 3427 function = "gpio"; 3428 }; 3429 3430 qup_spi3_data_clk: qup-spi3-data-clk { 3431 pins = "gpio12", "gpio13", "gpio14"; 3432 function = "qup03"; 3433 }; 3434 3435 qup_spi3_cs: qup-spi3-cs { 3436 pins = "gpio15"; 3437 function = "qup03"; 3438 }; 3439 3440 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3441 pins = "gpio15"; 3442 function = "gpio"; 3443 }; 3444 3445 qup_spi4_data_clk: qup-spi4-data-clk { 3446 pins = "gpio16", "gpio17", "gpio18"; 3447 function = "qup04"; 3448 }; 3449 3450 qup_spi4_cs: qup-spi4-cs { 3451 pins = "gpio19"; 3452 function = "qup04"; 3453 }; 3454 3455 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3456 pins = "gpio19"; 3457 function = "gpio"; 3458 }; 3459 3460 qup_spi5_data_clk: qup-spi5-data-clk { 3461 pins = "gpio20", "gpio21", "gpio22"; 3462 function = "qup05"; 3463 }; 3464 3465 qup_spi5_cs: qup-spi5-cs { 3466 pins = "gpio23"; 3467 function = "qup05"; 3468 }; 3469 3470 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3471 pins = "gpio23"; 3472 function = "gpio"; 3473 }; 3474 3475 qup_spi6_data_clk: qup-spi6-data-clk { 3476 pins = "gpio24", "gpio25", "gpio26"; 3477 function = "qup06"; 3478 }; 3479 3480 qup_spi6_cs: qup-spi6-cs { 3481 pins = "gpio27"; 3482 function = "qup06"; 3483 }; 3484 3485 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3486 pins = "gpio27"; 3487 function = "gpio"; 3488 }; 3489 3490 qup_spi7_data_clk: qup-spi7-data-clk { 3491 pins = "gpio28", "gpio29", "gpio30"; 3492 function = "qup07"; 3493 }; 3494 3495 qup_spi7_cs: qup-spi7-cs { 3496 pins = "gpio31"; 3497 function = "qup07"; 3498 }; 3499 3500 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3501 pins = "gpio31"; 3502 function = "gpio"; 3503 }; 3504 3505 qup_spi8_data_clk: qup-spi8-data-clk { 3506 pins = "gpio32", "gpio33", "gpio34"; 3507 function = "qup10"; 3508 }; 3509 3510 qup_spi8_cs: qup-spi8-cs { 3511 pins = "gpio35"; 3512 function = "qup10"; 3513 }; 3514 3515 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3516 pins = "gpio35"; 3517 function = "gpio"; 3518 }; 3519 3520 qup_spi9_data_clk: qup-spi9-data-clk { 3521 pins = "gpio36", "gpio37", "gpio38"; 3522 function = "qup11"; 3523 }; 3524 3525 qup_spi9_cs: qup-spi9-cs { 3526 pins = "gpio39"; 3527 function = "qup11"; 3528 }; 3529 3530 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3531 pins = "gpio39"; 3532 function = "gpio"; 3533 }; 3534 3535 qup_spi10_data_clk: qup-spi10-data-clk { 3536 pins = "gpio40", "gpio41", "gpio42"; 3537 function = "qup12"; 3538 }; 3539 3540 qup_spi10_cs: qup-spi10-cs { 3541 pins = "gpio43"; 3542 function = "qup12"; 3543 }; 3544 3545 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3546 pins = "gpio43"; 3547 function = "gpio"; 3548 }; 3549 3550 qup_spi11_data_clk: qup-spi11-data-clk { 3551 pins = "gpio44", "gpio45", "gpio46"; 3552 function = "qup13"; 3553 }; 3554 3555 qup_spi11_cs: qup-spi11-cs { 3556 pins = "gpio47"; 3557 function = "qup13"; 3558 }; 3559 3560 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3561 pins = "gpio47"; 3562 function = "gpio"; 3563 }; 3564 3565 qup_spi12_data_clk: qup-spi12-data-clk { 3566 pins = "gpio48", "gpio49", "gpio50"; 3567 function = "qup14"; 3568 }; 3569 3570 qup_spi12_cs: qup-spi12-cs { 3571 pins = "gpio51"; 3572 function = "qup14"; 3573 }; 3574 3575 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3576 pins = "gpio51"; 3577 function = "gpio"; 3578 }; 3579 3580 qup_spi13_data_clk: qup-spi13-data-clk { 3581 pins = "gpio52", "gpio53", "gpio54"; 3582 function = "qup15"; 3583 }; 3584 3585 qup_spi13_cs: qup-spi13-cs { 3586 pins = "gpio55"; 3587 function = "qup15"; 3588 }; 3589 3590 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3591 pins = "gpio55"; 3592 function = "gpio"; 3593 }; 3594 3595 qup_spi14_data_clk: qup-spi14-data-clk { 3596 pins = "gpio56", "gpio57", "gpio58"; 3597 function = "qup16"; 3598 }; 3599 3600 qup_spi14_cs: qup-spi14-cs { 3601 pins = "gpio59"; 3602 function = "qup16"; 3603 }; 3604 3605 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3606 pins = "gpio59"; 3607 function = "gpio"; 3608 }; 3609 3610 qup_spi15_data_clk: qup-spi15-data-clk { 3611 pins = "gpio60", "gpio61", "gpio62"; 3612 function = "qup17"; 3613 }; 3614 3615 qup_spi15_cs: qup-spi15-cs { 3616 pins = "gpio63"; 3617 function = "qup17"; 3618 }; 3619 3620 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3621 pins = "gpio63"; 3622 function = "gpio"; 3623 }; 3624 3625 qup_uart0_cts: qup-uart0-cts { 3626 pins = "gpio0"; 3627 function = "qup00"; 3628 }; 3629 3630 qup_uart0_rts: qup-uart0-rts { 3631 pins = "gpio1"; 3632 function = "qup00"; 3633 }; 3634 3635 qup_uart0_tx: qup-uart0-tx { 3636 pins = "gpio2"; 3637 function = "qup00"; 3638 }; 3639 3640 qup_uart0_rx: qup-uart0-rx { 3641 pins = "gpio3"; 3642 function = "qup00"; 3643 }; 3644 3645 qup_uart1_cts: qup-uart1-cts { 3646 pins = "gpio4"; 3647 function = "qup01"; 3648 }; 3649 3650 qup_uart1_rts: qup-uart1-rts { 3651 pins = "gpio5"; 3652 function = "qup01"; 3653 }; 3654 3655 qup_uart1_tx: qup-uart1-tx { 3656 pins = "gpio6"; 3657 function = "qup01"; 3658 }; 3659 3660 qup_uart1_rx: qup-uart1-rx { 3661 pins = "gpio7"; 3662 function = "qup01"; 3663 }; 3664 3665 qup_uart2_cts: qup-uart2-cts { 3666 pins = "gpio8"; 3667 function = "qup02"; 3668 }; 3669 3670 qup_uart2_rts: qup-uart2-rts { 3671 pins = "gpio9"; 3672 function = "qup02"; 3673 }; 3674 3675 qup_uart2_tx: qup-uart2-tx { 3676 pins = "gpio10"; 3677 function = "qup02"; 3678 }; 3679 3680 qup_uart2_rx: qup-uart2-rx { 3681 pins = "gpio11"; 3682 function = "qup02"; 3683 }; 3684 3685 qup_uart3_cts: qup-uart3-cts { 3686 pins = "gpio12"; 3687 function = "qup03"; 3688 }; 3689 3690 qup_uart3_rts: qup-uart3-rts { 3691 pins = "gpio13"; 3692 function = "qup03"; 3693 }; 3694 3695 qup_uart3_tx: qup-uart3-tx { 3696 pins = "gpio14"; 3697 function = "qup03"; 3698 }; 3699 3700 qup_uart3_rx: qup-uart3-rx { 3701 pins = "gpio15"; 3702 function = "qup03"; 3703 }; 3704 3705 qup_uart4_cts: qup-uart4-cts { 3706 pins = "gpio16"; 3707 function = "qup04"; 3708 }; 3709 3710 qup_uart4_rts: qup-uart4-rts { 3711 pins = "gpio17"; 3712 function = "qup04"; 3713 }; 3714 3715 qup_uart4_tx: qup-uart4-tx { 3716 pins = "gpio18"; 3717 function = "qup04"; 3718 }; 3719 3720 qup_uart4_rx: qup-uart4-rx { 3721 pins = "gpio19"; 3722 function = "qup04"; 3723 }; 3724 3725 qup_uart5_cts: qup-uart5-cts { 3726 pins = "gpio20"; 3727 function = "qup05"; 3728 }; 3729 3730 qup_uart5_rts: qup-uart5-rts { 3731 pins = "gpio21"; 3732 function = "qup05"; 3733 }; 3734 3735 qup_uart5_tx: qup-uart5-tx { 3736 pins = "gpio22"; 3737 function = "qup05"; 3738 }; 3739 3740 qup_uart5_rx: qup-uart5-rx { 3741 pins = "gpio23"; 3742 function = "qup05"; 3743 }; 3744 3745 qup_uart6_cts: qup-uart6-cts { 3746 pins = "gpio24"; 3747 function = "qup06"; 3748 }; 3749 3750 qup_uart6_rts: qup-uart6-rts { 3751 pins = "gpio25"; 3752 function = "qup06"; 3753 }; 3754 3755 qup_uart6_tx: qup-uart6-tx { 3756 pins = "gpio26"; 3757 function = "qup06"; 3758 }; 3759 3760 qup_uart6_rx: qup-uart6-rx { 3761 pins = "gpio27"; 3762 function = "qup06"; 3763 }; 3764 3765 qup_uart7_cts: qup-uart7-cts { 3766 pins = "gpio28"; 3767 function = "qup07"; 3768 }; 3769 3770 qup_uart7_rts: qup-uart7-rts { 3771 pins = "gpio29"; 3772 function = "qup07"; 3773 }; 3774 3775 qup_uart7_tx: qup-uart7-tx { 3776 pins = "gpio30"; 3777 function = "qup07"; 3778 }; 3779 3780 qup_uart7_rx: qup-uart7-rx { 3781 pins = "gpio31"; 3782 function = "qup07"; 3783 }; 3784 3785 sdc1_on: sdc1-on { 3786 clk { 3787 pins = "sdc1_clk"; 3788 }; 3789 3790 cmd { 3791 pins = "sdc1_cmd"; 3792 }; 3793 3794 data { 3795 pins = "sdc1_data"; 3796 }; 3797 3798 rclk { 3799 pins = "sdc1_rclk"; 3800 }; 3801 }; 3802 3803 sdc1_off: sdc1-off { 3804 clk { 3805 pins = "sdc1_clk"; 3806 drive-strength = <2>; 3807 bias-bus-hold; 3808 }; 3809 3810 cmd { 3811 pins = "sdc1_cmd"; 3812 drive-strength = <2>; 3813 bias-bus-hold; 3814 }; 3815 3816 data { 3817 pins = "sdc1_data"; 3818 drive-strength = <2>; 3819 bias-bus-hold; 3820 }; 3821 3822 rclk { 3823 pins = "sdc1_rclk"; 3824 bias-bus-hold; 3825 }; 3826 }; 3827 3828 sdc2_on: sdc2-on { 3829 clk { 3830 pins = "sdc2_clk"; 3831 }; 3832 3833 cmd { 3834 pins = "sdc2_cmd"; 3835 }; 3836 3837 data { 3838 pins = "sdc2_data"; 3839 }; 3840 }; 3841 3842 sdc2_off: sdc2-off { 3843 clk { 3844 pins = "sdc2_clk"; 3845 drive-strength = <2>; 3846 bias-bus-hold; 3847 }; 3848 3849 cmd { 3850 pins ="sdc2_cmd"; 3851 drive-strength = <2>; 3852 bias-bus-hold; 3853 }; 3854 3855 data { 3856 pins ="sdc2_data"; 3857 drive-strength = <2>; 3858 bias-bus-hold; 3859 }; 3860 }; 3861 3862 qup_uart8_cts: qup-uart8-cts { 3863 pins = "gpio32"; 3864 function = "qup10"; 3865 }; 3866 3867 qup_uart8_rts: qup-uart8-rts { 3868 pins = "gpio33"; 3869 function = "qup10"; 3870 }; 3871 3872 qup_uart8_tx: qup-uart8-tx { 3873 pins = "gpio34"; 3874 function = "qup10"; 3875 }; 3876 3877 qup_uart8_rx: qup-uart8-rx { 3878 pins = "gpio35"; 3879 function = "qup10"; 3880 }; 3881 3882 qup_uart9_cts: qup-uart9-cts { 3883 pins = "gpio36"; 3884 function = "qup11"; 3885 }; 3886 3887 qup_uart9_rts: qup-uart9-rts { 3888 pins = "gpio37"; 3889 function = "qup11"; 3890 }; 3891 3892 qup_uart9_tx: qup-uart9-tx { 3893 pins = "gpio38"; 3894 function = "qup11"; 3895 }; 3896 3897 qup_uart9_rx: qup-uart9-rx { 3898 pins = "gpio39"; 3899 function = "qup11"; 3900 }; 3901 3902 qup_uart10_cts: qup-uart10-cts { 3903 pins = "gpio40"; 3904 function = "qup12"; 3905 }; 3906 3907 qup_uart10_rts: qup-uart10-rts { 3908 pins = "gpio41"; 3909 function = "qup12"; 3910 }; 3911 3912 qup_uart10_tx: qup-uart10-tx { 3913 pins = "gpio42"; 3914 function = "qup12"; 3915 }; 3916 3917 qup_uart10_rx: qup-uart10-rx { 3918 pins = "gpio43"; 3919 function = "qup12"; 3920 }; 3921 3922 qup_uart11_cts: qup-uart11-cts { 3923 pins = "gpio44"; 3924 function = "qup13"; 3925 }; 3926 3927 qup_uart11_rts: qup-uart11-rts { 3928 pins = "gpio45"; 3929 function = "qup13"; 3930 }; 3931 3932 qup_uart11_tx: qup-uart11-tx { 3933 pins = "gpio46"; 3934 function = "qup13"; 3935 }; 3936 3937 qup_uart11_rx: qup-uart11-rx { 3938 pins = "gpio47"; 3939 function = "qup13"; 3940 }; 3941 3942 qup_uart12_cts: qup-uart12-cts { 3943 pins = "gpio48"; 3944 function = "qup14"; 3945 }; 3946 3947 qup_uart12_rts: qup-uart12-rts { 3948 pins = "gpio49"; 3949 function = "qup14"; 3950 }; 3951 3952 qup_uart12_tx: qup-uart12-tx { 3953 pins = "gpio50"; 3954 function = "qup14"; 3955 }; 3956 3957 qup_uart12_rx: qup-uart12-rx { 3958 pins = "gpio51"; 3959 function = "qup14"; 3960 }; 3961 3962 qup_uart13_cts: qup-uart13-cts { 3963 pins = "gpio52"; 3964 function = "qup15"; 3965 }; 3966 3967 qup_uart13_rts: qup-uart13-rts { 3968 pins = "gpio53"; 3969 function = "qup15"; 3970 }; 3971 3972 qup_uart13_tx: qup-uart13-tx { 3973 pins = "gpio54"; 3974 function = "qup15"; 3975 }; 3976 3977 qup_uart13_rx: qup-uart13-rx { 3978 pins = "gpio55"; 3979 function = "qup15"; 3980 }; 3981 3982 qup_uart14_cts: qup-uart14-cts { 3983 pins = "gpio56"; 3984 function = "qup16"; 3985 }; 3986 3987 qup_uart14_rts: qup-uart14-rts { 3988 pins = "gpio57"; 3989 function = "qup16"; 3990 }; 3991 3992 qup_uart14_tx: qup-uart14-tx { 3993 pins = "gpio58"; 3994 function = "qup16"; 3995 }; 3996 3997 qup_uart14_rx: qup-uart14-rx { 3998 pins = "gpio59"; 3999 function = "qup16"; 4000 }; 4001 4002 qup_uart15_cts: qup-uart15-cts { 4003 pins = "gpio60"; 4004 function = "qup17"; 4005 }; 4006 4007 qup_uart15_rts: qup-uart15-rts { 4008 pins = "gpio61"; 4009 function = "qup17"; 4010 }; 4011 4012 qup_uart15_tx: qup-uart15-tx { 4013 pins = "gpio62"; 4014 function = "qup17"; 4015 }; 4016 4017 qup_uart15_rx: qup-uart15-rx { 4018 pins = "gpio63"; 4019 function = "qup17"; 4020 }; 4021 }; 4022 4023 imem@146a5000 { 4024 compatible = "qcom,sc7280-imem", "syscon"; 4025 reg = <0 0x146a5000 0 0x6000>; 4026 4027 #address-cells = <1>; 4028 #size-cells = <1>; 4029 4030 ranges = <0 0 0x146a5000 0x6000>; 4031 4032 pil-reloc@594c { 4033 compatible = "qcom,pil-reloc-info"; 4034 reg = <0x594c 0xc8>; 4035 }; 4036 }; 4037 4038 apps_smmu: iommu@15000000 { 4039 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4040 reg = <0 0x15000000 0 0x100000>; 4041 #iommu-cells = <2>; 4042 #global-interrupts = <1>; 4043 dma-coherent; 4044 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4125 }; 4126 4127 intc: interrupt-controller@17a00000 { 4128 compatible = "arm,gic-v3"; 4129 #address-cells = <2>; 4130 #size-cells = <2>; 4131 ranges; 4132 #interrupt-cells = <3>; 4133 interrupt-controller; 4134 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4135 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4136 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4137 4138 gic-its@17a40000 { 4139 compatible = "arm,gic-v3-its"; 4140 msi-controller; 4141 #msi-cells = <1>; 4142 reg = <0 0x17a40000 0 0x20000>; 4143 status = "disabled"; 4144 }; 4145 }; 4146 4147 watchdog@17c10000 { 4148 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4149 reg = <0 0x17c10000 0 0x1000>; 4150 clocks = <&sleep_clk>; 4151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4152 }; 4153 4154 timer@17c20000 { 4155 #address-cells = <2>; 4156 #size-cells = <2>; 4157 ranges; 4158 compatible = "arm,armv7-timer-mem"; 4159 reg = <0 0x17c20000 0 0x1000>; 4160 4161 frame@17c21000 { 4162 frame-number = <0>; 4163 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4165 reg = <0 0x17c21000 0 0x1000>, 4166 <0 0x17c22000 0 0x1000>; 4167 }; 4168 4169 frame@17c23000 { 4170 frame-number = <1>; 4171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4172 reg = <0 0x17c23000 0 0x1000>; 4173 status = "disabled"; 4174 }; 4175 4176 frame@17c25000 { 4177 frame-number = <2>; 4178 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4179 reg = <0 0x17c25000 0 0x1000>; 4180 status = "disabled"; 4181 }; 4182 4183 frame@17c27000 { 4184 frame-number = <3>; 4185 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4186 reg = <0 0x17c27000 0 0x1000>; 4187 status = "disabled"; 4188 }; 4189 4190 frame@17c29000 { 4191 frame-number = <4>; 4192 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4193 reg = <0 0x17c29000 0 0x1000>; 4194 status = "disabled"; 4195 }; 4196 4197 frame@17c2b000 { 4198 frame-number = <5>; 4199 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4200 reg = <0 0x17c2b000 0 0x1000>; 4201 status = "disabled"; 4202 }; 4203 4204 frame@17c2d000 { 4205 frame-number = <6>; 4206 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4207 reg = <0 0x17c2d000 0 0x1000>; 4208 status = "disabled"; 4209 }; 4210 }; 4211 4212 apps_rsc: rsc@18200000 { 4213 compatible = "qcom,rpmh-rsc"; 4214 reg = <0 0x18200000 0 0x10000>, 4215 <0 0x18210000 0 0x10000>, 4216 <0 0x18220000 0 0x10000>; 4217 reg-names = "drv-0", "drv-1", "drv-2"; 4218 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4221 qcom,tcs-offset = <0xd00>; 4222 qcom,drv-id = <2>; 4223 qcom,tcs-config = <ACTIVE_TCS 2>, 4224 <SLEEP_TCS 3>, 4225 <WAKE_TCS 3>, 4226 <CONTROL_TCS 1>; 4227 4228 apps_bcm_voter: bcm-voter { 4229 compatible = "qcom,bcm-voter"; 4230 }; 4231 4232 rpmhpd: power-controller { 4233 compatible = "qcom,sc7280-rpmhpd"; 4234 #power-domain-cells = <1>; 4235 operating-points-v2 = <&rpmhpd_opp_table>; 4236 4237 rpmhpd_opp_table: opp-table { 4238 compatible = "operating-points-v2"; 4239 4240 rpmhpd_opp_ret: opp1 { 4241 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4242 }; 4243 4244 rpmhpd_opp_low_svs: opp2 { 4245 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4246 }; 4247 4248 rpmhpd_opp_svs: opp3 { 4249 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4250 }; 4251 4252 rpmhpd_opp_svs_l1: opp4 { 4253 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4254 }; 4255 4256 rpmhpd_opp_svs_l2: opp5 { 4257 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4258 }; 4259 4260 rpmhpd_opp_nom: opp6 { 4261 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4262 }; 4263 4264 rpmhpd_opp_nom_l1: opp7 { 4265 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4266 }; 4267 4268 rpmhpd_opp_turbo: opp8 { 4269 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4270 }; 4271 4272 rpmhpd_opp_turbo_l1: opp9 { 4273 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4274 }; 4275 }; 4276 }; 4277 4278 rpmhcc: clock-controller { 4279 compatible = "qcom,sc7280-rpmh-clk"; 4280 clocks = <&xo_board>; 4281 clock-names = "xo"; 4282 #clock-cells = <1>; 4283 }; 4284 }; 4285 4286 cpufreq_hw: cpufreq@18591000 { 4287 compatible = "qcom,cpufreq-epss"; 4288 reg = <0 0x18591000 0 0x1000>, 4289 <0 0x18592000 0 0x1000>, 4290 <0 0x18593000 0 0x1000>; 4291 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4292 clock-names = "xo", "alternate"; 4293 #freq-domain-cells = <1>; 4294 }; 4295 }; 4296 4297 thermal_zones: thermal-zones { 4298 cpu0-thermal { 4299 polling-delay-passive = <250>; 4300 polling-delay = <0>; 4301 4302 thermal-sensors = <&tsens0 1>; 4303 4304 trips { 4305 cpu0_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "passive"; 4309 }; 4310 4311 cpu0_alert1: trip-point1 { 4312 temperature = <95000>; 4313 hysteresis = <2000>; 4314 type = "passive"; 4315 }; 4316 4317 cpu0_crit: cpu-crit { 4318 temperature = <110000>; 4319 hysteresis = <0>; 4320 type = "critical"; 4321 }; 4322 }; 4323 4324 cooling-maps { 4325 map0 { 4326 trip = <&cpu0_alert0>; 4327 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4331 }; 4332 map1 { 4333 trip = <&cpu0_alert1>; 4334 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4338 }; 4339 }; 4340 }; 4341 4342 cpu1-thermal { 4343 polling-delay-passive = <250>; 4344 polling-delay = <0>; 4345 4346 thermal-sensors = <&tsens0 2>; 4347 4348 trips { 4349 cpu1_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "passive"; 4353 }; 4354 4355 cpu1_alert1: trip-point1 { 4356 temperature = <95000>; 4357 hysteresis = <2000>; 4358 type = "passive"; 4359 }; 4360 4361 cpu1_crit: cpu-crit { 4362 temperature = <110000>; 4363 hysteresis = <0>; 4364 type = "critical"; 4365 }; 4366 }; 4367 4368 cooling-maps { 4369 map0 { 4370 trip = <&cpu1_alert0>; 4371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4375 }; 4376 map1 { 4377 trip = <&cpu1_alert1>; 4378 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382 }; 4383 }; 4384 }; 4385 4386 cpu2-thermal { 4387 polling-delay-passive = <250>; 4388 polling-delay = <0>; 4389 4390 thermal-sensors = <&tsens0 3>; 4391 4392 trips { 4393 cpu2_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu2_alert1: trip-point1 { 4400 temperature = <95000>; 4401 hysteresis = <2000>; 4402 type = "passive"; 4403 }; 4404 4405 cpu2_crit: cpu-crit { 4406 temperature = <110000>; 4407 hysteresis = <0>; 4408 type = "critical"; 4409 }; 4410 }; 4411 4412 cooling-maps { 4413 map0 { 4414 trip = <&cpu2_alert0>; 4415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4419 }; 4420 map1 { 4421 trip = <&cpu2_alert1>; 4422 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4426 }; 4427 }; 4428 }; 4429 4430 cpu3-thermal { 4431 polling-delay-passive = <250>; 4432 polling-delay = <0>; 4433 4434 thermal-sensors = <&tsens0 4>; 4435 4436 trips { 4437 cpu3_alert0: trip-point0 { 4438 temperature = <90000>; 4439 hysteresis = <2000>; 4440 type = "passive"; 4441 }; 4442 4443 cpu3_alert1: trip-point1 { 4444 temperature = <95000>; 4445 hysteresis = <2000>; 4446 type = "passive"; 4447 }; 4448 4449 cpu3_crit: cpu-crit { 4450 temperature = <110000>; 4451 hysteresis = <0>; 4452 type = "critical"; 4453 }; 4454 }; 4455 4456 cooling-maps { 4457 map0 { 4458 trip = <&cpu3_alert0>; 4459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4463 }; 4464 map1 { 4465 trip = <&cpu3_alert1>; 4466 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4470 }; 4471 }; 4472 }; 4473 4474 cpu4-thermal { 4475 polling-delay-passive = <250>; 4476 polling-delay = <0>; 4477 4478 thermal-sensors = <&tsens0 7>; 4479 4480 trips { 4481 cpu4_alert0: trip-point0 { 4482 temperature = <90000>; 4483 hysteresis = <2000>; 4484 type = "passive"; 4485 }; 4486 4487 cpu4_alert1: trip-point1 { 4488 temperature = <95000>; 4489 hysteresis = <2000>; 4490 type = "passive"; 4491 }; 4492 4493 cpu4_crit: cpu-crit { 4494 temperature = <110000>; 4495 hysteresis = <0>; 4496 type = "critical"; 4497 }; 4498 }; 4499 4500 cooling-maps { 4501 map0 { 4502 trip = <&cpu4_alert0>; 4503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4507 }; 4508 map1 { 4509 trip = <&cpu4_alert1>; 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4514 }; 4515 }; 4516 }; 4517 4518 cpu5-thermal { 4519 polling-delay-passive = <250>; 4520 polling-delay = <0>; 4521 4522 thermal-sensors = <&tsens0 8>; 4523 4524 trips { 4525 cpu5_alert0: trip-point0 { 4526 temperature = <90000>; 4527 hysteresis = <2000>; 4528 type = "passive"; 4529 }; 4530 4531 cpu5_alert1: trip-point1 { 4532 temperature = <95000>; 4533 hysteresis = <2000>; 4534 type = "passive"; 4535 }; 4536 4537 cpu5_crit: cpu-crit { 4538 temperature = <110000>; 4539 hysteresis = <0>; 4540 type = "critical"; 4541 }; 4542 }; 4543 4544 cooling-maps { 4545 map0 { 4546 trip = <&cpu5_alert0>; 4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4551 }; 4552 map1 { 4553 trip = <&cpu5_alert1>; 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4558 }; 4559 }; 4560 }; 4561 4562 cpu6-thermal { 4563 polling-delay-passive = <250>; 4564 polling-delay = <0>; 4565 4566 thermal-sensors = <&tsens0 9>; 4567 4568 trips { 4569 cpu6_alert0: trip-point0 { 4570 temperature = <90000>; 4571 hysteresis = <2000>; 4572 type = "passive"; 4573 }; 4574 4575 cpu6_alert1: trip-point1 { 4576 temperature = <95000>; 4577 hysteresis = <2000>; 4578 type = "passive"; 4579 }; 4580 4581 cpu6_crit: cpu-crit { 4582 temperature = <110000>; 4583 hysteresis = <0>; 4584 type = "critical"; 4585 }; 4586 }; 4587 4588 cooling-maps { 4589 map0 { 4590 trip = <&cpu6_alert0>; 4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4595 }; 4596 map1 { 4597 trip = <&cpu6_alert1>; 4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4602 }; 4603 }; 4604 }; 4605 4606 cpu7-thermal { 4607 polling-delay-passive = <250>; 4608 polling-delay = <0>; 4609 4610 thermal-sensors = <&tsens0 10>; 4611 4612 trips { 4613 cpu7_alert0: trip-point0 { 4614 temperature = <90000>; 4615 hysteresis = <2000>; 4616 type = "passive"; 4617 }; 4618 4619 cpu7_alert1: trip-point1 { 4620 temperature = <95000>; 4621 hysteresis = <2000>; 4622 type = "passive"; 4623 }; 4624 4625 cpu7_crit: cpu-crit { 4626 temperature = <110000>; 4627 hysteresis = <0>; 4628 type = "critical"; 4629 }; 4630 }; 4631 4632 cooling-maps { 4633 map0 { 4634 trip = <&cpu7_alert0>; 4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4639 }; 4640 map1 { 4641 trip = <&cpu7_alert1>; 4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4646 }; 4647 }; 4648 }; 4649 4650 cpu8-thermal { 4651 polling-delay-passive = <250>; 4652 polling-delay = <0>; 4653 4654 thermal-sensors = <&tsens0 11>; 4655 4656 trips { 4657 cpu8_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu8_alert1: trip-point1 { 4664 temperature = <95000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu8_crit: cpu-crit { 4670 temperature = <110000>; 4671 hysteresis = <0>; 4672 type = "critical"; 4673 }; 4674 }; 4675 4676 cooling-maps { 4677 map0 { 4678 trip = <&cpu8_alert0>; 4679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4683 }; 4684 map1 { 4685 trip = <&cpu8_alert1>; 4686 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4688 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4689 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4690 }; 4691 }; 4692 }; 4693 4694 cpu9-thermal { 4695 polling-delay-passive = <250>; 4696 polling-delay = <0>; 4697 4698 thermal-sensors = <&tsens0 12>; 4699 4700 trips { 4701 cpu9_alert0: trip-point0 { 4702 temperature = <90000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu9_alert1: trip-point1 { 4708 temperature = <95000>; 4709 hysteresis = <2000>; 4710 type = "passive"; 4711 }; 4712 4713 cpu9_crit: cpu-crit { 4714 temperature = <110000>; 4715 hysteresis = <0>; 4716 type = "critical"; 4717 }; 4718 }; 4719 4720 cooling-maps { 4721 map0 { 4722 trip = <&cpu9_alert0>; 4723 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4727 }; 4728 map1 { 4729 trip = <&cpu9_alert1>; 4730 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4734 }; 4735 }; 4736 }; 4737 4738 cpu10-thermal { 4739 polling-delay-passive = <250>; 4740 polling-delay = <0>; 4741 4742 thermal-sensors = <&tsens0 13>; 4743 4744 trips { 4745 cpu10_alert0: trip-point0 { 4746 temperature = <90000>; 4747 hysteresis = <2000>; 4748 type = "passive"; 4749 }; 4750 4751 cpu10_alert1: trip-point1 { 4752 temperature = <95000>; 4753 hysteresis = <2000>; 4754 type = "passive"; 4755 }; 4756 4757 cpu10_crit: cpu-crit { 4758 temperature = <110000>; 4759 hysteresis = <0>; 4760 type = "critical"; 4761 }; 4762 }; 4763 4764 cooling-maps { 4765 map0 { 4766 trip = <&cpu10_alert0>; 4767 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4771 }; 4772 map1 { 4773 trip = <&cpu10_alert1>; 4774 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4778 }; 4779 }; 4780 }; 4781 4782 cpu11-thermal { 4783 polling-delay-passive = <250>; 4784 polling-delay = <0>; 4785 4786 thermal-sensors = <&tsens0 14>; 4787 4788 trips { 4789 cpu11_alert0: trip-point0 { 4790 temperature = <90000>; 4791 hysteresis = <2000>; 4792 type = "passive"; 4793 }; 4794 4795 cpu11_alert1: trip-point1 { 4796 temperature = <95000>; 4797 hysteresis = <2000>; 4798 type = "passive"; 4799 }; 4800 4801 cpu11_crit: cpu-crit { 4802 temperature = <110000>; 4803 hysteresis = <0>; 4804 type = "critical"; 4805 }; 4806 }; 4807 4808 cooling-maps { 4809 map0 { 4810 trip = <&cpu11_alert0>; 4811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4815 }; 4816 map1 { 4817 trip = <&cpu11_alert1>; 4818 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4822 }; 4823 }; 4824 }; 4825 4826 aoss0-thermal { 4827 polling-delay-passive = <0>; 4828 polling-delay = <0>; 4829 4830 thermal-sensors = <&tsens0 0>; 4831 4832 trips { 4833 aoss0_alert0: trip-point0 { 4834 temperature = <90000>; 4835 hysteresis = <2000>; 4836 type = "hot"; 4837 }; 4838 4839 aoss0_crit: aoss0-crit { 4840 temperature = <110000>; 4841 hysteresis = <0>; 4842 type = "critical"; 4843 }; 4844 }; 4845 }; 4846 4847 aoss1-thermal { 4848 polling-delay-passive = <0>; 4849 polling-delay = <0>; 4850 4851 thermal-sensors = <&tsens1 0>; 4852 4853 trips { 4854 aoss1_alert0: trip-point0 { 4855 temperature = <90000>; 4856 hysteresis = <2000>; 4857 type = "hot"; 4858 }; 4859 4860 aoss1_crit: aoss1-crit { 4861 temperature = <110000>; 4862 hysteresis = <0>; 4863 type = "critical"; 4864 }; 4865 }; 4866 }; 4867 4868 cpuss0-thermal { 4869 polling-delay-passive = <0>; 4870 polling-delay = <0>; 4871 4872 thermal-sensors = <&tsens0 5>; 4873 4874 trips { 4875 cpuss0_alert0: trip-point0 { 4876 temperature = <90000>; 4877 hysteresis = <2000>; 4878 type = "hot"; 4879 }; 4880 cpuss0_crit: cluster0-crit { 4881 temperature = <110000>; 4882 hysteresis = <0>; 4883 type = "critical"; 4884 }; 4885 }; 4886 }; 4887 4888 cpuss1-thermal { 4889 polling-delay-passive = <0>; 4890 polling-delay = <0>; 4891 4892 thermal-sensors = <&tsens0 6>; 4893 4894 trips { 4895 cpuss1_alert0: trip-point0 { 4896 temperature = <90000>; 4897 hysteresis = <2000>; 4898 type = "hot"; 4899 }; 4900 cpuss1_crit: cluster0-crit { 4901 temperature = <110000>; 4902 hysteresis = <0>; 4903 type = "critical"; 4904 }; 4905 }; 4906 }; 4907 4908 gpuss0-thermal { 4909 polling-delay-passive = <100>; 4910 polling-delay = <0>; 4911 4912 thermal-sensors = <&tsens1 1>; 4913 4914 trips { 4915 gpuss0_alert0: trip-point0 { 4916 temperature = <95000>; 4917 hysteresis = <2000>; 4918 type = "passive"; 4919 }; 4920 4921 gpuss0_crit: gpuss0-crit { 4922 temperature = <110000>; 4923 hysteresis = <0>; 4924 type = "critical"; 4925 }; 4926 }; 4927 4928 cooling-maps { 4929 map0 { 4930 trip = <&gpuss0_alert0>; 4931 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4932 }; 4933 }; 4934 }; 4935 4936 gpuss1-thermal { 4937 polling-delay-passive = <100>; 4938 polling-delay = <0>; 4939 4940 thermal-sensors = <&tsens1 2>; 4941 4942 trips { 4943 gpuss1_alert0: trip-point0 { 4944 temperature = <95000>; 4945 hysteresis = <2000>; 4946 type = "passive"; 4947 }; 4948 4949 gpuss1_crit: gpuss1-crit { 4950 temperature = <110000>; 4951 hysteresis = <0>; 4952 type = "critical"; 4953 }; 4954 }; 4955 4956 cooling-maps { 4957 map0 { 4958 trip = <&gpuss1_alert0>; 4959 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4960 }; 4961 }; 4962 }; 4963 4964 nspss0-thermal { 4965 polling-delay-passive = <0>; 4966 polling-delay = <0>; 4967 4968 thermal-sensors = <&tsens1 3>; 4969 4970 trips { 4971 nspss0_alert0: trip-point0 { 4972 temperature = <90000>; 4973 hysteresis = <2000>; 4974 type = "hot"; 4975 }; 4976 4977 nspss0_crit: nspss0-crit { 4978 temperature = <110000>; 4979 hysteresis = <0>; 4980 type = "critical"; 4981 }; 4982 }; 4983 }; 4984 4985 nspss1-thermal { 4986 polling-delay-passive = <0>; 4987 polling-delay = <0>; 4988 4989 thermal-sensors = <&tsens1 4>; 4990 4991 trips { 4992 nspss1_alert0: trip-point0 { 4993 temperature = <90000>; 4994 hysteresis = <2000>; 4995 type = "hot"; 4996 }; 4997 4998 nspss1_crit: nspss1-crit { 4999 temperature = <110000>; 5000 hysteresis = <0>; 5001 type = "critical"; 5002 }; 5003 }; 5004 }; 5005 5006 video-thermal { 5007 polling-delay-passive = <0>; 5008 polling-delay = <0>; 5009 5010 thermal-sensors = <&tsens1 5>; 5011 5012 trips { 5013 video_alert0: trip-point0 { 5014 temperature = <90000>; 5015 hysteresis = <2000>; 5016 type = "hot"; 5017 }; 5018 5019 video_crit: video-crit { 5020 temperature = <110000>; 5021 hysteresis = <0>; 5022 type = "critical"; 5023 }; 5024 }; 5025 }; 5026 5027 ddr-thermal { 5028 polling-delay-passive = <0>; 5029 polling-delay = <0>; 5030 5031 thermal-sensors = <&tsens1 6>; 5032 5033 trips { 5034 ddr_alert0: trip-point0 { 5035 temperature = <90000>; 5036 hysteresis = <2000>; 5037 type = "hot"; 5038 }; 5039 5040 ddr_crit: ddr-crit { 5041 temperature = <110000>; 5042 hysteresis = <0>; 5043 type = "critical"; 5044 }; 5045 }; 5046 }; 5047 5048 mdmss0-thermal { 5049 polling-delay-passive = <0>; 5050 polling-delay = <0>; 5051 5052 thermal-sensors = <&tsens1 7>; 5053 5054 trips { 5055 mdmss0_alert0: trip-point0 { 5056 temperature = <90000>; 5057 hysteresis = <2000>; 5058 type = "hot"; 5059 }; 5060 5061 mdmss0_crit: mdmss0-crit { 5062 temperature = <110000>; 5063 hysteresis = <0>; 5064 type = "critical"; 5065 }; 5066 }; 5067 }; 5068 5069 mdmss1-thermal { 5070 polling-delay-passive = <0>; 5071 polling-delay = <0>; 5072 5073 thermal-sensors = <&tsens1 8>; 5074 5075 trips { 5076 mdmss1_alert0: trip-point0 { 5077 temperature = <90000>; 5078 hysteresis = <2000>; 5079 type = "hot"; 5080 }; 5081 5082 mdmss1_crit: mdmss1-crit { 5083 temperature = <110000>; 5084 hysteresis = <0>; 5085 type = "critical"; 5086 }; 5087 }; 5088 }; 5089 5090 mdmss2-thermal { 5091 polling-delay-passive = <0>; 5092 polling-delay = <0>; 5093 5094 thermal-sensors = <&tsens1 9>; 5095 5096 trips { 5097 mdmss2_alert0: trip-point0 { 5098 temperature = <90000>; 5099 hysteresis = <2000>; 5100 type = "hot"; 5101 }; 5102 5103 mdmss2_crit: mdmss2-crit { 5104 temperature = <110000>; 5105 hysteresis = <0>; 5106 type = "critical"; 5107 }; 5108 }; 5109 }; 5110 5111 mdmss3-thermal { 5112 polling-delay-passive = <0>; 5113 polling-delay = <0>; 5114 5115 thermal-sensors = <&tsens1 10>; 5116 5117 trips { 5118 mdmss3_alert0: trip-point0 { 5119 temperature = <90000>; 5120 hysteresis = <2000>; 5121 type = "hot"; 5122 }; 5123 5124 mdmss3_crit: mdmss3-crit { 5125 temperature = <110000>; 5126 hysteresis = <0>; 5127 type = "critical"; 5128 }; 5129 }; 5130 }; 5131 5132 camera0-thermal { 5133 polling-delay-passive = <0>; 5134 polling-delay = <0>; 5135 5136 thermal-sensors = <&tsens1 11>; 5137 5138 trips { 5139 camera0_alert0: trip-point0 { 5140 temperature = <90000>; 5141 hysteresis = <2000>; 5142 type = "hot"; 5143 }; 5144 5145 camera0_crit: camera0-crit { 5146 temperature = <110000>; 5147 hysteresis = <0>; 5148 type = "critical"; 5149 }; 5150 }; 5151 }; 5152 }; 5153 5154 timer { 5155 compatible = "arm,armv8-timer"; 5156 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5157 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5158 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5159 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5160 }; 5161}; 5162