1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 video_mem: memory@8b200000 { 133 reg = <0x0 0x8b200000 0x0 0x500000>; 134 no-map; 135 }; 136 137 ipa_fw_mem: memory@8b700000 { 138 reg = <0 0x8b700000 0 0x10000>; 139 no-map; 140 }; 141 142 rmtfs_mem: memory@9c900000 { 143 compatible = "qcom,rmtfs-mem"; 144 reg = <0x0 0x9c900000 0x0 0x280000>; 145 no-map; 146 147 qcom,client-id = <1>; 148 qcom,vmid = <15>; 149 }; 150 }; 151 152 cpus { 153 #address-cells = <2>; 154 #size-cells = <0>; 155 156 CPU0: cpu@0 { 157 device_type = "cpu"; 158 compatible = "arm,kryo"; 159 reg = <0x0 0x0>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 #cooling-cells = <2>; 167 L2_0: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 L3_0: l3-cache { 171 compatible = "cache"; 172 }; 173 }; 174 }; 175 176 CPU1: cpu@100 { 177 device_type = "cpu"; 178 compatible = "arm,kryo"; 179 reg = <0x0 0x100>; 180 enable-method = "psci"; 181 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 182 &LITTLE_CPU_SLEEP_1 183 &CLUSTER_SLEEP_0>; 184 next-level-cache = <&L2_100>; 185 qcom,freq-domain = <&cpufreq_hw 0>; 186 #cooling-cells = <2>; 187 L2_100: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU2: cpu@200 { 194 device_type = "cpu"; 195 compatible = "arm,kryo"; 196 reg = <0x0 0x200>; 197 enable-method = "psci"; 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 199 &LITTLE_CPU_SLEEP_1 200 &CLUSTER_SLEEP_0>; 201 next-level-cache = <&L2_200>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_200: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU3: cpu@300 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x300>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_300>; 219 qcom,freq-domain = <&cpufreq_hw 0>; 220 #cooling-cells = <2>; 221 L2_300: l2-cache { 222 compatible = "cache"; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU4: cpu@400 { 228 device_type = "cpu"; 229 compatible = "arm,kryo"; 230 reg = <0x0 0x400>; 231 enable-method = "psci"; 232 cpu-idle-states = <&BIG_CPU_SLEEP_0 233 &BIG_CPU_SLEEP_1 234 &CLUSTER_SLEEP_0>; 235 next-level-cache = <&L2_400>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 #cooling-cells = <2>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "arm,kryo"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 250 &BIG_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 next-level-cache = <&L2_500>; 253 qcom,freq-domain = <&cpufreq_hw 1>; 254 #cooling-cells = <2>; 255 L2_500: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU6: cpu@600 { 262 device_type = "cpu"; 263 compatible = "arm,kryo"; 264 reg = <0x0 0x600>; 265 enable-method = "psci"; 266 cpu-idle-states = <&BIG_CPU_SLEEP_0 267 &BIG_CPU_SLEEP_1 268 &CLUSTER_SLEEP_0>; 269 next-level-cache = <&L2_600>; 270 qcom,freq-domain = <&cpufreq_hw 1>; 271 #cooling-cells = <2>; 272 L2_600: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "arm,kryo"; 281 reg = <0x0 0x700>; 282 enable-method = "psci"; 283 cpu-idle-states = <&BIG_CPU_SLEEP_0 284 &BIG_CPU_SLEEP_1 285 &CLUSTER_SLEEP_0>; 286 next-level-cache = <&L2_700>; 287 qcom,freq-domain = <&cpufreq_hw 2>; 288 #cooling-cells = <2>; 289 L2_700: l2-cache { 290 compatible = "cache"; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "little-power-down"; 337 arm,psci-suspend-param = <0x40000003>; 338 entry-latency-us = <549>; 339 exit-latency-us = <901>; 340 min-residency-us = <1774>; 341 local-timer-stop; 342 }; 343 344 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "little-rail-power-down"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <915>; 350 min-residency-us = <4001>; 351 local-timer-stop; 352 }; 353 354 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 355 compatible = "arm,idle-state"; 356 idle-state-name = "big-power-down"; 357 arm,psci-suspend-param = <0x40000003>; 358 entry-latency-us = <523>; 359 exit-latency-us = <1244>; 360 min-residency-us = <2207>; 361 local-timer-stop; 362 }; 363 364 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 365 compatible = "arm,idle-state"; 366 idle-state-name = "big-rail-power-down"; 367 arm,psci-suspend-param = <0x40000004>; 368 entry-latency-us = <526>; 369 exit-latency-us = <1854>; 370 min-residency-us = <5555>; 371 local-timer-stop; 372 }; 373 374 CLUSTER_SLEEP_0: cluster-sleep-0 { 375 compatible = "arm,idle-state"; 376 idle-state-name = "cluster-power-down"; 377 arm,psci-suspend-param = <0x40003444>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9926>; 381 local-timer-stop; 382 }; 383 }; 384 }; 385 386 memory@80000000 { 387 device_type = "memory"; 388 /* We expect the bootloader to fill in the size */ 389 reg = <0 0x80000000 0 0>; 390 }; 391 392 firmware { 393 scm { 394 compatible = "qcom,scm-sc7280", "qcom,scm"; 395 }; 396 }; 397 398 clk_virt: interconnect { 399 compatible = "qcom,sc7280-clk-virt"; 400 #interconnect-cells = <2>; 401 qcom,bcm-voters = <&apps_bcm_voter>; 402 }; 403 404 smem { 405 compatible = "qcom,smem"; 406 memory-region = <&smem_mem>; 407 hwlocks = <&tcsr_mutex 3>; 408 }; 409 410 smp2p-adsp { 411 compatible = "qcom,smp2p"; 412 qcom,smem = <443>, <429>; 413 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 414 IPCC_MPROC_SIGNAL_SMP2P 415 IRQ_TYPE_EDGE_RISING>; 416 mboxes = <&ipcc IPCC_CLIENT_LPASS 417 IPCC_MPROC_SIGNAL_SMP2P>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <2>; 421 422 adsp_smp2p_out: master-kernel { 423 qcom,entry-name = "master-kernel"; 424 #qcom,smem-state-cells = <1>; 425 }; 426 427 adsp_smp2p_in: slave-kernel { 428 qcom,entry-name = "slave-kernel"; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 smp2p-cdsp { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <94>, <432>; 437 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 438 IPCC_MPROC_SIGNAL_SMP2P 439 IRQ_TYPE_EDGE_RISING>; 440 mboxes = <&ipcc IPCC_CLIENT_CDSP 441 IPCC_MPROC_SIGNAL_SMP2P>; 442 443 qcom,local-pid = <0>; 444 qcom,remote-pid = <5>; 445 446 cdsp_smp2p_out: master-kernel { 447 qcom,entry-name = "master-kernel"; 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 cdsp_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 smp2p-mpss { 459 compatible = "qcom,smp2p"; 460 qcom,smem = <435>, <428>; 461 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 462 IPCC_MPROC_SIGNAL_SMP2P 463 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&ipcc IPCC_CLIENT_MPSS 465 IPCC_MPROC_SIGNAL_SMP2P>; 466 467 qcom,local-pid = <0>; 468 qcom,remote-pid = <1>; 469 470 modem_smp2p_out: master-kernel { 471 qcom,entry-name = "master-kernel"; 472 #qcom,smem-state-cells = <1>; 473 }; 474 475 modem_smp2p_in: slave-kernel { 476 qcom,entry-name = "slave-kernel"; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 ipa_smp2p_out: ipa-ap-to-modem { 482 qcom,entry-name = "ipa"; 483 #qcom,smem-state-cells = <1>; 484 }; 485 486 ipa_smp2p_in: ipa-modem-to-ap { 487 qcom,entry-name = "ipa"; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 }; 492 493 smp2p-wpss { 494 compatible = "qcom,smp2p"; 495 qcom,smem = <617>, <616>; 496 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 497 IPCC_MPROC_SIGNAL_SMP2P 498 IRQ_TYPE_EDGE_RISING>; 499 mboxes = <&ipcc IPCC_CLIENT_WPSS 500 IPCC_MPROC_SIGNAL_SMP2P>; 501 502 qcom,local-pid = <0>; 503 qcom,remote-pid = <13>; 504 505 wpss_smp2p_out: master-kernel { 506 qcom,entry-name = "master-kernel"; 507 #qcom,smem-state-cells = <1>; 508 }; 509 510 wpss_smp2p_in: slave-kernel { 511 qcom,entry-name = "slave-kernel"; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 }; 516 517 pmu { 518 compatible = "arm,armv8-pmuv3"; 519 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 520 }; 521 522 psci { 523 compatible = "arm,psci-1.0"; 524 method = "smc"; 525 }; 526 527 qspi_opp_table: qspi-opp-table { 528 compatible = "operating-points-v2"; 529 530 opp-75000000 { 531 opp-hz = /bits/ 64 <75000000>; 532 required-opps = <&rpmhpd_opp_low_svs>; 533 }; 534 535 opp-150000000 { 536 opp-hz = /bits/ 64 <150000000>; 537 required-opps = <&rpmhpd_opp_svs>; 538 }; 539 540 opp-200000000 { 541 opp-hz = /bits/ 64 <200000000>; 542 required-opps = <&rpmhpd_opp_svs_l1>; 543 }; 544 545 opp-300000000 { 546 opp-hz = /bits/ 64 <300000000>; 547 required-opps = <&rpmhpd_opp_nom>; 548 }; 549 }; 550 551 qup_opp_table: qup-opp-table { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 564 opp-128000000 { 565 opp-hz = /bits/ 64 <128000000>; 566 required-opps = <&rpmhpd_opp_nom>; 567 }; 568 }; 569 570 soc: soc@0 { 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges = <0 0 0 0 0x10 0>; 574 dma-ranges = <0 0 0 0 0x10 0>; 575 compatible = "simple-bus"; 576 577 gcc: clock-controller@100000 { 578 compatible = "qcom,gcc-sc7280"; 579 reg = <0 0x00100000 0 0x1f0000>; 580 clocks = <&rpmhcc RPMH_CXO_CLK>, 581 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 582 <0>, <0>, <0>, <0>, <0>, <0>; 583 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 584 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 585 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 586 "ufs_phy_tx_symbol_0_clk", 587 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 588 #clock-cells = <1>; 589 #reset-cells = <1>; 590 #power-domain-cells = <1>; 591 }; 592 593 ipcc: mailbox@408000 { 594 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 595 reg = <0 0x00408000 0 0x1000>; 596 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 597 interrupt-controller; 598 #interrupt-cells = <3>; 599 #mbox-cells = <2>; 600 }; 601 602 qfprom: efuse@784000 { 603 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 604 reg = <0 0x00784000 0 0xa20>, 605 <0 0x00780000 0 0xa20>, 606 <0 0x00782000 0 0x120>, 607 <0 0x00786000 0 0x1fff>; 608 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 609 clock-names = "core"; 610 power-domains = <&rpmhpd SC7280_MX>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 }; 614 615 sdhc_1: sdhci@7c4000 { 616 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 617 status = "disabled"; 618 619 reg = <0 0x007c4000 0 0x1000>, 620 <0 0x007c5000 0 0x1000>; 621 reg-names = "hc", "cqhci"; 622 623 iommus = <&apps_smmu 0xc0 0x0>; 624 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "hc_irq", "pwr_irq"; 627 628 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 629 <&gcc GCC_SDCC1_AHB_CLK>, 630 <&rpmhcc RPMH_CXO_CLK>; 631 clock-names = "core", "iface", "xo"; 632 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 634 interconnect-names = "sdhc-ddr","cpu-sdhc"; 635 power-domains = <&rpmhpd SC7280_CX>; 636 operating-points-v2 = <&sdhc1_opp_table>; 637 638 bus-width = <8>; 639 supports-cqe; 640 641 qcom,dll-config = <0x0007642c>; 642 qcom,ddr-config = <0x80040868>; 643 644 mmc-ddr-1_8v; 645 mmc-hs200-1_8v; 646 mmc-hs400-1_8v; 647 mmc-hs400-enhanced-strobe; 648 649 sdhc1_opp_table: opp-table { 650 compatible = "operating-points-v2"; 651 652 opp-100000000 { 653 opp-hz = /bits/ 64 <100000000>; 654 required-opps = <&rpmhpd_opp_low_svs>; 655 opp-peak-kBps = <1800000 400000>; 656 opp-avg-kBps = <100000 0>; 657 }; 658 659 opp-384000000 { 660 opp-hz = /bits/ 64 <384000000>; 661 required-opps = <&rpmhpd_opp_nom>; 662 opp-peak-kBps = <5400000 1600000>; 663 opp-avg-kBps = <390000 0>; 664 }; 665 }; 666 667 }; 668 669 qupv3_id_0: geniqup@9c0000 { 670 compatible = "qcom,geni-se-qup"; 671 reg = <0 0x009c0000 0 0x2000>; 672 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 673 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 674 clock-names = "m-ahb", "s-ahb"; 675 #address-cells = <2>; 676 #size-cells = <2>; 677 ranges; 678 iommus = <&apps_smmu 0x123 0x0>; 679 status = "disabled"; 680 681 i2c0: i2c@980000 { 682 compatible = "qcom,geni-i2c"; 683 reg = <0 0x00980000 0 0x4000>; 684 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 685 clock-names = "se"; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&qup_i2c0_data_clk>; 688 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 692 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 693 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 694 interconnect-names = "qup-core", "qup-config", 695 "qup-memory"; 696 status = "disabled"; 697 }; 698 699 spi0: spi@980000 { 700 compatible = "qcom,geni-spi"; 701 reg = <0 0x00980000 0 0x4000>; 702 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 703 clock-names = "se"; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 706 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 power-domains = <&rpmhpd SC7280_CX>; 710 operating-points-v2 = <&qup_opp_table>; 711 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 712 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 713 interconnect-names = "qup-core", "qup-config"; 714 status = "disabled"; 715 }; 716 717 uart0: serial@980000 { 718 compatible = "qcom,geni-uart"; 719 reg = <0 0x00980000 0 0x4000>; 720 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 721 clock-names = "se"; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 724 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 725 power-domains = <&rpmhpd SC7280_CX>; 726 operating-points-v2 = <&qup_opp_table>; 727 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 728 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 729 interconnect-names = "qup-core", "qup-config"; 730 status = "disabled"; 731 }; 732 733 i2c1: i2c@984000 { 734 compatible = "qcom,geni-i2c"; 735 reg = <0 0x00984000 0 0x4000>; 736 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 737 clock-names = "se"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&qup_i2c1_data_clk>; 740 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 745 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 746 interconnect-names = "qup-core", "qup-config", 747 "qup-memory"; 748 status = "disabled"; 749 }; 750 751 spi1: spi@984000 { 752 compatible = "qcom,geni-spi"; 753 reg = <0 0x00984000 0 0x4000>; 754 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 755 clock-names = "se"; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 758 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 power-domains = <&rpmhpd SC7280_CX>; 762 operating-points-v2 = <&qup_opp_table>; 763 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 764 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 765 interconnect-names = "qup-core", "qup-config"; 766 status = "disabled"; 767 }; 768 769 uart1: serial@984000 { 770 compatible = "qcom,geni-uart"; 771 reg = <0 0x00984000 0 0x4000>; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 773 clock-names = "se"; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 776 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 777 power-domains = <&rpmhpd SC7280_CX>; 778 operating-points-v2 = <&qup_opp_table>; 779 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 780 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 781 interconnect-names = "qup-core", "qup-config"; 782 status = "disabled"; 783 }; 784 785 i2c2: i2c@988000 { 786 compatible = "qcom,geni-i2c"; 787 reg = <0 0x00988000 0 0x4000>; 788 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 789 clock-names = "se"; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&qup_i2c2_data_clk>; 792 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 796 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 797 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 798 interconnect-names = "qup-core", "qup-config", 799 "qup-memory"; 800 status = "disabled"; 801 }; 802 803 spi2: spi@988000 { 804 compatible = "qcom,geni-spi"; 805 reg = <0 0x00988000 0 0x4000>; 806 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 807 clock-names = "se"; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 810 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 power-domains = <&rpmhpd SC7280_CX>; 814 operating-points-v2 = <&qup_opp_table>; 815 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 816 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 817 interconnect-names = "qup-core", "qup-config"; 818 status = "disabled"; 819 }; 820 821 uart2: serial@988000 { 822 compatible = "qcom,geni-uart"; 823 reg = <0 0x00988000 0 0x4000>; 824 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 825 clock-names = "se"; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 828 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 829 power-domains = <&rpmhpd SC7280_CX>; 830 operating-points-v2 = <&qup_opp_table>; 831 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 832 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 833 interconnect-names = "qup-core", "qup-config"; 834 status = "disabled"; 835 }; 836 837 i2c3: i2c@98c000 { 838 compatible = "qcom,geni-i2c"; 839 reg = <0 0x0098c000 0 0x4000>; 840 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 841 clock-names = "se"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_i2c3_data_clk>; 844 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 848 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 849 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 850 interconnect-names = "qup-core", "qup-config", 851 "qup-memory"; 852 status = "disabled"; 853 }; 854 855 spi3: spi@98c000 { 856 compatible = "qcom,geni-spi"; 857 reg = <0 0x0098c000 0 0x4000>; 858 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 859 clock-names = "se"; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 862 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 power-domains = <&rpmhpd SC7280_CX>; 866 operating-points-v2 = <&qup_opp_table>; 867 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 868 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 869 interconnect-names = "qup-core", "qup-config"; 870 status = "disabled"; 871 }; 872 873 uart3: serial@98c000 { 874 compatible = "qcom,geni-uart"; 875 reg = <0 0x0098c000 0 0x4000>; 876 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 877 clock-names = "se"; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 880 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 881 power-domains = <&rpmhpd SC7280_CX>; 882 operating-points-v2 = <&qup_opp_table>; 883 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 884 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 885 interconnect-names = "qup-core", "qup-config"; 886 status = "disabled"; 887 }; 888 889 i2c4: i2c@990000 { 890 compatible = "qcom,geni-i2c"; 891 reg = <0 0x00990000 0 0x4000>; 892 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 893 clock-names = "se"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&qup_i2c4_data_clk>; 896 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 900 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 901 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 902 interconnect-names = "qup-core", "qup-config", 903 "qup-memory"; 904 status = "disabled"; 905 }; 906 907 spi4: spi@990000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00990000 0 0x4000>; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 911 clock-names = "se"; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 914 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 power-domains = <&rpmhpd SC7280_CX>; 918 operating-points-v2 = <&qup_opp_table>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 921 interconnect-names = "qup-core", "qup-config"; 922 status = "disabled"; 923 }; 924 925 uart4: serial@990000 { 926 compatible = "qcom,geni-uart"; 927 reg = <0 0x00990000 0 0x4000>; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 929 clock-names = "se"; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 932 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 933 power-domains = <&rpmhpd SC7280_CX>; 934 operating-points-v2 = <&qup_opp_table>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 937 interconnect-names = "qup-core", "qup-config"; 938 status = "disabled"; 939 }; 940 941 i2c5: i2c@994000 { 942 compatible = "qcom,geni-i2c"; 943 reg = <0 0x00994000 0 0x4000>; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 945 clock-names = "se"; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_i2c5_data_clk>; 948 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 953 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 954 interconnect-names = "qup-core", "qup-config", 955 "qup-memory"; 956 status = "disabled"; 957 }; 958 959 spi5: spi@994000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0 0x00994000 0 0x4000>; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 963 clock-names = "se"; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 966 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 power-domains = <&rpmhpd SC7280_CX>; 970 operating-points-v2 = <&qup_opp_table>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 973 interconnect-names = "qup-core", "qup-config"; 974 status = "disabled"; 975 }; 976 977 uart5: serial@994000 { 978 compatible = "qcom,geni-uart"; 979 reg = <0 0x00994000 0 0x4000>; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 981 clock-names = "se"; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 984 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 985 power-domains = <&rpmhpd SC7280_CX>; 986 operating-points-v2 = <&qup_opp_table>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 989 interconnect-names = "qup-core", "qup-config"; 990 status = "disabled"; 991 }; 992 993 i2c6: i2c@998000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00998000 0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 997 clock-names = "se"; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c6_data_clk>; 1000 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1005 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", 1007 "qup-memory"; 1008 status = "disabled"; 1009 }; 1010 1011 spi6: spi@998000 { 1012 compatible = "qcom,geni-spi"; 1013 reg = <0 0x00998000 0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1015 clock-names = "se"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1018 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 power-domains = <&rpmhpd SC7280_CX>; 1022 operating-points-v2 = <&qup_opp_table>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1025 interconnect-names = "qup-core", "qup-config"; 1026 status = "disabled"; 1027 }; 1028 1029 uart6: serial@998000 { 1030 compatible = "qcom,geni-uart"; 1031 reg = <0 0x00998000 0 0x4000>; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1033 clock-names = "se"; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1036 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1037 power-domains = <&rpmhpd SC7280_CX>; 1038 operating-points-v2 = <&qup_opp_table>; 1039 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1040 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1041 interconnect-names = "qup-core", "qup-config"; 1042 status = "disabled"; 1043 }; 1044 1045 i2c7: i2c@99c000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0 0x0099c000 0 0x4000>; 1048 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1049 clock-names = "se"; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_i2c7_data_clk>; 1052 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1057 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1058 interconnect-names = "qup-core", "qup-config", 1059 "qup-memory"; 1060 status = "disabled"; 1061 }; 1062 1063 spi7: spi@99c000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0 0x0099c000 0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1067 clock-names = "se"; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1070 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 power-domains = <&rpmhpd SC7280_CX>; 1074 operating-points-v2 = <&qup_opp_table>; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1076 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 status = "disabled"; 1079 }; 1080 1081 uart7: serial@99c000 { 1082 compatible = "qcom,geni-uart"; 1083 reg = <0 0x0099c000 0 0x4000>; 1084 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1085 clock-names = "se"; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1088 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1089 power-domains = <&rpmhpd SC7280_CX>; 1090 operating-points-v2 = <&qup_opp_table>; 1091 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1093 interconnect-names = "qup-core", "qup-config"; 1094 status = "disabled"; 1095 }; 1096 }; 1097 1098 qupv3_id_1: geniqup@ac0000 { 1099 compatible = "qcom,geni-se-qup"; 1100 reg = <0 0x00ac0000 0 0x2000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1102 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1103 clock-names = "m-ahb", "s-ahb"; 1104 #address-cells = <2>; 1105 #size-cells = <2>; 1106 ranges; 1107 iommus = <&apps_smmu 0x43 0x0>; 1108 status = "disabled"; 1109 1110 i2c8: i2c@a80000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x00a80000 0 0x4000>; 1113 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1114 clock-names = "se"; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c8_data_clk>; 1117 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1121 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1122 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1123 interconnect-names = "qup-core", "qup-config", 1124 "qup-memory"; 1125 status = "disabled"; 1126 }; 1127 1128 spi8: spi@a80000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00a80000 0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1132 clock-names = "se"; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1135 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 status = "disabled"; 1144 }; 1145 1146 uart8: serial@a80000 { 1147 compatible = "qcom,geni-uart"; 1148 reg = <0 0x00a80000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1153 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&rpmhpd SC7280_CX>; 1155 operating-points-v2 = <&qup_opp_table>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1158 interconnect-names = "qup-core", "qup-config"; 1159 status = "disabled"; 1160 }; 1161 1162 i2c9: i2c@a84000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x00a84000 0 0x4000>; 1165 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1166 clock-names = "se"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&qup_i2c9_data_clk>; 1169 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1174 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", 1176 "qup-memory"; 1177 status = "disabled"; 1178 }; 1179 1180 spi9: spi@a84000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0 0x00a84000 0 0x4000>; 1183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1184 clock-names = "se"; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1187 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 power-domains = <&rpmhpd SC7280_CX>; 1191 operating-points-v2 = <&qup_opp_table>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1193 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1194 interconnect-names = "qup-core", "qup-config"; 1195 status = "disabled"; 1196 }; 1197 1198 uart9: serial@a84000 { 1199 compatible = "qcom,geni-uart"; 1200 reg = <0 0x00a84000 0 0x4000>; 1201 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1202 clock-names = "se"; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1205 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1206 power-domains = <&rpmhpd SC7280_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1210 interconnect-names = "qup-core", "qup-config"; 1211 status = "disabled"; 1212 }; 1213 1214 i2c10: i2c@a88000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0 0x00a88000 0 0x4000>; 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1218 clock-names = "se"; 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&qup_i2c10_data_clk>; 1221 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1225 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1226 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", 1228 "qup-memory"; 1229 status = "disabled"; 1230 }; 1231 1232 spi10: spi@a88000 { 1233 compatible = "qcom,geni-spi"; 1234 reg = <0 0x00a88000 0 0x4000>; 1235 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1236 clock-names = "se"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1239 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 power-domains = <&rpmhpd SC7280_CX>; 1243 operating-points-v2 = <&qup_opp_table>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1246 interconnect-names = "qup-core", "qup-config"; 1247 status = "disabled"; 1248 }; 1249 1250 uart10: serial@a88000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00a88000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1257 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c11: i2c@a8c000 { 1267 compatible = "qcom,geni-i2c"; 1268 reg = <0 0x00a8c000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_i2c11_data_clk>; 1273 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1278 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", 1280 "qup-memory"; 1281 status = "disabled"; 1282 }; 1283 1284 spi11: spi@a8c000 { 1285 compatible = "qcom,geni-spi"; 1286 reg = <0 0x00a8c000 0 0x4000>; 1287 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1288 clock-names = "se"; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1291 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 power-domains = <&rpmhpd SC7280_CX>; 1295 operating-points-v2 = <&qup_opp_table>; 1296 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1297 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 status = "disabled"; 1300 }; 1301 1302 uart11: serial@a8c000 { 1303 compatible = "qcom,geni-uart"; 1304 reg = <0 0x00a8c000 0 0x4000>; 1305 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1306 clock-names = "se"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1309 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1310 power-domains = <&rpmhpd SC7280_CX>; 1311 operating-points-v2 = <&qup_opp_table>; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1313 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1314 interconnect-names = "qup-core", "qup-config"; 1315 status = "disabled"; 1316 }; 1317 1318 i2c12: i2c@a90000 { 1319 compatible = "qcom,geni-i2c"; 1320 reg = <0 0x00a90000 0 0x4000>; 1321 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1322 clock-names = "se"; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_i2c12_data_clk>; 1325 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1330 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1331 interconnect-names = "qup-core", "qup-config", 1332 "qup-memory"; 1333 status = "disabled"; 1334 }; 1335 1336 spi12: spi@a90000 { 1337 compatible = "qcom,geni-spi"; 1338 reg = <0 0x00a90000 0 0x4000>; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1340 clock-names = "se"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1343 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 power-domains = <&rpmhpd SC7280_CX>; 1347 operating-points-v2 = <&qup_opp_table>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1350 interconnect-names = "qup-core", "qup-config"; 1351 status = "disabled"; 1352 }; 1353 1354 uart12: serial@a90000 { 1355 compatible = "qcom,geni-uart"; 1356 reg = <0 0x00a90000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1358 clock-names = "se"; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1361 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1362 power-domains = <&rpmhpd SC7280_CX>; 1363 operating-points-v2 = <&qup_opp_table>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1366 interconnect-names = "qup-core", "qup-config"; 1367 status = "disabled"; 1368 }; 1369 1370 i2c13: i2c@a94000 { 1371 compatible = "qcom,geni-i2c"; 1372 reg = <0 0x00a94000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_i2c13_data_clk>; 1377 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1382 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1383 interconnect-names = "qup-core", "qup-config", 1384 "qup-memory"; 1385 status = "disabled"; 1386 }; 1387 1388 spi13: spi@a94000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0 0x00a94000 0 0x4000>; 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1392 clock-names = "se"; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1395 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SC7280_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 status = "disabled"; 1404 }; 1405 1406 uart13: serial@a94000 { 1407 compatible = "qcom,geni-uart"; 1408 reg = <0 0x00a94000 0 0x4000>; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1410 clock-names = "se"; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1413 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC7280_CX>; 1415 operating-points-v2 = <&qup_opp_table>; 1416 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1418 interconnect-names = "qup-core", "qup-config"; 1419 status = "disabled"; 1420 }; 1421 1422 i2c14: i2c@a98000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00a98000 0 0x4000>; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1426 clock-names = "se"; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_i2c14_data_clk>; 1429 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1434 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", 1436 "qup-memory"; 1437 status = "disabled"; 1438 }; 1439 1440 spi14: spi@a98000 { 1441 compatible = "qcom,geni-spi"; 1442 reg = <0 0x00a98000 0 0x4000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1444 clock-names = "se"; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1447 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 power-domains = <&rpmhpd SC7280_CX>; 1451 operating-points-v2 = <&qup_opp_table>; 1452 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1453 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 uart14: serial@a98000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x00a98000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1465 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SC7280_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 status = "disabled"; 1472 }; 1473 1474 i2c15: i2c@a9c000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00a9c000 0 0x4000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1478 clock-names = "se"; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_i2c15_data_clk>; 1481 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1486 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", 1488 "qup-memory"; 1489 status = "disabled"; 1490 }; 1491 1492 spi15: spi@a9c000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0 0x00a9c000 0 0x4000>; 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1496 clock-names = "se"; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1499 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 power-domains = <&rpmhpd SC7280_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1506 interconnect-names = "qup-core", "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 uart15: serial@a9c000 { 1511 compatible = "qcom,geni-uart"; 1512 reg = <0 0x00a9c000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1514 clock-names = "se"; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1517 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1518 power-domains = <&rpmhpd SC7280_CX>; 1519 operating-points-v2 = <&qup_opp_table>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1522 interconnect-names = "qup-core", "qup-config"; 1523 status = "disabled"; 1524 }; 1525 }; 1526 1527 cnoc2: interconnect@1500000 { 1528 reg = <0 0x01500000 0 0x1000>; 1529 compatible = "qcom,sc7280-cnoc2"; 1530 #interconnect-cells = <2>; 1531 qcom,bcm-voters = <&apps_bcm_voter>; 1532 }; 1533 1534 cnoc3: interconnect@1502000 { 1535 reg = <0 0x01502000 0 0x1000>; 1536 compatible = "qcom,sc7280-cnoc3"; 1537 #interconnect-cells = <2>; 1538 qcom,bcm-voters = <&apps_bcm_voter>; 1539 }; 1540 1541 mc_virt: interconnect@1580000 { 1542 reg = <0 0x01580000 0 0x4>; 1543 compatible = "qcom,sc7280-mc-virt"; 1544 #interconnect-cells = <2>; 1545 qcom,bcm-voters = <&apps_bcm_voter>; 1546 }; 1547 1548 system_noc: interconnect@1680000 { 1549 reg = <0 0x01680000 0 0x15480>; 1550 compatible = "qcom,sc7280-system-noc"; 1551 #interconnect-cells = <2>; 1552 qcom,bcm-voters = <&apps_bcm_voter>; 1553 }; 1554 1555 aggre1_noc: interconnect@16e0000 { 1556 compatible = "qcom,sc7280-aggre1-noc"; 1557 reg = <0 0x016e0000 0 0x1c080>; 1558 #interconnect-cells = <2>; 1559 qcom,bcm-voters = <&apps_bcm_voter>; 1560 }; 1561 1562 aggre2_noc: interconnect@1700000 { 1563 reg = <0 0x01700000 0 0x2b080>; 1564 compatible = "qcom,sc7280-aggre2-noc"; 1565 #interconnect-cells = <2>; 1566 qcom,bcm-voters = <&apps_bcm_voter>; 1567 }; 1568 1569 mmss_noc: interconnect@1740000 { 1570 reg = <0 0x01740000 0 0x1e080>; 1571 compatible = "qcom,sc7280-mmss-noc"; 1572 #interconnect-cells = <2>; 1573 qcom,bcm-voters = <&apps_bcm_voter>; 1574 }; 1575 1576 pcie1: pci@1c08000 { 1577 compatible = "qcom,pcie-sc7280"; 1578 reg = <0 0x01c08000 0 0x3000>, 1579 <0 0x40000000 0 0xf1d>, 1580 <0 0x40000f20 0 0xa8>, 1581 <0 0x40001000 0 0x1000>, 1582 <0 0x40100000 0 0x100000>; 1583 1584 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1585 device_type = "pci"; 1586 linux,pci-domain = <1>; 1587 bus-range = <0x00 0xff>; 1588 num-lanes = <2>; 1589 1590 #address-cells = <3>; 1591 #size-cells = <2>; 1592 1593 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1594 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1595 1596 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1597 interrupt-names = "msi"; 1598 #interrupt-cells = <1>; 1599 interrupt-map-mask = <0 0 0 0x7>; 1600 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, 1601 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, 1602 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, 1603 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; 1604 1605 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1606 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1607 <&pcie1_lane 0>, 1608 <&rpmhcc RPMH_CXO_CLK>, 1609 <&gcc GCC_PCIE_1_AUX_CLK>, 1610 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1611 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1612 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1613 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1614 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1615 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1616 1617 clock-names = "pipe", 1618 "pipe_mux", 1619 "phy_pipe", 1620 "ref", 1621 "aux", 1622 "cfg", 1623 "bus_master", 1624 "bus_slave", 1625 "slave_q2a", 1626 "tbu", 1627 "ddrss_sf_tbu"; 1628 1629 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1630 assigned-clock-rates = <19200000>; 1631 1632 resets = <&gcc GCC_PCIE_1_BCR>; 1633 reset-names = "pci"; 1634 1635 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1636 1637 phys = <&pcie1_lane>; 1638 phy-names = "pciephy"; 1639 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&pcie1_clkreq_n>; 1642 1643 iommus = <&apps_smmu 0x1c80 0x1>; 1644 1645 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1646 <0x100 &apps_smmu 0x1c81 0x1>; 1647 1648 status = "disabled"; 1649 }; 1650 1651 pcie1_phy: phy@1c0e000 { 1652 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1653 reg = <0 0x01c0e000 0 0x1c0>; 1654 #address-cells = <2>; 1655 #size-cells = <2>; 1656 ranges; 1657 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1658 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1659 <&gcc GCC_PCIE_CLKREF_EN>, 1660 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1661 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1662 1663 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1664 reset-names = "phy"; 1665 1666 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1667 assigned-clock-rates = <100000000>; 1668 1669 status = "disabled"; 1670 1671 pcie1_lane: lanes@1c0e200 { 1672 reg = <0 0x01c0e200 0 0x170>, 1673 <0 0x01c0e400 0 0x200>, 1674 <0 0x01c0ea00 0 0x1f0>, 1675 <0 0x01c0e600 0 0x170>, 1676 <0 0x01c0e800 0 0x200>, 1677 <0 0x01c0ee00 0 0xf4>; 1678 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1679 clock-names = "pipe0"; 1680 1681 #phy-cells = <0>; 1682 #clock-cells = <1>; 1683 clock-output-names = "pcie_1_pipe_clk"; 1684 }; 1685 }; 1686 1687 ipa: ipa@1e40000 { 1688 compatible = "qcom,sc7280-ipa"; 1689 1690 iommus = <&apps_smmu 0x480 0x0>, 1691 <&apps_smmu 0x482 0x0>; 1692 reg = <0 0x1e40000 0 0x8000>, 1693 <0 0x1e50000 0 0x4ad0>, 1694 <0 0x1e04000 0 0x23000>; 1695 reg-names = "ipa-reg", 1696 "ipa-shared", 1697 "gsi"; 1698 1699 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1700 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1701 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1702 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1703 interrupt-names = "ipa", 1704 "gsi", 1705 "ipa-clock-query", 1706 "ipa-setup-ready"; 1707 1708 clocks = <&rpmhcc RPMH_IPA_CLK>; 1709 clock-names = "core"; 1710 1711 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1712 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1713 interconnect-names = "memory", 1714 "config"; 1715 1716 qcom,smem-states = <&ipa_smp2p_out 0>, 1717 <&ipa_smp2p_out 1>; 1718 qcom,smem-state-names = "ipa-clock-enabled-valid", 1719 "ipa-clock-enabled"; 1720 1721 status = "disabled"; 1722 }; 1723 1724 tcsr_mutex: hwlock@1f40000 { 1725 compatible = "qcom,tcsr-mutex", "syscon"; 1726 reg = <0 0x01f40000 0 0x40000>; 1727 #hwlock-cells = <1>; 1728 }; 1729 1730 tcsr: syscon@1fc0000 { 1731 compatible = "qcom,sc7280-tcsr", "syscon"; 1732 reg = <0 0x01fc0000 0 0x30000>; 1733 }; 1734 1735 lpasscc: lpasscc@3000000 { 1736 compatible = "qcom,sc7280-lpasscc"; 1737 reg = <0 0x03000000 0 0x40>, 1738 <0 0x03c04000 0 0x4>, 1739 <0 0x03389000 0 0x24>; 1740 reg-names = "qdsp6ss", "top_cc", "cc"; 1741 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1742 clock-names = "iface"; 1743 #clock-cells = <1>; 1744 }; 1745 1746 lpass_ag_noc: interconnect@3c40000 { 1747 reg = <0 0x03c40000 0 0xf080>; 1748 compatible = "qcom,sc7280-lpass-ag-noc"; 1749 #interconnect-cells = <2>; 1750 qcom,bcm-voters = <&apps_bcm_voter>; 1751 }; 1752 1753 gpu: gpu@3d00000 { 1754 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1755 #stream-id-cells = <16>; 1756 reg = <0 0x03d00000 0 0x40000>, 1757 <0 0x03d9e000 0 0x1000>, 1758 <0 0x03d61000 0 0x800>; 1759 reg-names = "kgsl_3d0_reg_memory", 1760 "cx_mem", 1761 "cx_dbgc"; 1762 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1763 iommus = <&adreno_smmu 0 0x401>; 1764 operating-points-v2 = <&gpu_opp_table>; 1765 qcom,gmu = <&gmu>; 1766 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1767 interconnect-names = "gfx-mem"; 1768 #cooling-cells = <2>; 1769 1770 gpu_opp_table: opp-table { 1771 compatible = "operating-points-v2"; 1772 1773 opp-315000000 { 1774 opp-hz = /bits/ 64 <315000000>; 1775 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1776 opp-peak-kBps = <1804000>; 1777 }; 1778 1779 opp-450000000 { 1780 opp-hz = /bits/ 64 <450000000>; 1781 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1782 opp-peak-kBps = <4068000>; 1783 }; 1784 1785 opp-550000000 { 1786 opp-hz = /bits/ 64 <550000000>; 1787 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1788 opp-peak-kBps = <6832000>; 1789 }; 1790 }; 1791 }; 1792 1793 gmu: gmu@3d69000 { 1794 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1795 reg = <0 0x03d6a000 0 0x34000>, 1796 <0 0x3de0000 0 0x10000>, 1797 <0 0x0b290000 0 0x10000>; 1798 reg-names = "gmu", "rscc", "gmu_pdc"; 1799 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1801 interrupt-names = "hfi", "gmu"; 1802 clocks = <&gpucc 5>, 1803 <&gpucc 8>, 1804 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1805 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1806 <&gpucc 2>, 1807 <&gpucc 15>, 1808 <&gpucc 11>; 1809 clock-names = "gmu", 1810 "cxo", 1811 "axi", 1812 "memnoc", 1813 "ahb", 1814 "hub", 1815 "smmu_vote"; 1816 power-domains = <&gpucc 0>, 1817 <&gpucc 1>; 1818 power-domain-names = "cx", 1819 "gx"; 1820 iommus = <&adreno_smmu 5 0x400>; 1821 operating-points-v2 = <&gmu_opp_table>; 1822 1823 gmu_opp_table: opp-table { 1824 compatible = "operating-points-v2"; 1825 1826 opp-200000000 { 1827 opp-hz = /bits/ 64 <200000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1829 }; 1830 }; 1831 }; 1832 1833 gpucc: clock-controller@3d90000 { 1834 compatible = "qcom,sc7280-gpucc"; 1835 reg = <0 0x03d90000 0 0x9000>; 1836 clocks = <&rpmhcc RPMH_CXO_CLK>, 1837 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1838 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1839 clock-names = "bi_tcxo", 1840 "gcc_gpu_gpll0_clk_src", 1841 "gcc_gpu_gpll0_div_clk_src"; 1842 #clock-cells = <1>; 1843 #reset-cells = <1>; 1844 #power-domain-cells = <1>; 1845 }; 1846 1847 adreno_smmu: iommu@3da0000 { 1848 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1849 reg = <0 0x03da0000 0 0x20000>; 1850 #iommu-cells = <2>; 1851 #global-interrupts = <2>; 1852 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1864 1865 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1866 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1867 <&gpucc 2>, 1868 <&gpucc 11>, 1869 <&gpucc 5>, 1870 <&gpucc 15>, 1871 <&gpucc 13>; 1872 clock-names = "gcc_gpu_memnoc_gfx_clk", 1873 "gcc_gpu_snoc_dvm_gfx_clk", 1874 "gpu_cc_ahb_clk", 1875 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1876 "gpu_cc_cx_gmu_clk", 1877 "gpu_cc_hub_cx_int_clk", 1878 "gpu_cc_hub_aon_clk"; 1879 1880 power-domains = <&gpucc 0>; 1881 }; 1882 1883 remoteproc_mpss: remoteproc@4080000 { 1884 compatible = "qcom,sc7280-mpss-pas"; 1885 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1886 reg-names = "qdsp6", "rmb"; 1887 1888 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1889 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1890 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1891 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1892 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1893 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1894 interrupt-names = "wdog", "fatal", "ready", "handover", 1895 "stop-ack", "shutdown-ack"; 1896 1897 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1898 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1899 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1900 <&rpmhcc RPMH_PKA_CLK>, 1901 <&rpmhcc RPMH_CXO_CLK>; 1902 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1903 1904 power-domains = <&rpmhpd SC7280_CX>, 1905 <&rpmhpd SC7280_MSS>; 1906 power-domain-names = "cx", "mss"; 1907 1908 memory-region = <&mpss_mem>; 1909 1910 qcom,qmp = <&aoss_qmp>; 1911 1912 qcom,smem-states = <&modem_smp2p_out 0>; 1913 qcom,smem-state-names = "stop"; 1914 1915 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1916 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1917 reset-names = "mss_restart", "pdc_reset"; 1918 1919 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1920 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1921 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1922 1923 status = "disabled"; 1924 1925 glink-edge { 1926 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1927 IPCC_MPROC_SIGNAL_GLINK_QMP 1928 IRQ_TYPE_EDGE_RISING>; 1929 mboxes = <&ipcc IPCC_CLIENT_MPSS 1930 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1931 label = "modem"; 1932 qcom,remote-pid = <1>; 1933 }; 1934 }; 1935 1936 stm@6002000 { 1937 compatible = "arm,coresight-stm", "arm,primecell"; 1938 reg = <0 0x06002000 0 0x1000>, 1939 <0 0x16280000 0 0x180000>; 1940 reg-names = "stm-base", "stm-stimulus-base"; 1941 1942 clocks = <&aoss_qmp>; 1943 clock-names = "apb_pclk"; 1944 1945 out-ports { 1946 port { 1947 stm_out: endpoint { 1948 remote-endpoint = <&funnel0_in7>; 1949 }; 1950 }; 1951 }; 1952 }; 1953 1954 funnel@6041000 { 1955 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1956 reg = <0 0x06041000 0 0x1000>; 1957 1958 clocks = <&aoss_qmp>; 1959 clock-names = "apb_pclk"; 1960 1961 out-ports { 1962 port { 1963 funnel0_out: endpoint { 1964 remote-endpoint = <&merge_funnel_in0>; 1965 }; 1966 }; 1967 }; 1968 1969 in-ports { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 port@7 { 1974 reg = <7>; 1975 funnel0_in7: endpoint { 1976 remote-endpoint = <&stm_out>; 1977 }; 1978 }; 1979 }; 1980 }; 1981 1982 funnel@6042000 { 1983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1984 reg = <0 0x06042000 0 0x1000>; 1985 1986 clocks = <&aoss_qmp>; 1987 clock-names = "apb_pclk"; 1988 1989 out-ports { 1990 port { 1991 funnel1_out: endpoint { 1992 remote-endpoint = <&merge_funnel_in1>; 1993 }; 1994 }; 1995 }; 1996 1997 in-ports { 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 port@4 { 2002 reg = <4>; 2003 funnel1_in4: endpoint { 2004 remote-endpoint = <&apss_merge_funnel_out>; 2005 }; 2006 }; 2007 }; 2008 }; 2009 2010 funnel@6045000 { 2011 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2012 reg = <0 0x06045000 0 0x1000>; 2013 2014 clocks = <&aoss_qmp>; 2015 clock-names = "apb_pclk"; 2016 2017 out-ports { 2018 port { 2019 merge_funnel_out: endpoint { 2020 remote-endpoint = <&swao_funnel_in>; 2021 }; 2022 }; 2023 }; 2024 2025 in-ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 2029 port@0 { 2030 reg = <0>; 2031 merge_funnel_in0: endpoint { 2032 remote-endpoint = <&funnel0_out>; 2033 }; 2034 }; 2035 2036 port@1 { 2037 reg = <1>; 2038 merge_funnel_in1: endpoint { 2039 remote-endpoint = <&funnel1_out>; 2040 }; 2041 }; 2042 }; 2043 }; 2044 2045 replicator@6046000 { 2046 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2047 reg = <0 0x06046000 0 0x1000>; 2048 2049 clocks = <&aoss_qmp>; 2050 clock-names = "apb_pclk"; 2051 2052 out-ports { 2053 port { 2054 replicator_out: endpoint { 2055 remote-endpoint = <&etr_in>; 2056 }; 2057 }; 2058 }; 2059 2060 in-ports { 2061 port { 2062 replicator_in: endpoint { 2063 remote-endpoint = <&swao_replicator_out>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 etr@6048000 { 2070 compatible = "arm,coresight-tmc", "arm,primecell"; 2071 reg = <0 0x06048000 0 0x1000>; 2072 iommus = <&apps_smmu 0x04c0 0>; 2073 2074 clocks = <&aoss_qmp>; 2075 clock-names = "apb_pclk"; 2076 arm,scatter-gather; 2077 2078 in-ports { 2079 port { 2080 etr_in: endpoint { 2081 remote-endpoint = <&replicator_out>; 2082 }; 2083 }; 2084 }; 2085 }; 2086 2087 funnel@6b04000 { 2088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2089 reg = <0 0x06b04000 0 0x1000>; 2090 2091 clocks = <&aoss_qmp>; 2092 clock-names = "apb_pclk"; 2093 2094 out-ports { 2095 port { 2096 swao_funnel_out: endpoint { 2097 remote-endpoint = <&etf_in>; 2098 }; 2099 }; 2100 }; 2101 2102 in-ports { 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 port@7 { 2107 reg = <7>; 2108 swao_funnel_in: endpoint { 2109 remote-endpoint = <&merge_funnel_out>; 2110 }; 2111 }; 2112 }; 2113 }; 2114 2115 etf@6b05000 { 2116 compatible = "arm,coresight-tmc", "arm,primecell"; 2117 reg = <0 0x06b05000 0 0x1000>; 2118 2119 clocks = <&aoss_qmp>; 2120 clock-names = "apb_pclk"; 2121 2122 out-ports { 2123 port { 2124 etf_out: endpoint { 2125 remote-endpoint = <&swao_replicator_in>; 2126 }; 2127 }; 2128 }; 2129 2130 in-ports { 2131 port { 2132 etf_in: endpoint { 2133 remote-endpoint = <&swao_funnel_out>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 replicator@6b06000 { 2140 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2141 reg = <0 0x06b06000 0 0x1000>; 2142 2143 clocks = <&aoss_qmp>; 2144 clock-names = "apb_pclk"; 2145 qcom,replicator-loses-context; 2146 2147 out-ports { 2148 port { 2149 swao_replicator_out: endpoint { 2150 remote-endpoint = <&replicator_in>; 2151 }; 2152 }; 2153 }; 2154 2155 in-ports { 2156 port { 2157 swao_replicator_in: endpoint { 2158 remote-endpoint = <&etf_out>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 etm@7040000 { 2165 compatible = "arm,coresight-etm4x", "arm,primecell"; 2166 reg = <0 0x07040000 0 0x1000>; 2167 2168 cpu = <&CPU0>; 2169 2170 clocks = <&aoss_qmp>; 2171 clock-names = "apb_pclk"; 2172 arm,coresight-loses-context-with-cpu; 2173 qcom,skip-power-up; 2174 2175 out-ports { 2176 port { 2177 etm0_out: endpoint { 2178 remote-endpoint = <&apss_funnel_in0>; 2179 }; 2180 }; 2181 }; 2182 }; 2183 2184 etm@7140000 { 2185 compatible = "arm,coresight-etm4x", "arm,primecell"; 2186 reg = <0 0x07140000 0 0x1000>; 2187 2188 cpu = <&CPU1>; 2189 2190 clocks = <&aoss_qmp>; 2191 clock-names = "apb_pclk"; 2192 arm,coresight-loses-context-with-cpu; 2193 qcom,skip-power-up; 2194 2195 out-ports { 2196 port { 2197 etm1_out: endpoint { 2198 remote-endpoint = <&apss_funnel_in1>; 2199 }; 2200 }; 2201 }; 2202 }; 2203 2204 etm@7240000 { 2205 compatible = "arm,coresight-etm4x", "arm,primecell"; 2206 reg = <0 0x07240000 0 0x1000>; 2207 2208 cpu = <&CPU2>; 2209 2210 clocks = <&aoss_qmp>; 2211 clock-names = "apb_pclk"; 2212 arm,coresight-loses-context-with-cpu; 2213 qcom,skip-power-up; 2214 2215 out-ports { 2216 port { 2217 etm2_out: endpoint { 2218 remote-endpoint = <&apss_funnel_in2>; 2219 }; 2220 }; 2221 }; 2222 }; 2223 2224 etm@7340000 { 2225 compatible = "arm,coresight-etm4x", "arm,primecell"; 2226 reg = <0 0x07340000 0 0x1000>; 2227 2228 cpu = <&CPU3>; 2229 2230 clocks = <&aoss_qmp>; 2231 clock-names = "apb_pclk"; 2232 arm,coresight-loses-context-with-cpu; 2233 qcom,skip-power-up; 2234 2235 out-ports { 2236 port { 2237 etm3_out: endpoint { 2238 remote-endpoint = <&apss_funnel_in3>; 2239 }; 2240 }; 2241 }; 2242 }; 2243 2244 etm@7440000 { 2245 compatible = "arm,coresight-etm4x", "arm,primecell"; 2246 reg = <0 0x07440000 0 0x1000>; 2247 2248 cpu = <&CPU4>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 arm,coresight-loses-context-with-cpu; 2253 qcom,skip-power-up; 2254 2255 out-ports { 2256 port { 2257 etm4_out: endpoint { 2258 remote-endpoint = <&apss_funnel_in4>; 2259 }; 2260 }; 2261 }; 2262 }; 2263 2264 etm@7540000 { 2265 compatible = "arm,coresight-etm4x", "arm,primecell"; 2266 reg = <0 0x07540000 0 0x1000>; 2267 2268 cpu = <&CPU5>; 2269 2270 clocks = <&aoss_qmp>; 2271 clock-names = "apb_pclk"; 2272 arm,coresight-loses-context-with-cpu; 2273 qcom,skip-power-up; 2274 2275 out-ports { 2276 port { 2277 etm5_out: endpoint { 2278 remote-endpoint = <&apss_funnel_in5>; 2279 }; 2280 }; 2281 }; 2282 }; 2283 2284 etm@7640000 { 2285 compatible = "arm,coresight-etm4x", "arm,primecell"; 2286 reg = <0 0x07640000 0 0x1000>; 2287 2288 cpu = <&CPU6>; 2289 2290 clocks = <&aoss_qmp>; 2291 clock-names = "apb_pclk"; 2292 arm,coresight-loses-context-with-cpu; 2293 qcom,skip-power-up; 2294 2295 out-ports { 2296 port { 2297 etm6_out: endpoint { 2298 remote-endpoint = <&apss_funnel_in6>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 etm@7740000 { 2305 compatible = "arm,coresight-etm4x", "arm,primecell"; 2306 reg = <0 0x07740000 0 0x1000>; 2307 2308 cpu = <&CPU7>; 2309 2310 clocks = <&aoss_qmp>; 2311 clock-names = "apb_pclk"; 2312 arm,coresight-loses-context-with-cpu; 2313 qcom,skip-power-up; 2314 2315 out-ports { 2316 port { 2317 etm7_out: endpoint { 2318 remote-endpoint = <&apss_funnel_in7>; 2319 }; 2320 }; 2321 }; 2322 }; 2323 2324 funnel@7800000 { /* APSS Funnel */ 2325 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2326 reg = <0 0x07800000 0 0x1000>; 2327 2328 clocks = <&aoss_qmp>; 2329 clock-names = "apb_pclk"; 2330 2331 out-ports { 2332 port { 2333 apss_funnel_out: endpoint { 2334 remote-endpoint = <&apss_merge_funnel_in>; 2335 }; 2336 }; 2337 }; 2338 2339 in-ports { 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 2343 port@0 { 2344 reg = <0>; 2345 apss_funnel_in0: endpoint { 2346 remote-endpoint = <&etm0_out>; 2347 }; 2348 }; 2349 2350 port@1 { 2351 reg = <1>; 2352 apss_funnel_in1: endpoint { 2353 remote-endpoint = <&etm1_out>; 2354 }; 2355 }; 2356 2357 port@2 { 2358 reg = <2>; 2359 apss_funnel_in2: endpoint { 2360 remote-endpoint = <&etm2_out>; 2361 }; 2362 }; 2363 2364 port@3 { 2365 reg = <3>; 2366 apss_funnel_in3: endpoint { 2367 remote-endpoint = <&etm3_out>; 2368 }; 2369 }; 2370 2371 port@4 { 2372 reg = <4>; 2373 apss_funnel_in4: endpoint { 2374 remote-endpoint = <&etm4_out>; 2375 }; 2376 }; 2377 2378 port@5 { 2379 reg = <5>; 2380 apss_funnel_in5: endpoint { 2381 remote-endpoint = <&etm5_out>; 2382 }; 2383 }; 2384 2385 port@6 { 2386 reg = <6>; 2387 apss_funnel_in6: endpoint { 2388 remote-endpoint = <&etm6_out>; 2389 }; 2390 }; 2391 2392 port@7 { 2393 reg = <7>; 2394 apss_funnel_in7: endpoint { 2395 remote-endpoint = <&etm7_out>; 2396 }; 2397 }; 2398 }; 2399 }; 2400 2401 funnel@7810000 { 2402 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2403 reg = <0 0x07810000 0 0x1000>; 2404 2405 clocks = <&aoss_qmp>; 2406 clock-names = "apb_pclk"; 2407 2408 out-ports { 2409 port { 2410 apss_merge_funnel_out: endpoint { 2411 remote-endpoint = <&funnel1_in4>; 2412 }; 2413 }; 2414 }; 2415 2416 in-ports { 2417 port { 2418 apss_merge_funnel_in: endpoint { 2419 remote-endpoint = <&apss_funnel_out>; 2420 }; 2421 }; 2422 }; 2423 }; 2424 2425 sdhc_2: sdhci@8804000 { 2426 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2427 status = "disabled"; 2428 2429 reg = <0 0x08804000 0 0x1000>; 2430 2431 iommus = <&apps_smmu 0x100 0x0>; 2432 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2434 interrupt-names = "hc_irq", "pwr_irq"; 2435 2436 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2437 <&gcc GCC_SDCC2_AHB_CLK>, 2438 <&rpmhcc RPMH_CXO_CLK>; 2439 clock-names = "core", "iface", "xo"; 2440 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2442 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2443 power-domains = <&rpmhpd SC7280_CX>; 2444 operating-points-v2 = <&sdhc2_opp_table>; 2445 2446 bus-width = <4>; 2447 2448 qcom,dll-config = <0x0007642c>; 2449 2450 sdhc2_opp_table: opp-table { 2451 compatible = "operating-points-v2"; 2452 2453 opp-100000000 { 2454 opp-hz = /bits/ 64 <100000000>; 2455 required-opps = <&rpmhpd_opp_low_svs>; 2456 opp-peak-kBps = <1800000 400000>; 2457 opp-avg-kBps = <100000 0>; 2458 }; 2459 2460 opp-202000000 { 2461 opp-hz = /bits/ 64 <202000000>; 2462 required-opps = <&rpmhpd_opp_nom>; 2463 opp-peak-kBps = <5400000 1600000>; 2464 opp-avg-kBps = <200000 0>; 2465 }; 2466 }; 2467 2468 }; 2469 2470 usb_1_hsphy: phy@88e3000 { 2471 compatible = "qcom,sc7280-usb-hs-phy", 2472 "qcom,usb-snps-hs-7nm-phy"; 2473 reg = <0 0x088e3000 0 0x400>; 2474 status = "disabled"; 2475 #phy-cells = <0>; 2476 2477 clocks = <&rpmhcc RPMH_CXO_CLK>; 2478 clock-names = "ref"; 2479 2480 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2481 }; 2482 2483 usb_2_hsphy: phy@88e4000 { 2484 compatible = "qcom,sc7280-usb-hs-phy", 2485 "qcom,usb-snps-hs-7nm-phy"; 2486 reg = <0 0x088e4000 0 0x400>; 2487 status = "disabled"; 2488 #phy-cells = <0>; 2489 2490 clocks = <&rpmhcc RPMH_CXO_CLK>; 2491 clock-names = "ref"; 2492 2493 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2494 }; 2495 2496 usb_1_qmpphy: phy-wrapper@88e9000 { 2497 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2498 "qcom,sm8250-qmp-usb3-dp-phy"; 2499 reg = <0 0x088e9000 0 0x200>, 2500 <0 0x088e8000 0 0x40>, 2501 <0 0x088ea000 0 0x200>; 2502 status = "disabled"; 2503 #address-cells = <2>; 2504 #size-cells = <2>; 2505 ranges; 2506 2507 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2508 <&rpmhcc RPMH_CXO_CLK>, 2509 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2510 clock-names = "aux", "ref_clk_src", "com_aux"; 2511 2512 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2513 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2514 reset-names = "phy", "common"; 2515 2516 usb_1_ssphy: usb3-phy@88e9200 { 2517 reg = <0 0x088e9200 0 0x200>, 2518 <0 0x088e9400 0 0x200>, 2519 <0 0x088e9c00 0 0x400>, 2520 <0 0x088e9600 0 0x200>, 2521 <0 0x088e9800 0 0x200>, 2522 <0 0x088e9a00 0 0x100>; 2523 #clock-cells = <0>; 2524 #phy-cells = <0>; 2525 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2526 clock-names = "pipe0"; 2527 clock-output-names = "usb3_phy_pipe_clk_src"; 2528 }; 2529 2530 dp_phy: dp-phy@88ea200 { 2531 reg = <0 0x088ea200 0 0x200>, 2532 <0 0x088ea400 0 0x200>, 2533 <0 0x088eaa00 0 0x200>, 2534 <0 0x088ea600 0 0x200>, 2535 <0 0x088ea800 0 0x200>; 2536 #phy-cells = <0>; 2537 #clock-cells = <1>; 2538 }; 2539 }; 2540 2541 usb_2: usb@8cf8800 { 2542 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2543 reg = <0 0x08cf8800 0 0x400>; 2544 status = "disabled"; 2545 #address-cells = <2>; 2546 #size-cells = <2>; 2547 ranges; 2548 dma-ranges; 2549 2550 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2551 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2552 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2553 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2554 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2555 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2556 "sleep"; 2557 2558 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2559 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2560 assigned-clock-rates = <19200000>, <200000000>; 2561 2562 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2563 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2564 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2565 interrupt-names = "hs_phy_irq", 2566 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2567 2568 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2569 2570 resets = <&gcc GCC_USB30_SEC_BCR>; 2571 2572 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2574 interconnect-names = "usb-ddr", "apps-usb"; 2575 2576 usb_2_dwc3: usb@8c00000 { 2577 compatible = "snps,dwc3"; 2578 reg = <0 0x08c00000 0 0xe000>; 2579 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2580 iommus = <&apps_smmu 0xa0 0x0>; 2581 snps,dis_u2_susphy_quirk; 2582 snps,dis_enblslpm_quirk; 2583 phys = <&usb_2_hsphy>; 2584 phy-names = "usb2-phy"; 2585 maximum-speed = "high-speed"; 2586 }; 2587 }; 2588 2589 qspi: spi@88dc000 { 2590 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2591 reg = <0 0x088dc000 0 0x1000>; 2592 #address-cells = <1>; 2593 #size-cells = <0>; 2594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2596 <&gcc GCC_QSPI_CORE_CLK>; 2597 clock-names = "iface", "core"; 2598 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2599 &cnoc2 SLAVE_QSPI_0 0>; 2600 interconnect-names = "qspi-config"; 2601 power-domains = <&rpmhpd SC7280_CX>; 2602 operating-points-v2 = <&qspi_opp_table>; 2603 status = "disabled"; 2604 }; 2605 2606 dc_noc: interconnect@90e0000 { 2607 reg = <0 0x090e0000 0 0x5080>; 2608 compatible = "qcom,sc7280-dc-noc"; 2609 #interconnect-cells = <2>; 2610 qcom,bcm-voters = <&apps_bcm_voter>; 2611 }; 2612 2613 gem_noc: interconnect@9100000 { 2614 reg = <0 0x9100000 0 0xe2200>; 2615 compatible = "qcom,sc7280-gem-noc"; 2616 #interconnect-cells = <2>; 2617 qcom,bcm-voters = <&apps_bcm_voter>; 2618 }; 2619 2620 system-cache-controller@9200000 { 2621 compatible = "qcom,sc7280-llcc"; 2622 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2623 reg-names = "llcc_base", "llcc_broadcast_base"; 2624 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2625 }; 2626 2627 nsp_noc: interconnect@a0c0000 { 2628 reg = <0 0x0a0c0000 0 0x10000>; 2629 compatible = "qcom,sc7280-nsp-noc"; 2630 #interconnect-cells = <2>; 2631 qcom,bcm-voters = <&apps_bcm_voter>; 2632 }; 2633 2634 usb_1: usb@a6f8800 { 2635 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2636 reg = <0 0x0a6f8800 0 0x400>; 2637 status = "disabled"; 2638 #address-cells = <2>; 2639 #size-cells = <2>; 2640 ranges; 2641 dma-ranges; 2642 2643 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2644 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2645 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2646 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2647 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2648 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2649 "sleep"; 2650 2651 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2652 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2653 assigned-clock-rates = <19200000>, <200000000>; 2654 2655 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2656 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2657 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2658 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2659 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2660 "dm_hs_phy_irq", "ss_phy_irq"; 2661 2662 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2663 2664 resets = <&gcc GCC_USB30_PRIM_BCR>; 2665 2666 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2667 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2668 interconnect-names = "usb-ddr", "apps-usb"; 2669 2670 usb_1_dwc3: usb@a600000 { 2671 compatible = "snps,dwc3"; 2672 reg = <0 0x0a600000 0 0xe000>; 2673 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2674 iommus = <&apps_smmu 0xe0 0x0>; 2675 snps,dis_u2_susphy_quirk; 2676 snps,dis_enblslpm_quirk; 2677 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2678 phy-names = "usb2-phy", "usb3-phy"; 2679 maximum-speed = "super-speed"; 2680 }; 2681 }; 2682 2683 venus: video-codec@aa00000 { 2684 compatible = "qcom,sc7280-venus"; 2685 reg = <0 0x0aa00000 0 0xd0600>; 2686 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2689 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2690 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2691 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2692 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2693 clock-names = "core", "bus", "iface", 2694 "vcodec_core", "vcodec_bus"; 2695 2696 power-domains = <&videocc MVSC_GDSC>, 2697 <&videocc MVS0_GDSC>, 2698 <&rpmhpd SC7280_CX>; 2699 power-domain-names = "venus", "vcodec0", "cx"; 2700 operating-points-v2 = <&venus_opp_table>; 2701 2702 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2703 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2704 interconnect-names = "cpu-cfg", "video-mem"; 2705 2706 iommus = <&apps_smmu 0x2180 0x20>, 2707 <&apps_smmu 0x2184 0x20>; 2708 memory-region = <&video_mem>; 2709 2710 video-decoder { 2711 compatible = "venus-decoder"; 2712 }; 2713 2714 video-encoder { 2715 compatible = "venus-encoder"; 2716 }; 2717 2718 video-firmware { 2719 iommus = <&apps_smmu 0x21a2 0x0>; 2720 }; 2721 2722 venus_opp_table: venus-opp-table { 2723 compatible = "operating-points-v2"; 2724 2725 opp-133330000 { 2726 opp-hz = /bits/ 64 <133330000>; 2727 required-opps = <&rpmhpd_opp_low_svs>; 2728 }; 2729 2730 opp-240000000 { 2731 opp-hz = /bits/ 64 <240000000>; 2732 required-opps = <&rpmhpd_opp_svs>; 2733 }; 2734 2735 opp-335000000 { 2736 opp-hz = /bits/ 64 <335000000>; 2737 required-opps = <&rpmhpd_opp_svs_l1>; 2738 }; 2739 2740 opp-424000000 { 2741 opp-hz = /bits/ 64 <424000000>; 2742 required-opps = <&rpmhpd_opp_nom>; 2743 }; 2744 2745 opp-460000048 { 2746 opp-hz = /bits/ 64 <460000048>; 2747 required-opps = <&rpmhpd_opp_turbo>; 2748 }; 2749 }; 2750 2751 }; 2752 2753 videocc: clock-controller@aaf0000 { 2754 compatible = "qcom,sc7280-videocc"; 2755 reg = <0 0xaaf0000 0 0x10000>; 2756 clocks = <&rpmhcc RPMH_CXO_CLK>, 2757 <&rpmhcc RPMH_CXO_CLK_A>; 2758 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2759 #clock-cells = <1>; 2760 #reset-cells = <1>; 2761 #power-domain-cells = <1>; 2762 }; 2763 2764 dispcc: clock-controller@af00000 { 2765 compatible = "qcom,sc7280-dispcc"; 2766 reg = <0 0xaf00000 0 0x20000>; 2767 clocks = <&rpmhcc RPMH_CXO_CLK>, 2768 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2769 <0>, <0>, <0>, <0>, <0>, <0>; 2770 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2771 "dsi0_phy_pll_out_byteclk", 2772 "dsi0_phy_pll_out_dsiclk", 2773 "dp_phy_pll_link_clk", 2774 "dp_phy_pll_vco_div_clk", 2775 "edp_phy_pll_link_clk", 2776 "edp_phy_pll_vco_div_clk"; 2777 #clock-cells = <1>; 2778 #reset-cells = <1>; 2779 #power-domain-cells = <1>; 2780 }; 2781 2782 pdc: interrupt-controller@b220000 { 2783 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2784 reg = <0 0x0b220000 0 0x30000>; 2785 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2786 <55 306 4>, <59 312 3>, <62 374 2>, 2787 <64 434 2>, <66 438 3>, <69 86 1>, 2788 <70 520 54>, <124 609 31>, <155 63 1>, 2789 <156 716 12>; 2790 #interrupt-cells = <2>; 2791 interrupt-parent = <&intc>; 2792 interrupt-controller; 2793 }; 2794 2795 pdc_reset: reset-controller@b5e0000 { 2796 compatible = "qcom,sc7280-pdc-global"; 2797 reg = <0 0x0b5e0000 0 0x20000>; 2798 #reset-cells = <1>; 2799 }; 2800 2801 tsens0: thermal-sensor@c263000 { 2802 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2803 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2804 <0 0x0c222000 0 0x1ff>; /* SROT */ 2805 #qcom,sensors = <15>; 2806 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2808 interrupt-names = "uplow","critical"; 2809 #thermal-sensor-cells = <1>; 2810 }; 2811 2812 tsens1: thermal-sensor@c265000 { 2813 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2814 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2815 <0 0x0c223000 0 0x1ff>; /* SROT */ 2816 #qcom,sensors = <12>; 2817 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2819 interrupt-names = "uplow","critical"; 2820 #thermal-sensor-cells = <1>; 2821 }; 2822 2823 aoss_reset: reset-controller@c2a0000 { 2824 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2825 reg = <0 0x0c2a0000 0 0x31000>; 2826 #reset-cells = <1>; 2827 }; 2828 2829 aoss_qmp: power-controller@c300000 { 2830 compatible = "qcom,sc7280-aoss-qmp"; 2831 reg = <0 0x0c300000 0 0x400>; 2832 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2833 IPCC_MPROC_SIGNAL_GLINK_QMP 2834 IRQ_TYPE_EDGE_RISING>; 2835 mboxes = <&ipcc IPCC_CLIENT_AOP 2836 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2837 2838 #clock-cells = <0>; 2839 }; 2840 2841 sram@c3f0000 { 2842 compatible = "qcom,rpmh-stats"; 2843 reg = <0 0x0c3f0000 0 0x400>; 2844 }; 2845 2846 spmi_bus: spmi@c440000 { 2847 compatible = "qcom,spmi-pmic-arb"; 2848 reg = <0 0x0c440000 0 0x1100>, 2849 <0 0x0c600000 0 0x2000000>, 2850 <0 0x0e600000 0 0x100000>, 2851 <0 0x0e700000 0 0xa0000>, 2852 <0 0x0c40a000 0 0x26000>; 2853 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2854 interrupt-names = "periph_irq"; 2855 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2856 qcom,ee = <0>; 2857 qcom,channel = <0>; 2858 #address-cells = <1>; 2859 #size-cells = <1>; 2860 interrupt-controller; 2861 #interrupt-cells = <4>; 2862 }; 2863 2864 tlmm: pinctrl@f100000 { 2865 compatible = "qcom,sc7280-pinctrl"; 2866 reg = <0 0x0f100000 0 0x300000>; 2867 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2868 gpio-controller; 2869 #gpio-cells = <2>; 2870 interrupt-controller; 2871 #interrupt-cells = <2>; 2872 gpio-ranges = <&tlmm 0 0 175>; 2873 wakeup-parent = <&pdc>; 2874 2875 pcie1_clkreq_n: pcie1-clkreq-n { 2876 pins = "gpio79"; 2877 function = "pcie1_clkreqn"; 2878 drive-strength = <2>; 2879 bias-pull-up; 2880 }; 2881 2882 qspi_clk: qspi-clk { 2883 pins = "gpio14"; 2884 function = "qspi_clk"; 2885 }; 2886 2887 qspi_cs0: qspi-cs0 { 2888 pins = "gpio15"; 2889 function = "qspi_cs"; 2890 }; 2891 2892 qspi_cs1: qspi-cs1 { 2893 pins = "gpio19"; 2894 function = "qspi_cs"; 2895 }; 2896 2897 qspi_data01: qspi-data01 { 2898 pins = "gpio12", "gpio13"; 2899 function = "qspi_data"; 2900 }; 2901 2902 qspi_data12: qspi-data12 { 2903 pins = "gpio16", "gpio17"; 2904 function = "qspi_data"; 2905 }; 2906 2907 qup_i2c0_data_clk: qup-i2c0-data-clk { 2908 pins = "gpio0", "gpio1"; 2909 function = "qup00"; 2910 }; 2911 2912 qup_i2c1_data_clk: qup-i2c1-data-clk { 2913 pins = "gpio4", "gpio5"; 2914 function = "qup01"; 2915 }; 2916 2917 qup_i2c2_data_clk: qup-i2c2-data-clk { 2918 pins = "gpio8", "gpio9"; 2919 function = "qup02"; 2920 }; 2921 2922 qup_i2c3_data_clk: qup-i2c3-data-clk { 2923 pins = "gpio12", "gpio13"; 2924 function = "qup03"; 2925 }; 2926 2927 qup_i2c4_data_clk: qup-i2c4-data-clk { 2928 pins = "gpio16", "gpio17"; 2929 function = "qup04"; 2930 }; 2931 2932 qup_i2c5_data_clk: qup-i2c5-data-clk { 2933 pins = "gpio20", "gpio21"; 2934 function = "qup05"; 2935 }; 2936 2937 qup_i2c6_data_clk: qup-i2c6-data-clk { 2938 pins = "gpio24", "gpio25"; 2939 function = "qup06"; 2940 }; 2941 2942 qup_i2c7_data_clk: qup-i2c7-data-clk { 2943 pins = "gpio28", "gpio29"; 2944 function = "qup07"; 2945 }; 2946 2947 qup_i2c8_data_clk: qup-i2c8-data-clk { 2948 pins = "gpio32", "gpio33"; 2949 function = "qup10"; 2950 }; 2951 2952 qup_i2c9_data_clk: qup-i2c9-data-clk { 2953 pins = "gpio36", "gpio37"; 2954 function = "qup11"; 2955 }; 2956 2957 qup_i2c10_data_clk: qup-i2c10-data-clk { 2958 pins = "gpio40", "gpio41"; 2959 function = "qup12"; 2960 }; 2961 2962 qup_i2c11_data_clk: qup-i2c11-data-clk { 2963 pins = "gpio44", "gpio45"; 2964 function = "qup13"; 2965 }; 2966 2967 qup_i2c12_data_clk: qup-i2c12-data-clk { 2968 pins = "gpio48", "gpio49"; 2969 function = "qup14"; 2970 }; 2971 2972 qup_i2c13_data_clk: qup-i2c13-data-clk { 2973 pins = "gpio52", "gpio53"; 2974 function = "qup15"; 2975 }; 2976 2977 qup_i2c14_data_clk: qup-i2c14-data-clk { 2978 pins = "gpio56", "gpio57"; 2979 function = "qup16"; 2980 }; 2981 2982 qup_i2c15_data_clk: qup-i2c15-data-clk { 2983 pins = "gpio60", "gpio61"; 2984 function = "qup17"; 2985 }; 2986 2987 qup_spi0_data_clk: qup-spi0-data-clk { 2988 pins = "gpio0", "gpio1", "gpio2"; 2989 function = "qup00"; 2990 }; 2991 2992 qup_spi0_cs: qup-spi0-cs { 2993 pins = "gpio3"; 2994 function = "qup00"; 2995 }; 2996 2997 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2998 pins = "gpio3"; 2999 function = "gpio"; 3000 }; 3001 3002 qup_spi1_data_clk: qup-spi1-data-clk { 3003 pins = "gpio4", "gpio5", "gpio6"; 3004 function = "qup01"; 3005 }; 3006 3007 qup_spi1_cs: qup-spi1-cs { 3008 pins = "gpio7"; 3009 function = "qup01"; 3010 }; 3011 3012 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3013 pins = "gpio7"; 3014 function = "gpio"; 3015 }; 3016 3017 qup_spi2_data_clk: qup-spi2-data-clk { 3018 pins = "gpio8", "gpio9", "gpio10"; 3019 function = "qup02"; 3020 }; 3021 3022 qup_spi2_cs: qup-spi2-cs { 3023 pins = "gpio11"; 3024 function = "qup02"; 3025 }; 3026 3027 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3028 pins = "gpio11"; 3029 function = "gpio"; 3030 }; 3031 3032 qup_spi3_data_clk: qup-spi3-data-clk { 3033 pins = "gpio12", "gpio13", "gpio14"; 3034 function = "qup03"; 3035 }; 3036 3037 qup_spi3_cs: qup-spi3-cs { 3038 pins = "gpio15"; 3039 function = "qup03"; 3040 }; 3041 3042 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3043 pins = "gpio15"; 3044 function = "gpio"; 3045 }; 3046 3047 qup_spi4_data_clk: qup-spi4-data-clk { 3048 pins = "gpio16", "gpio17", "gpio18"; 3049 function = "qup04"; 3050 }; 3051 3052 qup_spi4_cs: qup-spi4-cs { 3053 pins = "gpio19"; 3054 function = "qup04"; 3055 }; 3056 3057 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3058 pins = "gpio19"; 3059 function = "gpio"; 3060 }; 3061 3062 qup_spi5_data_clk: qup-spi5-data-clk { 3063 pins = "gpio20", "gpio21", "gpio22"; 3064 function = "qup05"; 3065 }; 3066 3067 qup_spi5_cs: qup-spi5-cs { 3068 pins = "gpio23"; 3069 function = "qup05"; 3070 }; 3071 3072 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3073 pins = "gpio23"; 3074 function = "gpio"; 3075 }; 3076 3077 qup_spi6_data_clk: qup-spi6-data-clk { 3078 pins = "gpio24", "gpio25", "gpio26"; 3079 function = "qup06"; 3080 }; 3081 3082 qup_spi6_cs: qup-spi6-cs { 3083 pins = "gpio27"; 3084 function = "qup06"; 3085 }; 3086 3087 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3088 pins = "gpio27"; 3089 function = "gpio"; 3090 }; 3091 3092 qup_spi7_data_clk: qup-spi7-data-clk { 3093 pins = "gpio28", "gpio29", "gpio30"; 3094 function = "qup07"; 3095 }; 3096 3097 qup_spi7_cs: qup-spi7-cs { 3098 pins = "gpio31"; 3099 function = "qup07"; 3100 }; 3101 3102 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3103 pins = "gpio31"; 3104 function = "gpio"; 3105 }; 3106 3107 qup_spi8_data_clk: qup-spi8-data-clk { 3108 pins = "gpio32", "gpio33", "gpio34"; 3109 function = "qup10"; 3110 }; 3111 3112 qup_spi8_cs: qup-spi8-cs { 3113 pins = "gpio35"; 3114 function = "qup10"; 3115 }; 3116 3117 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3118 pins = "gpio35"; 3119 function = "gpio"; 3120 }; 3121 3122 qup_spi9_data_clk: qup-spi9-data-clk { 3123 pins = "gpio36", "gpio37", "gpio38"; 3124 function = "qup11"; 3125 }; 3126 3127 qup_spi9_cs: qup-spi9-cs { 3128 pins = "gpio39"; 3129 function = "qup11"; 3130 }; 3131 3132 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3133 pins = "gpio39"; 3134 function = "gpio"; 3135 }; 3136 3137 qup_spi10_data_clk: qup-spi10-data-clk { 3138 pins = "gpio40", "gpio41", "gpio42"; 3139 function = "qup12"; 3140 }; 3141 3142 qup_spi10_cs: qup-spi10-cs { 3143 pins = "gpio43"; 3144 function = "qup12"; 3145 }; 3146 3147 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3148 pins = "gpio43"; 3149 function = "gpio"; 3150 }; 3151 3152 qup_spi11_data_clk: qup-spi11-data-clk { 3153 pins = "gpio44", "gpio45", "gpio46"; 3154 function = "qup13"; 3155 }; 3156 3157 qup_spi11_cs: qup-spi11-cs { 3158 pins = "gpio47"; 3159 function = "qup13"; 3160 }; 3161 3162 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3163 pins = "gpio47"; 3164 function = "gpio"; 3165 }; 3166 3167 qup_spi12_data_clk: qup-spi12-data-clk { 3168 pins = "gpio48", "gpio49", "gpio50"; 3169 function = "qup14"; 3170 }; 3171 3172 qup_spi12_cs: qup-spi12-cs { 3173 pins = "gpio51"; 3174 function = "qup14"; 3175 }; 3176 3177 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3178 pins = "gpio51"; 3179 function = "gpio"; 3180 }; 3181 3182 qup_spi13_data_clk: qup-spi13-data-clk { 3183 pins = "gpio52", "gpio53", "gpio54"; 3184 function = "qup15"; 3185 }; 3186 3187 qup_spi13_cs: qup-spi13-cs { 3188 pins = "gpio55"; 3189 function = "qup15"; 3190 }; 3191 3192 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3193 pins = "gpio55"; 3194 function = "gpio"; 3195 }; 3196 3197 qup_spi14_data_clk: qup-spi14-data-clk { 3198 pins = "gpio56", "gpio57", "gpio58"; 3199 function = "qup16"; 3200 }; 3201 3202 qup_spi14_cs: qup-spi14-cs { 3203 pins = "gpio59"; 3204 function = "qup16"; 3205 }; 3206 3207 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3208 pins = "gpio59"; 3209 function = "gpio"; 3210 }; 3211 3212 qup_spi15_data_clk: qup-spi15-data-clk { 3213 pins = "gpio60", "gpio61", "gpio62"; 3214 function = "qup17"; 3215 }; 3216 3217 qup_spi15_cs: qup-spi15-cs { 3218 pins = "gpio63"; 3219 function = "qup17"; 3220 }; 3221 3222 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3223 pins = "gpio63"; 3224 function = "gpio"; 3225 }; 3226 3227 qup_uart0_cts: qup-uart0-cts { 3228 pins = "gpio0"; 3229 function = "qup00"; 3230 }; 3231 3232 qup_uart0_rts: qup-uart0-rts { 3233 pins = "gpio1"; 3234 function = "qup00"; 3235 }; 3236 3237 qup_uart0_tx: qup-uart0-tx { 3238 pins = "gpio2"; 3239 function = "qup00"; 3240 }; 3241 3242 qup_uart0_rx: qup-uart0-rx { 3243 pins = "gpio3"; 3244 function = "qup00"; 3245 }; 3246 3247 qup_uart1_cts: qup-uart1-cts { 3248 pins = "gpio4"; 3249 function = "qup01"; 3250 }; 3251 3252 qup_uart1_rts: qup-uart1-rts { 3253 pins = "gpio5"; 3254 function = "qup01"; 3255 }; 3256 3257 qup_uart1_tx: qup-uart1-tx { 3258 pins = "gpio6"; 3259 function = "qup01"; 3260 }; 3261 3262 qup_uart1_rx: qup-uart1-rx { 3263 pins = "gpio7"; 3264 function = "qup01"; 3265 }; 3266 3267 qup_uart2_cts: qup-uart2-cts { 3268 pins = "gpio8"; 3269 function = "qup02"; 3270 }; 3271 3272 qup_uart2_rts: qup-uart2-rts { 3273 pins = "gpio9"; 3274 function = "qup02"; 3275 }; 3276 3277 qup_uart2_tx: qup-uart2-tx { 3278 pins = "gpio10"; 3279 function = "qup02"; 3280 }; 3281 3282 qup_uart2_rx: qup-uart2-rx { 3283 pins = "gpio11"; 3284 function = "qup02"; 3285 }; 3286 3287 qup_uart3_cts: qup-uart3-cts { 3288 pins = "gpio12"; 3289 function = "qup03"; 3290 }; 3291 3292 qup_uart3_rts: qup-uart3-rts { 3293 pins = "gpio13"; 3294 function = "qup03"; 3295 }; 3296 3297 qup_uart3_tx: qup-uart3-tx { 3298 pins = "gpio14"; 3299 function = "qup03"; 3300 }; 3301 3302 qup_uart3_rx: qup-uart3-rx { 3303 pins = "gpio15"; 3304 function = "qup03"; 3305 }; 3306 3307 qup_uart4_cts: qup-uart4-cts { 3308 pins = "gpio16"; 3309 function = "qup04"; 3310 }; 3311 3312 qup_uart4_rts: qup-uart4-rts { 3313 pins = "gpio17"; 3314 function = "qup04"; 3315 }; 3316 3317 qup_uart4_tx: qup-uart4-tx { 3318 pins = "gpio18"; 3319 function = "qup04"; 3320 }; 3321 3322 qup_uart4_rx: qup-uart4-rx { 3323 pins = "gpio19"; 3324 function = "qup04"; 3325 }; 3326 3327 qup_uart5_cts: qup-uart5-cts { 3328 pins = "gpio20"; 3329 function = "qup05"; 3330 }; 3331 3332 qup_uart5_rts: qup-uart5-rts { 3333 pins = "gpio21"; 3334 function = "qup05"; 3335 }; 3336 3337 qup_uart5_tx: qup-uart5-tx { 3338 pins = "gpio22"; 3339 function = "qup05"; 3340 }; 3341 3342 qup_uart5_rx: qup-uart5-rx { 3343 pins = "gpio23"; 3344 function = "qup05"; 3345 }; 3346 3347 qup_uart6_cts: qup-uart6-cts { 3348 pins = "gpio24"; 3349 function = "qup06"; 3350 }; 3351 3352 qup_uart6_rts: qup-uart6-rts { 3353 pins = "gpio25"; 3354 function = "qup06"; 3355 }; 3356 3357 qup_uart6_tx: qup-uart6-tx { 3358 pins = "gpio26"; 3359 function = "qup06"; 3360 }; 3361 3362 qup_uart6_rx: qup-uart6-rx { 3363 pins = "gpio27"; 3364 function = "qup06"; 3365 }; 3366 3367 qup_uart7_cts: qup-uart7-cts { 3368 pins = "gpio28"; 3369 function = "qup07"; 3370 }; 3371 3372 qup_uart7_rts: qup-uart7-rts { 3373 pins = "gpio29"; 3374 function = "qup07"; 3375 }; 3376 3377 qup_uart7_tx: qup-uart7-tx { 3378 pins = "gpio30"; 3379 function = "qup07"; 3380 }; 3381 3382 qup_uart7_rx: qup-uart7-rx { 3383 pins = "gpio31"; 3384 function = "qup07"; 3385 }; 3386 3387 sdc1_on: sdc1-on { 3388 clk { 3389 pins = "sdc1_clk"; 3390 }; 3391 3392 cmd { 3393 pins = "sdc1_cmd"; 3394 }; 3395 3396 data { 3397 pins = "sdc1_data"; 3398 }; 3399 3400 rclk { 3401 pins = "sdc1_rclk"; 3402 }; 3403 }; 3404 3405 sdc1_off: sdc1-off { 3406 clk { 3407 pins = "sdc1_clk"; 3408 drive-strength = <2>; 3409 bias-bus-hold; 3410 }; 3411 3412 cmd { 3413 pins = "sdc1_cmd"; 3414 drive-strength = <2>; 3415 bias-bus-hold; 3416 }; 3417 3418 data { 3419 pins = "sdc1_data"; 3420 drive-strength = <2>; 3421 bias-bus-hold; 3422 }; 3423 3424 rclk { 3425 pins = "sdc1_rclk"; 3426 bias-bus-hold; 3427 }; 3428 }; 3429 3430 sdc2_on: sdc2-on { 3431 clk { 3432 pins = "sdc2_clk"; 3433 }; 3434 3435 cmd { 3436 pins = "sdc2_cmd"; 3437 }; 3438 3439 data { 3440 pins = "sdc2_data"; 3441 }; 3442 }; 3443 3444 sdc2_off: sdc2-off { 3445 clk { 3446 pins = "sdc2_clk"; 3447 drive-strength = <2>; 3448 bias-bus-hold; 3449 }; 3450 3451 cmd { 3452 pins ="sdc2_cmd"; 3453 drive-strength = <2>; 3454 bias-bus-hold; 3455 }; 3456 3457 data { 3458 pins ="sdc2_data"; 3459 drive-strength = <2>; 3460 bias-bus-hold; 3461 }; 3462 }; 3463 3464 qup_uart8_cts: qup-uart8-cts { 3465 pins = "gpio32"; 3466 function = "qup10"; 3467 }; 3468 3469 qup_uart8_rts: qup-uart8-rts { 3470 pins = "gpio33"; 3471 function = "qup10"; 3472 }; 3473 3474 qup_uart8_tx: qup-uart8-tx { 3475 pins = "gpio34"; 3476 function = "qup10"; 3477 }; 3478 3479 qup_uart8_rx: qup-uart8-rx { 3480 pins = "gpio35"; 3481 function = "qup10"; 3482 }; 3483 3484 qup_uart9_cts: qup-uart9-cts { 3485 pins = "gpio36"; 3486 function = "qup11"; 3487 }; 3488 3489 qup_uart9_rts: qup-uart9-rts { 3490 pins = "gpio37"; 3491 function = "qup11"; 3492 }; 3493 3494 qup_uart9_tx: qup-uart9-tx { 3495 pins = "gpio38"; 3496 function = "qup11"; 3497 }; 3498 3499 qup_uart9_rx: qup-uart9-rx { 3500 pins = "gpio39"; 3501 function = "qup11"; 3502 }; 3503 3504 qup_uart10_cts: qup-uart10-cts { 3505 pins = "gpio40"; 3506 function = "qup12"; 3507 }; 3508 3509 qup_uart10_rts: qup-uart10-rts { 3510 pins = "gpio41"; 3511 function = "qup12"; 3512 }; 3513 3514 qup_uart10_tx: qup-uart10-tx { 3515 pins = "gpio42"; 3516 function = "qup12"; 3517 }; 3518 3519 qup_uart10_rx: qup-uart10-rx { 3520 pins = "gpio43"; 3521 function = "qup12"; 3522 }; 3523 3524 qup_uart11_cts: qup-uart11-cts { 3525 pins = "gpio44"; 3526 function = "qup13"; 3527 }; 3528 3529 qup_uart11_rts: qup-uart11-rts { 3530 pins = "gpio45"; 3531 function = "qup13"; 3532 }; 3533 3534 qup_uart11_tx: qup-uart11-tx { 3535 pins = "gpio46"; 3536 function = "qup13"; 3537 }; 3538 3539 qup_uart11_rx: qup-uart11-rx { 3540 pins = "gpio47"; 3541 function = "qup13"; 3542 }; 3543 3544 qup_uart12_cts: qup-uart12-cts { 3545 pins = "gpio48"; 3546 function = "qup14"; 3547 }; 3548 3549 qup_uart12_rts: qup-uart12-rts { 3550 pins = "gpio49"; 3551 function = "qup14"; 3552 }; 3553 3554 qup_uart12_tx: qup-uart12-tx { 3555 pins = "gpio50"; 3556 function = "qup14"; 3557 }; 3558 3559 qup_uart12_rx: qup-uart12-rx { 3560 pins = "gpio51"; 3561 function = "qup14"; 3562 }; 3563 3564 qup_uart13_cts: qup-uart13-cts { 3565 pins = "gpio52"; 3566 function = "qup15"; 3567 }; 3568 3569 qup_uart13_rts: qup-uart13-rts { 3570 pins = "gpio53"; 3571 function = "qup15"; 3572 }; 3573 3574 qup_uart13_tx: qup-uart13-tx { 3575 pins = "gpio54"; 3576 function = "qup15"; 3577 }; 3578 3579 qup_uart13_rx: qup-uart13-rx { 3580 pins = "gpio55"; 3581 function = "qup15"; 3582 }; 3583 3584 qup_uart14_cts: qup-uart14-cts { 3585 pins = "gpio56"; 3586 function = "qup16"; 3587 }; 3588 3589 qup_uart14_rts: qup-uart14-rts { 3590 pins = "gpio57"; 3591 function = "qup16"; 3592 }; 3593 3594 qup_uart14_tx: qup-uart14-tx { 3595 pins = "gpio58"; 3596 function = "qup16"; 3597 }; 3598 3599 qup_uart14_rx: qup-uart14-rx { 3600 pins = "gpio59"; 3601 function = "qup16"; 3602 }; 3603 3604 qup_uart15_cts: qup-uart15-cts { 3605 pins = "gpio60"; 3606 function = "qup17"; 3607 }; 3608 3609 qup_uart15_rts: qup-uart15-rts { 3610 pins = "gpio61"; 3611 function = "qup17"; 3612 }; 3613 3614 qup_uart15_tx: qup-uart15-tx { 3615 pins = "gpio62"; 3616 function = "qup17"; 3617 }; 3618 3619 qup_uart15_rx: qup-uart15-rx { 3620 pins = "gpio63"; 3621 function = "qup17"; 3622 }; 3623 }; 3624 3625 imem@146a5000 { 3626 compatible = "qcom,sc7280-imem", "syscon"; 3627 reg = <0 0x146a5000 0 0x6000>; 3628 3629 #address-cells = <1>; 3630 #size-cells = <1>; 3631 3632 ranges = <0 0 0x146a5000 0x6000>; 3633 3634 pil-reloc@594c { 3635 compatible = "qcom,pil-reloc-info"; 3636 reg = <0x594c 0xc8>; 3637 }; 3638 }; 3639 3640 apps_smmu: iommu@15000000 { 3641 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3642 reg = <0 0x15000000 0 0x100000>; 3643 #iommu-cells = <2>; 3644 #global-interrupts = <1>; 3645 dma-coherent; 3646 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3727 }; 3728 3729 intc: interrupt-controller@17a00000 { 3730 compatible = "arm,gic-v3"; 3731 #address-cells = <2>; 3732 #size-cells = <2>; 3733 ranges; 3734 #interrupt-cells = <3>; 3735 interrupt-controller; 3736 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3737 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3738 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3739 3740 gic-its@17a40000 { 3741 compatible = "arm,gic-v3-its"; 3742 msi-controller; 3743 #msi-cells = <1>; 3744 reg = <0 0x17a40000 0 0x20000>; 3745 status = "disabled"; 3746 }; 3747 }; 3748 3749 watchdog@17c10000 { 3750 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3751 reg = <0 0x17c10000 0 0x1000>; 3752 clocks = <&sleep_clk>; 3753 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3754 }; 3755 3756 timer@17c20000 { 3757 #address-cells = <2>; 3758 #size-cells = <2>; 3759 ranges; 3760 compatible = "arm,armv7-timer-mem"; 3761 reg = <0 0x17c20000 0 0x1000>; 3762 3763 frame@17c21000 { 3764 frame-number = <0>; 3765 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3767 reg = <0 0x17c21000 0 0x1000>, 3768 <0 0x17c22000 0 0x1000>; 3769 }; 3770 3771 frame@17c23000 { 3772 frame-number = <1>; 3773 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3774 reg = <0 0x17c23000 0 0x1000>; 3775 status = "disabled"; 3776 }; 3777 3778 frame@17c25000 { 3779 frame-number = <2>; 3780 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3781 reg = <0 0x17c25000 0 0x1000>; 3782 status = "disabled"; 3783 }; 3784 3785 frame@17c27000 { 3786 frame-number = <3>; 3787 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3788 reg = <0 0x17c27000 0 0x1000>; 3789 status = "disabled"; 3790 }; 3791 3792 frame@17c29000 { 3793 frame-number = <4>; 3794 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3795 reg = <0 0x17c29000 0 0x1000>; 3796 status = "disabled"; 3797 }; 3798 3799 frame@17c2b000 { 3800 frame-number = <5>; 3801 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3802 reg = <0 0x17c2b000 0 0x1000>; 3803 status = "disabled"; 3804 }; 3805 3806 frame@17c2d000 { 3807 frame-number = <6>; 3808 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3809 reg = <0 0x17c2d000 0 0x1000>; 3810 status = "disabled"; 3811 }; 3812 }; 3813 3814 apps_rsc: rsc@18200000 { 3815 compatible = "qcom,rpmh-rsc"; 3816 reg = <0 0x18200000 0 0x10000>, 3817 <0 0x18210000 0 0x10000>, 3818 <0 0x18220000 0 0x10000>; 3819 reg-names = "drv-0", "drv-1", "drv-2"; 3820 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3823 qcom,tcs-offset = <0xd00>; 3824 qcom,drv-id = <2>; 3825 qcom,tcs-config = <ACTIVE_TCS 2>, 3826 <SLEEP_TCS 3>, 3827 <WAKE_TCS 3>, 3828 <CONTROL_TCS 1>; 3829 3830 apps_bcm_voter: bcm-voter { 3831 compatible = "qcom,bcm-voter"; 3832 }; 3833 3834 rpmhpd: power-controller { 3835 compatible = "qcom,sc7280-rpmhpd"; 3836 #power-domain-cells = <1>; 3837 operating-points-v2 = <&rpmhpd_opp_table>; 3838 3839 rpmhpd_opp_table: opp-table { 3840 compatible = "operating-points-v2"; 3841 3842 rpmhpd_opp_ret: opp1 { 3843 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3844 }; 3845 3846 rpmhpd_opp_low_svs: opp2 { 3847 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3848 }; 3849 3850 rpmhpd_opp_svs: opp3 { 3851 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3852 }; 3853 3854 rpmhpd_opp_svs_l1: opp4 { 3855 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3856 }; 3857 3858 rpmhpd_opp_svs_l2: opp5 { 3859 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3860 }; 3861 3862 rpmhpd_opp_nom: opp6 { 3863 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3864 }; 3865 3866 rpmhpd_opp_nom_l1: opp7 { 3867 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3868 }; 3869 3870 rpmhpd_opp_turbo: opp8 { 3871 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3872 }; 3873 3874 rpmhpd_opp_turbo_l1: opp9 { 3875 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3876 }; 3877 }; 3878 }; 3879 3880 rpmhcc: clock-controller { 3881 compatible = "qcom,sc7280-rpmh-clk"; 3882 clocks = <&xo_board>; 3883 clock-names = "xo"; 3884 #clock-cells = <1>; 3885 }; 3886 }; 3887 3888 cpufreq_hw: cpufreq@18591000 { 3889 compatible = "qcom,cpufreq-epss"; 3890 reg = <0 0x18591000 0 0x1000>, 3891 <0 0x18592000 0 0x1000>, 3892 <0 0x18593000 0 0x1000>; 3893 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3894 clock-names = "xo", "alternate"; 3895 #freq-domain-cells = <1>; 3896 }; 3897 }; 3898 3899 thermal_zones: thermal-zones { 3900 cpu0-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <0>; 3903 3904 thermal-sensors = <&tsens0 1>; 3905 3906 trips { 3907 cpu0_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu0_alert1: trip-point1 { 3914 temperature = <95000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu0_crit: cpu-crit { 3920 temperature = <110000>; 3921 hysteresis = <0>; 3922 type = "critical"; 3923 }; 3924 }; 3925 3926 cooling-maps { 3927 map0 { 3928 trip = <&cpu0_alert0>; 3929 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3933 }; 3934 map1 { 3935 trip = <&cpu0_alert1>; 3936 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3940 }; 3941 }; 3942 }; 3943 3944 cpu1-thermal { 3945 polling-delay-passive = <250>; 3946 polling-delay = <0>; 3947 3948 thermal-sensors = <&tsens0 2>; 3949 3950 trips { 3951 cpu1_alert0: trip-point0 { 3952 temperature = <90000>; 3953 hysteresis = <2000>; 3954 type = "passive"; 3955 }; 3956 3957 cpu1_alert1: trip-point1 { 3958 temperature = <95000>; 3959 hysteresis = <2000>; 3960 type = "passive"; 3961 }; 3962 3963 cpu1_crit: cpu-crit { 3964 temperature = <110000>; 3965 hysteresis = <0>; 3966 type = "critical"; 3967 }; 3968 }; 3969 3970 cooling-maps { 3971 map0 { 3972 trip = <&cpu1_alert0>; 3973 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3977 }; 3978 map1 { 3979 trip = <&cpu1_alert1>; 3980 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 }; 3986 }; 3987 3988 cpu2-thermal { 3989 polling-delay-passive = <250>; 3990 polling-delay = <0>; 3991 3992 thermal-sensors = <&tsens0 3>; 3993 3994 trips { 3995 cpu2_alert0: trip-point0 { 3996 temperature = <90000>; 3997 hysteresis = <2000>; 3998 type = "passive"; 3999 }; 4000 4001 cpu2_alert1: trip-point1 { 4002 temperature = <95000>; 4003 hysteresis = <2000>; 4004 type = "passive"; 4005 }; 4006 4007 cpu2_crit: cpu-crit { 4008 temperature = <110000>; 4009 hysteresis = <0>; 4010 type = "critical"; 4011 }; 4012 }; 4013 4014 cooling-maps { 4015 map0 { 4016 trip = <&cpu2_alert0>; 4017 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4021 }; 4022 map1 { 4023 trip = <&cpu2_alert1>; 4024 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4028 }; 4029 }; 4030 }; 4031 4032 cpu3-thermal { 4033 polling-delay-passive = <250>; 4034 polling-delay = <0>; 4035 4036 thermal-sensors = <&tsens0 4>; 4037 4038 trips { 4039 cpu3_alert0: trip-point0 { 4040 temperature = <90000>; 4041 hysteresis = <2000>; 4042 type = "passive"; 4043 }; 4044 4045 cpu3_alert1: trip-point1 { 4046 temperature = <95000>; 4047 hysteresis = <2000>; 4048 type = "passive"; 4049 }; 4050 4051 cpu3_crit: cpu-crit { 4052 temperature = <110000>; 4053 hysteresis = <0>; 4054 type = "critical"; 4055 }; 4056 }; 4057 4058 cooling-maps { 4059 map0 { 4060 trip = <&cpu3_alert0>; 4061 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4062 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4063 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4065 }; 4066 map1 { 4067 trip = <&cpu3_alert1>; 4068 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4072 }; 4073 }; 4074 }; 4075 4076 cpu4-thermal { 4077 polling-delay-passive = <250>; 4078 polling-delay = <0>; 4079 4080 thermal-sensors = <&tsens0 7>; 4081 4082 trips { 4083 cpu4_alert0: trip-point0 { 4084 temperature = <90000>; 4085 hysteresis = <2000>; 4086 type = "passive"; 4087 }; 4088 4089 cpu4_alert1: trip-point1 { 4090 temperature = <95000>; 4091 hysteresis = <2000>; 4092 type = "passive"; 4093 }; 4094 4095 cpu4_crit: cpu-crit { 4096 temperature = <110000>; 4097 hysteresis = <0>; 4098 type = "critical"; 4099 }; 4100 }; 4101 4102 cooling-maps { 4103 map0 { 4104 trip = <&cpu4_alert0>; 4105 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4109 }; 4110 map1 { 4111 trip = <&cpu4_alert1>; 4112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4116 }; 4117 }; 4118 }; 4119 4120 cpu5-thermal { 4121 polling-delay-passive = <250>; 4122 polling-delay = <0>; 4123 4124 thermal-sensors = <&tsens0 8>; 4125 4126 trips { 4127 cpu5_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <2000>; 4130 type = "passive"; 4131 }; 4132 4133 cpu5_alert1: trip-point1 { 4134 temperature = <95000>; 4135 hysteresis = <2000>; 4136 type = "passive"; 4137 }; 4138 4139 cpu5_crit: cpu-crit { 4140 temperature = <110000>; 4141 hysteresis = <0>; 4142 type = "critical"; 4143 }; 4144 }; 4145 4146 cooling-maps { 4147 map0 { 4148 trip = <&cpu5_alert0>; 4149 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4150 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4153 }; 4154 map1 { 4155 trip = <&cpu5_alert1>; 4156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4160 }; 4161 }; 4162 }; 4163 4164 cpu6-thermal { 4165 polling-delay-passive = <250>; 4166 polling-delay = <0>; 4167 4168 thermal-sensors = <&tsens0 9>; 4169 4170 trips { 4171 cpu6_alert0: trip-point0 { 4172 temperature = <90000>; 4173 hysteresis = <2000>; 4174 type = "passive"; 4175 }; 4176 4177 cpu6_alert1: trip-point1 { 4178 temperature = <95000>; 4179 hysteresis = <2000>; 4180 type = "passive"; 4181 }; 4182 4183 cpu6_crit: cpu-crit { 4184 temperature = <110000>; 4185 hysteresis = <0>; 4186 type = "critical"; 4187 }; 4188 }; 4189 4190 cooling-maps { 4191 map0 { 4192 trip = <&cpu6_alert0>; 4193 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4194 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4197 }; 4198 map1 { 4199 trip = <&cpu6_alert1>; 4200 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4204 }; 4205 }; 4206 }; 4207 4208 cpu7-thermal { 4209 polling-delay-passive = <250>; 4210 polling-delay = <0>; 4211 4212 thermal-sensors = <&tsens0 10>; 4213 4214 trips { 4215 cpu7_alert0: trip-point0 { 4216 temperature = <90000>; 4217 hysteresis = <2000>; 4218 type = "passive"; 4219 }; 4220 4221 cpu7_alert1: trip-point1 { 4222 temperature = <95000>; 4223 hysteresis = <2000>; 4224 type = "passive"; 4225 }; 4226 4227 cpu7_crit: cpu-crit { 4228 temperature = <110000>; 4229 hysteresis = <0>; 4230 type = "critical"; 4231 }; 4232 }; 4233 4234 cooling-maps { 4235 map0 { 4236 trip = <&cpu7_alert0>; 4237 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4238 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4241 }; 4242 map1 { 4243 trip = <&cpu7_alert1>; 4244 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4245 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4248 }; 4249 }; 4250 }; 4251 4252 cpu8-thermal { 4253 polling-delay-passive = <250>; 4254 polling-delay = <0>; 4255 4256 thermal-sensors = <&tsens0 11>; 4257 4258 trips { 4259 cpu8_alert0: trip-point0 { 4260 temperature = <90000>; 4261 hysteresis = <2000>; 4262 type = "passive"; 4263 }; 4264 4265 cpu8_alert1: trip-point1 { 4266 temperature = <95000>; 4267 hysteresis = <2000>; 4268 type = "passive"; 4269 }; 4270 4271 cpu8_crit: cpu-crit { 4272 temperature = <110000>; 4273 hysteresis = <0>; 4274 type = "critical"; 4275 }; 4276 }; 4277 4278 cooling-maps { 4279 map0 { 4280 trip = <&cpu8_alert0>; 4281 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4282 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4285 }; 4286 map1 { 4287 trip = <&cpu8_alert1>; 4288 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4289 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4292 }; 4293 }; 4294 }; 4295 4296 cpu9-thermal { 4297 polling-delay-passive = <250>; 4298 polling-delay = <0>; 4299 4300 thermal-sensors = <&tsens0 12>; 4301 4302 trips { 4303 cpu9_alert0: trip-point0 { 4304 temperature = <90000>; 4305 hysteresis = <2000>; 4306 type = "passive"; 4307 }; 4308 4309 cpu9_alert1: trip-point1 { 4310 temperature = <95000>; 4311 hysteresis = <2000>; 4312 type = "passive"; 4313 }; 4314 4315 cpu9_crit: cpu-crit { 4316 temperature = <110000>; 4317 hysteresis = <0>; 4318 type = "critical"; 4319 }; 4320 }; 4321 4322 cooling-maps { 4323 map0 { 4324 trip = <&cpu9_alert0>; 4325 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4326 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4327 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4329 }; 4330 map1 { 4331 trip = <&cpu9_alert1>; 4332 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4333 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4336 }; 4337 }; 4338 }; 4339 4340 cpu10-thermal { 4341 polling-delay-passive = <250>; 4342 polling-delay = <0>; 4343 4344 thermal-sensors = <&tsens0 13>; 4345 4346 trips { 4347 cpu10_alert0: trip-point0 { 4348 temperature = <90000>; 4349 hysteresis = <2000>; 4350 type = "passive"; 4351 }; 4352 4353 cpu10_alert1: trip-point1 { 4354 temperature = <95000>; 4355 hysteresis = <2000>; 4356 type = "passive"; 4357 }; 4358 4359 cpu10_crit: cpu-crit { 4360 temperature = <110000>; 4361 hysteresis = <0>; 4362 type = "critical"; 4363 }; 4364 }; 4365 4366 cooling-maps { 4367 map0 { 4368 trip = <&cpu10_alert0>; 4369 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4370 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4373 }; 4374 map1 { 4375 trip = <&cpu10_alert1>; 4376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4377 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4380 }; 4381 }; 4382 }; 4383 4384 cpu11-thermal { 4385 polling-delay-passive = <250>; 4386 polling-delay = <0>; 4387 4388 thermal-sensors = <&tsens0 14>; 4389 4390 trips { 4391 cpu11_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "passive"; 4395 }; 4396 4397 cpu11_alert1: trip-point1 { 4398 temperature = <95000>; 4399 hysteresis = <2000>; 4400 type = "passive"; 4401 }; 4402 4403 cpu11_crit: cpu-crit { 4404 temperature = <110000>; 4405 hysteresis = <0>; 4406 type = "critical"; 4407 }; 4408 }; 4409 4410 cooling-maps { 4411 map0 { 4412 trip = <&cpu11_alert0>; 4413 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4414 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4417 }; 4418 map1 { 4419 trip = <&cpu11_alert1>; 4420 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4421 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4424 }; 4425 }; 4426 }; 4427 4428 aoss0-thermal { 4429 polling-delay-passive = <0>; 4430 polling-delay = <0>; 4431 4432 thermal-sensors = <&tsens0 0>; 4433 4434 trips { 4435 aoss0_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "hot"; 4439 }; 4440 4441 aoss0_crit: aoss0-crit { 4442 temperature = <110000>; 4443 hysteresis = <0>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 4449 aoss1-thermal { 4450 polling-delay-passive = <0>; 4451 polling-delay = <0>; 4452 4453 thermal-sensors = <&tsens1 0>; 4454 4455 trips { 4456 aoss1_alert0: trip-point0 { 4457 temperature = <90000>; 4458 hysteresis = <2000>; 4459 type = "hot"; 4460 }; 4461 4462 aoss1_crit: aoss1-crit { 4463 temperature = <110000>; 4464 hysteresis = <0>; 4465 type = "critical"; 4466 }; 4467 }; 4468 }; 4469 4470 cpuss0-thermal { 4471 polling-delay-passive = <0>; 4472 polling-delay = <0>; 4473 4474 thermal-sensors = <&tsens0 5>; 4475 4476 trips { 4477 cpuss0_alert0: trip-point0 { 4478 temperature = <90000>; 4479 hysteresis = <2000>; 4480 type = "hot"; 4481 }; 4482 cpuss0_crit: cluster0-crit { 4483 temperature = <110000>; 4484 hysteresis = <0>; 4485 type = "critical"; 4486 }; 4487 }; 4488 }; 4489 4490 cpuss1-thermal { 4491 polling-delay-passive = <0>; 4492 polling-delay = <0>; 4493 4494 thermal-sensors = <&tsens0 6>; 4495 4496 trips { 4497 cpuss1_alert0: trip-point0 { 4498 temperature = <90000>; 4499 hysteresis = <2000>; 4500 type = "hot"; 4501 }; 4502 cpuss1_crit: cluster0-crit { 4503 temperature = <110000>; 4504 hysteresis = <0>; 4505 type = "critical"; 4506 }; 4507 }; 4508 }; 4509 4510 gpuss0-thermal { 4511 polling-delay-passive = <100>; 4512 polling-delay = <0>; 4513 4514 thermal-sensors = <&tsens1 1>; 4515 4516 trips { 4517 gpuss0_alert0: trip-point0 { 4518 temperature = <95000>; 4519 hysteresis = <2000>; 4520 type = "passive"; 4521 }; 4522 4523 gpuss0_crit: gpuss0-crit { 4524 temperature = <110000>; 4525 hysteresis = <0>; 4526 type = "critical"; 4527 }; 4528 }; 4529 4530 cooling-maps { 4531 map0 { 4532 trip = <&gpuss0_alert0>; 4533 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4534 }; 4535 }; 4536 }; 4537 4538 gpuss1-thermal { 4539 polling-delay-passive = <100>; 4540 polling-delay = <0>; 4541 4542 thermal-sensors = <&tsens1 2>; 4543 4544 trips { 4545 gpuss1_alert0: trip-point0 { 4546 temperature = <95000>; 4547 hysteresis = <2000>; 4548 type = "passive"; 4549 }; 4550 4551 gpuss1_crit: gpuss1-crit { 4552 temperature = <110000>; 4553 hysteresis = <0>; 4554 type = "critical"; 4555 }; 4556 }; 4557 4558 cooling-maps { 4559 map0 { 4560 trip = <&gpuss1_alert0>; 4561 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4562 }; 4563 }; 4564 }; 4565 4566 nspss0-thermal { 4567 polling-delay-passive = <0>; 4568 polling-delay = <0>; 4569 4570 thermal-sensors = <&tsens1 3>; 4571 4572 trips { 4573 nspss0_alert0: trip-point0 { 4574 temperature = <90000>; 4575 hysteresis = <2000>; 4576 type = "hot"; 4577 }; 4578 4579 nspss0_crit: nspss0-crit { 4580 temperature = <110000>; 4581 hysteresis = <0>; 4582 type = "critical"; 4583 }; 4584 }; 4585 }; 4586 4587 nspss1-thermal { 4588 polling-delay-passive = <0>; 4589 polling-delay = <0>; 4590 4591 thermal-sensors = <&tsens1 4>; 4592 4593 trips { 4594 nspss1_alert0: trip-point0 { 4595 temperature = <90000>; 4596 hysteresis = <2000>; 4597 type = "hot"; 4598 }; 4599 4600 nspss1_crit: nspss1-crit { 4601 temperature = <110000>; 4602 hysteresis = <0>; 4603 type = "critical"; 4604 }; 4605 }; 4606 }; 4607 4608 video-thermal { 4609 polling-delay-passive = <0>; 4610 polling-delay = <0>; 4611 4612 thermal-sensors = <&tsens1 5>; 4613 4614 trips { 4615 video_alert0: trip-point0 { 4616 temperature = <90000>; 4617 hysteresis = <2000>; 4618 type = "hot"; 4619 }; 4620 4621 video_crit: video-crit { 4622 temperature = <110000>; 4623 hysteresis = <0>; 4624 type = "critical"; 4625 }; 4626 }; 4627 }; 4628 4629 ddr-thermal { 4630 polling-delay-passive = <0>; 4631 polling-delay = <0>; 4632 4633 thermal-sensors = <&tsens1 6>; 4634 4635 trips { 4636 ddr_alert0: trip-point0 { 4637 temperature = <90000>; 4638 hysteresis = <2000>; 4639 type = "hot"; 4640 }; 4641 4642 ddr_crit: ddr-crit { 4643 temperature = <110000>; 4644 hysteresis = <0>; 4645 type = "critical"; 4646 }; 4647 }; 4648 }; 4649 4650 mdmss0-thermal { 4651 polling-delay-passive = <0>; 4652 polling-delay = <0>; 4653 4654 thermal-sensors = <&tsens1 7>; 4655 4656 trips { 4657 mdmss0_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "hot"; 4661 }; 4662 4663 mdmss0_crit: mdmss0-crit { 4664 temperature = <110000>; 4665 hysteresis = <0>; 4666 type = "critical"; 4667 }; 4668 }; 4669 }; 4670 4671 mdmss1-thermal { 4672 polling-delay-passive = <0>; 4673 polling-delay = <0>; 4674 4675 thermal-sensors = <&tsens1 8>; 4676 4677 trips { 4678 mdmss1_alert0: trip-point0 { 4679 temperature = <90000>; 4680 hysteresis = <2000>; 4681 type = "hot"; 4682 }; 4683 4684 mdmss1_crit: mdmss1-crit { 4685 temperature = <110000>; 4686 hysteresis = <0>; 4687 type = "critical"; 4688 }; 4689 }; 4690 }; 4691 4692 mdmss2-thermal { 4693 polling-delay-passive = <0>; 4694 polling-delay = <0>; 4695 4696 thermal-sensors = <&tsens1 9>; 4697 4698 trips { 4699 mdmss2_alert0: trip-point0 { 4700 temperature = <90000>; 4701 hysteresis = <2000>; 4702 type = "hot"; 4703 }; 4704 4705 mdmss2_crit: mdmss2-crit { 4706 temperature = <110000>; 4707 hysteresis = <0>; 4708 type = "critical"; 4709 }; 4710 }; 4711 }; 4712 4713 mdmss3-thermal { 4714 polling-delay-passive = <0>; 4715 polling-delay = <0>; 4716 4717 thermal-sensors = <&tsens1 10>; 4718 4719 trips { 4720 mdmss3_alert0: trip-point0 { 4721 temperature = <90000>; 4722 hysteresis = <2000>; 4723 type = "hot"; 4724 }; 4725 4726 mdmss3_crit: mdmss3-crit { 4727 temperature = <110000>; 4728 hysteresis = <0>; 4729 type = "critical"; 4730 }; 4731 }; 4732 }; 4733 4734 camera0-thermal { 4735 polling-delay-passive = <0>; 4736 polling-delay = <0>; 4737 4738 thermal-sensors = <&tsens1 11>; 4739 4740 trips { 4741 camera0_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "hot"; 4745 }; 4746 4747 camera0_crit: camera0-crit { 4748 temperature = <110000>; 4749 hysteresis = <0>; 4750 type = "critical"; 4751 }; 4752 }; 4753 }; 4754 }; 4755 4756 timer { 4757 compatible = "arm,armv8-timer"; 4758 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4759 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4760 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4761 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4762 }; 4763}; 4764