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Searched refs:CONFIG_SYS_CLK_FREQ (Results 1 – 25 of 178) sorted by relevance

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/openbmc/u-boot/arch/xtensa/lib/
H A Dtime.c52 ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000; in __udelay()
75 return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base; in get_timer()
86 return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base; in get_timer()
115 return ccount / (CONFIG_SYS_CLK_FREQ / 1000000); in timer_get_us()
/openbmc/u-boot/include/configs/
H A Drsk7269.h46 #define CONFIG_SYS_CLK_FREQ 66125000 macro
47 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
49 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
H A Drsk7264.h47 #define CONFIG_SYS_CLK_FREQ 36000000 macro
48 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
50 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
H A Drsk7203.h58 #define CONFIG_SYS_CLK_FREQ 33333333 macro
59 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
61 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
H A Dshmin.h75 #define CONFIG_SYS_CLK_FREQ 40000000 macro
77 #define CONFIG_SYS_CLK_FREQ 33333333 macro
79 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dap_sh4a_4a.h96 #define CONFIG_SYS_CLK_FREQ 50000000 macro
98 #define CONFIG_SYS_CLK_FREQ 44444444 macro
100 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dr0p7734.h94 #define CONFIG_SYS_CLK_FREQ 50000000 macro
96 #define CONFIG_SYS_CLK_FREQ 44444444 macro
98 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Darmadillo-800eva.h23 #define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
95 #define CONFIG_SYS_CLK_FREQ 50000000 macro
96 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dexynos-common.h24 #define CONFIG_SYS_CLK_FREQ 24000000 macro
25 #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ
H A Dmpr2.h49 #define CONFIG_SYS_CLK_FREQ 24000000 macro
50 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dms7750se.h62 #define CONFIG_SYS_CLK_FREQ 33333333 macro
63 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dsh7752evb.h77 #define CONFIG_SYS_CLK_FREQ 48000000 macro
78 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dsh7753evb.h77 #define CONFIG_SYS_CLK_FREQ 48000000 macro
78 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dsh7763rdp.h68 #define CONFIG_SYS_CLK_FREQ 66666666 macro
69 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Despt.h68 #define CONFIG_SYS_CLK_FREQ 66666666 macro
69 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A DMigoR.h90 #define CONFIG_SYS_CLK_FREQ 33333333 macro
91 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dms7720se.h60 #define CONFIG_SYS_CLK_FREQ 33333333 macro
61 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dr2dplus.h46 #define CONFIG_SYS_CLK_FREQ 60000000 macro
47 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dms7722se.h80 #define CONFIG_SYS_CLK_FREQ 33333333 macro
81 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dsh7757lcr.h89 #define CONFIG_SYS_CLK_FREQ 48000000 macro
90 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dap325rxa.h111 #define CONFIG_SYS_CLK_FREQ 33333333 macro
112 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Decovec.h130 #define CONFIG_SYS_CLK_FREQ 41666666 macro
131 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
H A Dr7780mp.h71 #define CONFIG_SYS_CLK_FREQ 33333333 macro
72 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
/openbmc/u-boot/arch/nds32/cpu/n1213/ag101/
H A Dtimer.c74 (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ); in reset_timer_masked()
99 (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ); in get_timer_masked()
153 long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000; in __udelay()
188 return CONFIG_SYS_CLK_FREQ; in get_tbclk()
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c30 uint64_t rate = CONFIG_SYS_CLK_FREQ; in get_PLLCLK()
90 uclk_rate = CONFIG_SYS_CLK_FREQ; in get_UCLK()
92 uclk_rate = CONFIG_SYS_CLK_FREQ / 2; in get_UCLK()

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