1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 21a2621baSYoshihiro Shimoda /* 31a2621baSYoshihiro Shimoda * Configuation settings for the sh7752evb board 41a2621baSYoshihiro Shimoda * 51a2621baSYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 61a2621baSYoshihiro Shimoda */ 71a2621baSYoshihiro Shimoda 81a2621baSYoshihiro Shimoda #ifndef __SH7752EVB_H 91a2621baSYoshihiro Shimoda #define __SH7752EVB_H 101a2621baSYoshihiro Shimoda 111a2621baSYoshihiro Shimoda #define CONFIG_CPU_SH7752 1 121a2621baSYoshihiro Shimoda 1318a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 141a2621baSYoshihiro Shimoda #undef CONFIG_SHOW_BOOT_PROGRESS 151a2621baSYoshihiro Shimoda 161a2621baSYoshihiro Shimoda /* MEMORY */ 171a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_BASE (0x40000000) 181a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) 191a2621baSYoshihiro Shimoda 201a2621baSYoshihiro Shimoda #define CONFIG_SYS_PBSIZE 256 211a2621baSYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 221a2621baSYoshihiro Shimoda 231a2621baSYoshihiro Shimoda /* SCIF */ 241a2621baSYoshihiro Shimoda #define CONFIG_CONS_SCIF2 1 251a2621baSYoshihiro Shimoda 261a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) 271a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 281a2621baSYoshihiro Shimoda 480 * 1024 * 1024) 291a2621baSYoshihiro Shimoda #undef CONFIG_SYS_MEMTEST_SCRATCH 301a2621baSYoshihiro Shimoda #undef CONFIG_SYS_LOADS_BAUD_CHANGE 311a2621baSYoshihiro Shimoda 321a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) 331a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) 341a2621baSYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 351a2621baSYoshihiro Shimoda 128 * 1024 * 1024) 361a2621baSYoshihiro Shimoda 371a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE 0x00000000 381a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 391a2621baSYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 401a2621baSYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 411a2621baSYoshihiro Shimoda 421a2621baSYoshihiro Shimoda /* Ether */ 431a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT 0 441a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR 18 451a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 461a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER 1 471a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII 481a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI 491a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII 501a2621baSYoshihiro Shimoda #define CONFIG_PHY_VITESSE 511a2621baSYoshihiro Shimoda 521a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 531a2621baSYoshihiro Shimoda #define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) 541a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI 551a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_SIZE 17 561a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_NUM_CH 2 571a2621baSYoshihiro Shimoda 581a2621baSYoshihiro Shimoda /* SPI */ 591a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI_BASE 0xfe002000 601a2621baSYoshihiro Shimoda 611a2621baSYoshihiro Shimoda /* MMCIF */ 621a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 631a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK 48000000 641a2621baSYoshihiro Shimoda 651a2621baSYoshihiro Shimoda /* ENV setting */ 661a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED 671a2621baSYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE (64 * 1024) 681a2621baSYoshihiro Shimoda #define CONFIG_ENV_ADDR (0x00080000) 691a2621baSYoshihiro Shimoda #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 701a2621baSYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE 1 711a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 721a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 731a2621baSYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS \ 741a2621baSYoshihiro Shimoda "netboot=bootp; bootm\0" 751a2621baSYoshihiro Shimoda 761a2621baSYoshihiro Shimoda /* Board Clock */ 771a2621baSYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ 48000000 78684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 791a2621baSYoshihiro Shimoda #endif /* __SH7752EVB_H */ 80