1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c0bbdccSNobuhiro Iwamatsu /* 36c0bbdccSNobuhiro Iwamatsu * Configuation settings for the Hitachi Solution Engine 7722 46c0bbdccSNobuhiro Iwamatsu * 56c0bbdccSNobuhiro Iwamatsu * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 66c0bbdccSNobuhiro Iwamatsu */ 76c0bbdccSNobuhiro Iwamatsu 86c0bbdccSNobuhiro Iwamatsu #ifndef __MS7722SE_H 96c0bbdccSNobuhiro Iwamatsu #define __MS7722SE_H 106c0bbdccSNobuhiro Iwamatsu 116c0bbdccSNobuhiro Iwamatsu #define CONFIG_CPU_SH7722 1 126c0bbdccSNobuhiro Iwamatsu 1318a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 146c0bbdccSNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 156c0bbdccSNobuhiro Iwamatsu 166c0bbdccSNobuhiro Iwamatsu /* SMC9111 */ 177194ab80SBen Warren #define CONFIG_SMC91111 186c0bbdccSNobuhiro Iwamatsu #define CONFIG_SMC91111_BASE (0xB8000000) 196c0bbdccSNobuhiro Iwamatsu 206c0bbdccSNobuhiro Iwamatsu /* MEMORY */ 216c0bbdccSNobuhiro Iwamatsu #define MS7722SE_SDRAM_BASE (0x8C000000) 226c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BASE_1 (0xA0000000) 236c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) 246c0bbdccSNobuhiro Iwamatsu 256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 276c0bbdccSNobuhiro Iwamatsu 286c0bbdccSNobuhiro Iwamatsu /* SCIF */ 296c0bbdccSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0 1 306c0bbdccSNobuhiro Iwamatsu 316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) 326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 336c0bbdccSNobuhiro Iwamatsu 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ 356c0bbdccSNobuhiro Iwamatsu 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ 376c0bbdccSNobuhiro Iwamatsu 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE) 396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ 406c0bbdccSNobuhiro Iwamatsu 416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ 426c0bbdccSNobuhiro Iwamatsu 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image 446c0bbdccSNobuhiro Iwamatsu in Flash (NOT run time address in SDRAM) ?!? */ 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */ 466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ 476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 486c0bbdccSNobuhiro Iwamatsu 496c0bbdccSNobuhiro Iwamatsu /* FLASH */ 506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 526c0bbdccSNobuhiro Iwamatsu 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ 546c0bbdccSNobuhiro Iwamatsu 556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each 566c0bbdccSNobuhiro Iwamatsu Flash chip */ 576c0bbdccSNobuhiro Iwamatsu 586c0bbdccSNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ 626c0bbdccSNobuhiro Iwamatsu } 636c0bbdccSNobuhiro Iwamatsu 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ 686c0bbdccSNobuhiro Iwamatsu 696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_DIRECT_FLASH_TFTP 706c0bbdccSNobuhiro Iwamatsu 716c0bbdccSNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 720e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (8 * 1024) 730e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 760e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 786c0bbdccSNobuhiro Iwamatsu 796c0bbdccSNobuhiro Iwamatsu /* Board Clock */ 806c0bbdccSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 33333333 81684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 826c0bbdccSNobuhiro Iwamatsu 836c0bbdccSNobuhiro Iwamatsu #endif /* __MS7722SE_H */ 84