1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23313e0e2SMark Jonas /* 33313e0e2SMark Jonas * Configuation settings for MPR2 43313e0e2SMark Jonas * 53313e0e2SMark Jonas * Copyright (C) 2008 63313e0e2SMark Jonas * Mark Jonas <mark.jonas@de.bosch.com> 73313e0e2SMark Jonas */ 83313e0e2SMark Jonas 93313e0e2SMark Jonas #ifndef __MPR2_H 103313e0e2SMark Jonas #define __MPR2_H 113313e0e2SMark Jonas 123313e0e2SMark Jonas /* Supported commands */ 133313e0e2SMark Jonas 143313e0e2SMark Jonas /* Default environment variables */ 15b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "/boot/zImage" 163313e0e2SMark Jonas #define CONFIG_LOADADDR 0x8E000000 173313e0e2SMark Jonas 183313e0e2SMark Jonas /* CPU and platform */ 193313e0e2SMark Jonas #define CONFIG_CPU_SH7720 1 203313e0e2SMark Jonas 2118a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 2218a40e84SVladimir Zapolskiy 233313e0e2SMark Jonas /* U-Boot internals */ 246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 293313e0e2SMark Jonas 303313e0e2SMark Jonas /* Memory */ 316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE 0x8C000000 326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 353313e0e2SMark Jonas 363313e0e2SMark Jonas /* Flash */ 376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xA0000000 396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 256 406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 420e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (128 * 1024) 430e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 473313e0e2SMark Jonas 483313e0e2SMark Jonas /* Clocks */ 493313e0e2SMark Jonas #define CONFIG_SYS_CLK_FREQ 24000000 50684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 513313e0e2SMark Jonas 523313e0e2SMark Jonas /* UART */ 533313e0e2SMark Jonas #define CONFIG_CONS_SCIF0 1 543313e0e2SMark Jonas 553313e0e2SMark Jonas #endif /* __MPR2_H */ 56