xref: /openbmc/u-boot/include/configs/sh7763rdp.h (revision 2fe88d452268d61b5ca9cb0b1dda2974cc43faeb)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
27faddaecSNobuhiro Iwamatsu /*
37faddaecSNobuhiro Iwamatsu  * Configuation settings for the Renesas SH7763RDP board
47faddaecSNobuhiro Iwamatsu  *
57faddaecSNobuhiro Iwamatsu  * Copyright (C) 2008 Renesas Solutions Corp.
67faddaecSNobuhiro Iwamatsu  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
77faddaecSNobuhiro Iwamatsu  */
87faddaecSNobuhiro Iwamatsu 
97faddaecSNobuhiro Iwamatsu #ifndef __SH7763RDP_H
107faddaecSNobuhiro Iwamatsu #define __SH7763RDP_H
117faddaecSNobuhiro Iwamatsu 
127faddaecSNobuhiro Iwamatsu #define CONFIG_CPU_SH7763	1
137faddaecSNobuhiro Iwamatsu #define __LITTLE_ENDIAN		1
147faddaecSNobuhiro Iwamatsu 
157faddaecSNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE    1
167faddaecSNobuhiro Iwamatsu 
1718a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO
187faddaecSNobuhiro Iwamatsu #undef  CONFIG_SHOW_BOOT_PROGRESS
197faddaecSNobuhiro Iwamatsu 
207faddaecSNobuhiro Iwamatsu /* SCIF */
217faddaecSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF2		1
227faddaecSNobuhiro Iwamatsu 
236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
257faddaecSNobuhiro Iwamatsu 												settings for this board */
267faddaecSNobuhiro Iwamatsu 
277faddaecSNobuhiro Iwamatsu /* SDRAM */
286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
327faddaecSNobuhiro Iwamatsu 
337faddaecSNobuhiro Iwamatsu /* Flash(NOR) */
346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS (1)
376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT  (520)
387faddaecSNobuhiro Iwamatsu 
39a187559eSBin Meng /* U-Boot setting */
406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
437faddaecSNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */
446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
467faddaecSNobuhiro Iwamatsu 
476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_FLASH_QUIET_TEST
486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
497faddaecSNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */
506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
517faddaecSNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */
526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
537faddaecSNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */
546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
557faddaecSNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */
566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
577faddaecSNobuhiro Iwamatsu /* Use hardware flash sectors protection instead of U-Boot software protection */
586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
590e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
600e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
640e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
667faddaecSNobuhiro Iwamatsu 
677faddaecSNobuhiro Iwamatsu /* Clock */
687faddaecSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ	66666666
69684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
707faddaecSNobuhiro Iwamatsu 
71ba932445SNobuhiro Iwamatsu /* Ether */
72ba932445SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT (1)
73ba932445SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
74c8ceca95SYoshihiro Shimoda #define CONFIG_BITBANGMII
75c8ceca95SYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI
76a80a6619SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
77ba932445SNobuhiro Iwamatsu 
787faddaecSNobuhiro Iwamatsu #endif /* __SH7763RDP_H */
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