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/openbmc/linux/net/netlabel/
H A Dnetlabel_addrlist.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NetLabel Network Address Lists
5 * This file contains network address list functions used to manage ordered
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
32 * Address List Functions
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
37 * @addr: IPv4 address
41 * Searches the IPv4 address list given by @head. If a matching address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
[all …]
H A Dnetlabel_domainhash.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2006, 2008
55 * netlbl_domhsh_free_entry - Frees a domain hash table entry
56 * @entry: the entry's RCU field
60 * function so that the memory allocated to a hash table entry can be released
64 static void netlbl_domhsh_free_entry(struct rcu_head *entry) in netlbl_domhsh_free_entry() argument
74 ptr = container_of(entry, struct netlbl_dom_map, rcu); in netlbl_domhsh_free_entry()
75 if (ptr->def.type == NETLBL_NLTYPE_ADDRSELECT) { in netlbl_domhsh_free_entry()
77 &ptr->def.addrsel->list4) { in netlbl_domhsh_free_entry()
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dmpspec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 u32 mpf_physptr; /* Configuration table address */
42 u32 mpc_oemptr; /* OEM table address */
45 u32 mpc_lapic; /* Local APIC address */
51 /* Base MP configuration table entry types */
147 /* Extended MP configuration table entry types */
190 * X100 - X3FF
191 * X500 - X7FF
192 * X900 - XBFF
193 * XD00 - XFFF
[all …]
/openbmc/qemu/target/sh4/
H A Dhelper.c23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
33 #define MMU_ITLB_MISS (-1)
34 #define MMU_ITLB_MULTIPLE (-2)
35 #define MMU_ITLB_VIOLATION (-3)
36 #define MMU_DTLB_MISS_READ (-4)
37 #define MMU_DTLB_MISS_WRITE (-5)
38 #define MMU_DTLB_INITIAL_WRITE (-6)
39 #define MMU_DTLB_VIOLATION_READ (-7)
40 #define MMU_DTLB_VIOLATION_WRITE (-8)
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
[all …]
/openbmc/u-boot/drivers/misc/
H A Dqfw.c1 // SPDX-License-Identifier: GPL-2.0+
27 * @entry : BIOS linker command entry which tells where to allocate memory
29 * @addr : The address that should be used for low memory allcation. If the
34 static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr) in bios_linker_allocate() argument
40 align = le32_to_cpu(entry->alloc.align); in bios_linker_allocate()
42 if (align & (align - 1)) { in bios_linker_allocate()
44 return -EINVAL; in bios_linker_allocate()
47 file = qemu_fwcfg_find_file(entry->alloc.file); in bios_linker_allocate()
49 printf("error: can't find file %s\n", entry->alloc.file); in bios_linker_allocate()
50 return -ENOENT; in bios_linker_allocate()
[all …]
/openbmc/linux/arch/sh/mm/
H A Dtlbex_32.c5 * Copyright (C) 2003 - 2012 Paul Mundt
23 unsigned long address) in handle_tlbmiss() argument
30 pte_t entry; in handle_tlbmiss() local
35 * 29-bit mode, or due to PMB configuration in 32-bit mode. in handle_tlbmiss()
37 if (address >= P3SEG && address < P3_ADDR_MAX) { in handle_tlbmiss()
38 pgd = pgd_offset_k(address); in handle_tlbmiss()
40 if (unlikely(address >= TASK_SIZE || !current->mm)) in handle_tlbmiss()
43 pgd = pgd_offset(current->mm, address); in handle_tlbmiss()
46 p4d = p4d_offset(pgd, address); in handle_tlbmiss()
49 pud = pud_offset(p4d, address); in handle_tlbmiss()
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/
H A Dimages-r2.txt7 NOR0ADDRESS: 0x00000000 ;Image Flash Address
9 NOR0LOAD: 00000000 ;Image Load Address
10 NOR0ENTRY: 00000000 ;Image Entry Point
13 NOR1ADDRESS: 0x03EC0000 ;Image Flash Address
15 NOR1LOAD: 00000000 ;Image Load Address
16 NOR1ENTRY: 00000000 ;Image Entry Point
19 NOR2ADDRESS: 0x00500000 ;Image Flash Address
22 NOR2LOAD: 00000000 ;Image Load Address
23 NOR2ENTRY: 00000000 ;Image Entry Point
26 NOR3ADDRESS: 0x03000000 ;Image Flash Address
[all …]
H A Dimages-r1.txt7 NOR0ADDRESS: 0x00000000 ;Image Flash Address
9 NOR0LOAD: 00000000 ;Image Load Address
10 NOR0ENTRY: 00000000 ;Image Entry Point
13 NOR1ADDRESS: 0x03EC0000 ;Image Flash Address
15 NOR1LOAD: 00000000 ;Image Load Address
16 NOR1ENTRY: 00000000 ;Image Entry Point
19 NOR2ADDRESS: 0x00500000 ;Image Flash Address
22 NOR2LOAD: 00000000 ;Image Load Address
23 NOR2ENTRY: 00000000 ;Image Entry Point
26 NOR3ADDRESS: 0x03000000 ;Image Flash Address
[all …]
/openbmc/linux/arch/arm/mm/
H A Dcache-fa.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
18 #include "proc-macros.S"
42 ENTRY(fa_flush_icache_all)
51 * Clean and invalidate all cache entries in a particular address
54 ENTRY(fa_flush_user_cache_all)
61 ENTRY(fa_flush_kern_cache_all)
[all …]
H A Dcache-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wb.S
5 * Copyright (C) 1997-2002 Russell king
11 #include "proc-macros.S"
38 * 32768 150 149 150 214 216 212 <---
41 * Whole 132 136 132 221 217 207 <---
56 ENTRY(v4wb_flush_icache_all)
65 * Clean and invalidate all cache entries in a particular address
68 ENTRY(v4wb_flush_user_cache_all)
75 ENTRY(v4wb_flush_kern_cache_all)
[all …]
H A Dproc-arm946.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 * (Many of cache codes are from proc-arm926.S)
14 #include <asm/pgtable-hwdef.h>
16 #include "proc-macros.S"
19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
35 ENTRY(cpu_arm946_proc_init)
36 ENTRY(cpu_arm946_switch_mm)
42 ENTRY(cpu_arm946_proc_fin)
[all …]
H A Dcache-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4.S
5 * Copyright (C) 1997-2002 Russell king
11 #include "proc-macros.S"
18 ENTRY(v4_flush_icache_all)
25 * Invalidate all cache entries in a particular address
28 * - mm - mm_struct describing address space
30 ENTRY(v4_flush_user_cache_all)
37 ENTRY(v4_flush_kern_cache_all)
50 * address space.
[all …]
H A Dcache-v4wt.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wt.S
5 * Copyright (C) 1997-2002 Russell king
15 #include "proc-macros.S"
46 ENTRY(v4wt_flush_icache_all)
55 * Invalidate all cache entries in a particular address
58 ENTRY(v4wt_flush_user_cache_all)
65 ENTRY(v4wt_flush_kern_cache_all)
78 * address space.
80 * - start - start address (inclusive, page aligned)
[all …]
H A Dproc-arm926.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
5 * Copyright (C) 1999-2001 ARM Limited
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
19 #include <asm/pgtable-hwdef.h>
22 #include "proc-macros.S"
26 * using the single invalidate entry instructions. Anything larger
43 ENTRY(cpu_arm926_proc_init)
49 ENTRY(cpu_arm926_proc_fin)
[all …]
H A Dproc-arm922.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
8 * hacked for non-paged-MM by Hyok S. Choi, 2003.
13 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
53 ENTRY(cpu_arm922_proc_init)
59 ENTRY(cpu_arm922_proc_fin)
77 ENTRY(cpu_arm922_reset)
96 ENTRY(cpu_arm922_do_idle)
[all …]
H A Dproc-mohawk.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
7 * Heavily based on proc-arm926.S and proc-xsc3.S
15 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
34 ENTRY(cpu_mohawk_proc_init)
40 ENTRY(cpu_mohawk_proc_fin)
60 ENTRY(cpu_mohawk_reset)
79 ENTRY(cpu_mohawk_do_idle)
90 ENTRY(mohawk_flush_icache_all)
[all …]
H A Dproc-arm925.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Copyright (C) 2002-2003 MontaVista Software, Inc.
10 * Update for Linux-2.6 and cache flush improvements
13 * hacked for non-paged-MM by Hyok S. Choi, 2004.
18 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
23 * entry mode" must be 0 to flush the entries in both segments
24 * at once. This is the default value. See TRM 2-20 and 2-24 for
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
[all …]
H A Dproc-arm920.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
12 * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
19 #include <asm/pgtable-hwdef.h>
22 #include "proc-macros.S"
51 ENTRY(cpu_arm920_proc_init)
57 ENTRY(cpu_arm920_proc_fin)
75 ENTRY(cpu_arm920_reset)
94 ENTRY(cpu_arm920_do_idle)
[all …]
H A Dproc-arm1022.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
16 #include <asm/asm-offsets.h>
18 #include <asm/pgtable-hwdef.h>
21 #include "proc-macros.S"
25 * using the single invalidate entry instructions. Anything larger
59 ENTRY(cpu_arm1022_proc_init)
65 ENTRY(cpu_arm1022_proc_fin)
83 ENTRY(cpu_arm1022_reset)
[all …]
H A Dproc-arm1026.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
10 * functions on the ARM1026EJ-S.
16 #include <asm/asm-offsets.h>
18 #include <asm/pgtable-hwdef.h>
21 #include "proc-macros.S"
25 * using the single invalidate entry instructions. Anything larger
59 ENTRY(cpu_arm1026_proc_init)
65 ENTRY(cpu_arm1026_proc_fin)
[all …]
H A Dproc-feroceon.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
5 * Heavily based on proc-arm926.S
14 #include <asm/pgtable-hwdef.h>
17 #include "proc-macros.S"
21 * using the single invalidate entry instructions. Anything larger
46 ENTRY(cpu_feroceon_proc_init)
52 movne r3, #((4 - 1) << 30) @ 4-way
54 moveq r3, #0 @ 1-way
68 ENTRY(cpu_feroceon_proc_fin)
[all …]
H A Dproc-arm1020e.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
16 #include <asm/asm-offsets.h>
18 #include <asm/pgtable-hwdef.h>
21 #include "proc-macros.S"
25 * using the single invalidate entry instructions. Anything larger
59 ENTRY(cpu_arm1020e_proc_init)
65 ENTRY(cpu_arm1020e_proc_fin)
83 ENTRY(cpu_arm1020e_reset)
[all …]
/openbmc/qemu/target/s390x/
H A Dmmu_helper.c19 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
22 #include "s390x-internal.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "hw/s390x/storage-keys.h"
46 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); in trigger_access_exception()
52 /* check whether the address would be proteted by Low-Address Protection */
58 /* check whether Low-Address Protection is enabled for mmu_translate() */
61 if (!(env->cregs[0] & CR0_LOWPROT)) { in lowprot_enabled()
[all …]
/openbmc/linux/mm/
H A Dpage_vma_mapped.c1 // SPDX-License-Identifier: GPL-2.0
20 if (pvmw->flags & PVMW_SYNC) { in map_pte()
22 pvmw->pte = pte_offset_map_lock(pvmw->vma->vm_mm, pvmw->pmd, in map_pte()
23 pvmw->address, &pvmw->ptl); in map_pte()
24 *ptlp = pvmw->ptl; in map_pte()
25 return !!pvmw->pte; in map_pte()
30 * in case *pvmw->pmd changes underneath us; so we need to in map_pte()
35 pvmw->pte = pte_offset_map_nolock(pvmw->vma->vm_mm, pvmw->pmd, in map_pte()
36 pvmw->address, ptlp); in map_pte()
37 if (!pvmw->pte) in map_pte()
[all …]

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