arm/mm/proc-arm925.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8  *  Copyright (C) 2002-2003 MontaVista Software, Inc.
10  *  Update for Linux-2.6 and cache flush improvements
13  *  hacked for non-paged-MM by Hyok S. Choi, 2004.
18  *  CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20  * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22  * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
23  *	  entry mode" must be 0 to flush the entries in both segments
24  *	  at once. This is the default value. See TRM 2-20 and 2-24 for
27  * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
29  *	  to work in this mode. This mode only works with 16-bit external
30  *	  memory. See TRM 2-24 for more information.
32  * NOTE3: Write-back cache flushing seems to be flakey with devices using
34  *        write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
35  *        the default for OMAP-1510).
43 #include <asm/pgtable-hwdef.h>
46 #include "proc-macros.S"
74 ENTRY(cpu_arm925_proc_init)
80 ENTRY(cpu_arm925_proc_fin)
98 ENTRY(cpu_arm925_reset)
126 ENTRY(cpu_arm925_do_idle)
141 ENTRY(arm925_flush_icache_all)
151  *	address space.
153 ENTRY(arm925_flush_user_cache_all)
161 ENTRY(arm925_flush_kern_cache_all)
169 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
183  *	specified address range.
185  *	- start	- start address (inclusive)
186  *	- end	- end address (exclusive)
187  *	- flags	- vm_flags describing address space
189 ENTRY(arm925_flush_user_cache_range)
196 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
197 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
199 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
200 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
203 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
204 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
206 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
207 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
220  *	region described by start, end.  If you have non-snooping
223  *	- start	- virtual start address
224  *	- end	- virtual end address
226 ENTRY(arm925_coherent_kern_range)
233  *	region described by start, end.  If you have non-snooping
236  *	- start	- virtual start address
237  *	- end	- virtual end address
239 ENTRY(arm925_coherent_user_range)
240 	bic	r0, r0, #CACHE_DLINESIZE - 1
241 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
242 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
256  *	- addr	- kernel address
257  *	- size	- region size
259 ENTRY(arm925_flush_kern_dcache_area)
261 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
273  *	Invalidate (discard) the specified virtual address range.
278  *	- start	- virtual start address
279  *	- end	- virtual end address
285 	tst	r0, #CACHE_DLINESIZE - 1
286 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
287 	tst	r1, #CACHE_DLINESIZE - 1
288 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
290 	bic	r0, r0, #CACHE_DLINESIZE - 1
291 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
301  *	Clean the specified virtual address range.
303  *	- start	- virtual start address
304  *	- end	- virtual end address
310 	bic	r0, r0, #CACHE_DLINESIZE - 1
311 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
322  *	Clean and invalidate the specified virtual address range.
324  *	- start	- virtual start address
325  *	- end	- virtual end address
327 ENTRY(arm925_dma_flush_range)
328 	bic	r0, r0, #CACHE_DLINESIZE - 1
331 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
333 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
343  *	- start	- kernel virtual start address
344  *	- size	- size of region
345  *	- dir	- DMA direction
347 ENTRY(arm925_dma_map_area)
357  *	- start	- kernel virtual start address
358  *	- size	- size of region
359  *	- dir	- DMA direction
361 ENTRY(arm925_dma_unmap_area)
368 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
371 ENTRY(cpu_arm925_dcache_clean_area)
373 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
391 ENTRY(cpu_arm925_switch_mm)
398 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
416 ENTRY(cpu_arm925_set_pte_ext)
421 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
431 	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
443 	mov	r0, #4				@ disable write-back on caches explicitly
456 	.size	__arm925_setup, . - __arm925_setup
469 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
505 	.size	__\name\()_proc_info, . - __\name\()_proc_info