19 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
22 #include "s390x-internal.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "hw/s390x/storage-keys.h"
46             stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);  in trigger_access_exception()
52 /* check whether the address would be proteted by Low-Address Protection */
58 /* check whether Low-Address Protection is enabled for mmu_translate() */
61     if (!(env->cregs[0] & CR0_LOWPROT)) {  in lowprot_enabled()
64     if (!(env->psw.mask & PSW_MASK_DAT)) {  in lowprot_enabled()
68     /* Check the private-space control bit */  in lowprot_enabled()
71         return !(env->cregs[1] & ASCE_PRIVATE_SPACE);  in lowprot_enabled()
73         return !(env->cregs[7] & ASCE_PRIVATE_SPACE);  in lowprot_enabled()
75         return !(env->cregs[13] & ASCE_PRIVATE_SPACE);  in lowprot_enabled()
84  * Translate real address to absolute (= physical)
85  * address by taking care of the prefix mapping.
90         return raddr + env->psa;    /* Map the lowcore. */  in mmu_real2abs()
91     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {  in mmu_real2abs()
92         return raddr - env->psa;    /* Map the 0 page. */  in mmu_real2abs()
106                                     uint64_t *entry)  in read_table_entry()  argument
112      * or absolute". Also, "it is unpredictable whether the address wraps  in read_table_entry()
117     if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,  in read_table_entry()
118                                     entry, sizeof(*entry)) !=  in read_table_entry()
122     *entry = be64_to_cpu(*entry);  in read_table_entry()
130     const bool edat1 = (env->cregs[0] & CR0_EDAT) &&  in mmu_translate_asce()
133     const bool iep = (env->cregs[0] & CR0_IEP) &&  in mmu_translate_asce()
138     uint64_t entry;  in mmu_translate_asce()  local
185         if (!read_table_entry(env, gaddr, &entry)) {  in mmu_translate_asce()
188         if (entry & REGION_ENTRY_I) {  in mmu_translate_asce()
191         if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {  in mmu_translate_asce()
194         if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||  in mmu_translate_asce()
195             VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {  in mmu_translate_asce()
198         if (edat1 && (entry & REGION_ENTRY_P)) {  in mmu_translate_asce()
201         gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;  in mmu_translate_asce()
204         if (!read_table_entry(env, gaddr, &entry)) {  in mmu_translate_asce()
207         if (entry & REGION_ENTRY_I) {  in mmu_translate_asce()
210         if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {  in mmu_translate_asce()
213         if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||  in mmu_translate_asce()
214             VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {  in mmu_translate_asce()
217         if (edat1 && (entry & REGION_ENTRY_P)) {  in mmu_translate_asce()
220         gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;  in mmu_translate_asce()
223         if (!read_table_entry(env, gaddr, &entry)) {  in mmu_translate_asce()
226         if (entry & REGION_ENTRY_I) {  in mmu_translate_asce()
229         if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {  in mmu_translate_asce()
232         if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {  in mmu_translate_asce()
235         if (edat1 && (entry & REGION_ENTRY_P)) {  in mmu_translate_asce()
238         if (edat2 && (entry & REGION3_ENTRY_FC)) {  in mmu_translate_asce()
239             if (iep && (entry & REGION3_ENTRY_IEP)) {  in mmu_translate_asce()
242             *raddr = (entry & REGION3_ENTRY_RFAA) |  in mmu_translate_asce()
246         if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||  in mmu_translate_asce()
247             VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {  in mmu_translate_asce()
250         gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;  in mmu_translate_asce()
253         if (!read_table_entry(env, gaddr, &entry)) {  in mmu_translate_asce()
256         if (entry & SEGMENT_ENTRY_I) {  in mmu_translate_asce()
259         if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {  in mmu_translate_asce()
262         if ((entry & SEGMENT_ENTRY_CS) && asce_p) {  in mmu_translate_asce()
265         if (entry & SEGMENT_ENTRY_P) {  in mmu_translate_asce()
268         if (edat1 && (entry & SEGMENT_ENTRY_FC)) {  in mmu_translate_asce()
269             if (iep && (entry & SEGMENT_ENTRY_IEP)) {  in mmu_translate_asce()
272             *raddr = (entry & SEGMENT_ENTRY_SFAA) |  in mmu_translate_asce()
276         gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;  in mmu_translate_asce()
280     if (!read_table_entry(env, gaddr, &entry)) {  in mmu_translate_asce()
283     if (entry & PAGE_ENTRY_I) {  in mmu_translate_asce()
286     if (entry & PAGE_ENTRY_0) {  in mmu_translate_asce()
289     if (entry & PAGE_ENTRY_P) {  in mmu_translate_asce()
292     if (iep && (entry & PAGE_ENTRY_IEP)) {  in mmu_translate_asce()
296     *raddr = entry & TARGET_PAGE_MASK;  in mmu_translate_asce()
307      * We expect to be called with an absolute address that has already been  in mmu_handle_skey()
319     if (!skeyclass->skeys_are_enabled(ss)) {  in mmu_handle_skey()
324      * Whenever we create a new TLB entry, we set the storage key reference  in mmu_handle_skey()
333      *         -> We can set reference/change bits even on exceptions.  in mmu_handle_skey()
337      * TODO: key-controlled protection. Only CPU accesses make use of the  in mmu_handle_skey()
338      *       PSW key. CSS accesses are different - we have to pass in the key.  in mmu_handle_skey()
351          * The TLB entry has to remain write-protected on read-faults if  in mmu_handle_skey()
375  * Translate a virtual (logical) address into a physical (absolute) address.
376  * @param vaddr  the virtual address
377  * @param rw     0 = read, 1 = write, 2 = code fetch, < 0 = load real address
378  * @param asc    address space control (one of the PSW_ASC_* modes)
379  * @param raddr  the translated address is stored to this pointer
398          * TLB entry will not be reused.  in mmu_translate()
402          * just by looking at the start address (triggering the tlb miss).  in mmu_translate()
414     if (rw != MMU_S390_LRA && !(env->psw.mask & PSW_MASK_DAT)) {  in mmu_translate()
421         asce = env->cregs[1];  in mmu_translate()
424         asce = env->cregs[13];  in mmu_translate()
427         asce = env->cregs[7];  in mmu_translate()
448     /* check for Instruction-Execution-Protection */  in mmu_translate()
457         /* Convert real address -> absolute address */  in mmu_translate()
478     uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;  in translate_pages()
479     CPUS390XState *env = &cpu->env;  in translate_pages()
509  * @laddr:     the logical start address
514  * Returns:    0 on success, non-zero if an exception occurred
537     nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)  in s390_cpu_virt_mem_rw()
543         trigger_access_exception(&cpu->env, ret, tec);  in s390_cpu_virt_mem_rw()
547             currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));  in s390_cpu_virt_mem_rw()
552             len -= currlen;  in s390_cpu_virt_mem_rw()
571  * Translate a real address into a physical (absolute) address.
572  * @param raddr  the real address
574  * @param addr   the translated address is stored to this pointer
581     const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;  in mmu_translate_real()