5  *  Copyright (C) 2003 - 2012  Paul Mundt
23 	       unsigned long address)  in handle_tlbmiss()  argument
30 	pte_t entry;  in handle_tlbmiss()  local
35 	 * 29-bit mode, or due to PMB configuration in 32-bit mode.  in handle_tlbmiss()
37 	if (address >= P3SEG && address < P3_ADDR_MAX) {  in handle_tlbmiss()
38 		pgd = pgd_offset_k(address);  in handle_tlbmiss()
40 		if (unlikely(address >= TASK_SIZE || !current->mm))  in handle_tlbmiss()
43 		pgd = pgd_offset(current->mm, address);  in handle_tlbmiss()
46 	p4d = p4d_offset(pgd, address);  in handle_tlbmiss()
49 	pud = pud_offset(p4d, address);  in handle_tlbmiss()
52 	pmd = pmd_offset(pud, address);  in handle_tlbmiss()
55 	pte = pte_offset_kernel(pmd, address);  in handle_tlbmiss()
56 	entry = *pte;  in handle_tlbmiss()
57 	if (unlikely(pte_none(entry) || pte_not_present(entry)))  in handle_tlbmiss()
59 	if (unlikely(error_code && !pte_write(entry)))  in handle_tlbmiss()
63 		entry = pte_mkdirty(entry);  in handle_tlbmiss()
64 	entry = pte_mkyoung(entry);  in handle_tlbmiss()
66 	set_pte(pte, entry);  in handle_tlbmiss()
70 	 * SH-4 does not set MMUCR.RC to the corresponding TLB entry in  in handle_tlbmiss()
72 	 * flush it in order to avoid potential TLB entry duplication.  in handle_tlbmiss()
75 		local_flush_tlb_one(get_asid(), address & PAGE_MASK);  in handle_tlbmiss()
79 	update_mmu_cache(NULL, address, pte);  in handle_tlbmiss()