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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mvebu.yaml124 reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
136 reg = <0x18140 0x40>, <0x181c8 0x08>;
145 clocks = <&coreclk 0>;
/openbmc/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dsoc.h13 #define SOC_MV78230_ID 0x7823
14 #define SOC_MV78260_ID 0x7826
15 #define SOC_MV78460_ID 0x7846
16 #define SOC_88F6720_ID 0x6720
17 #define SOC_88F6810_ID 0x6810
18 #define SOC_88F6820_ID 0x6820
19 #define SOC_88F6828_ID 0x6828
20 #define SOC_98DX3236_ID 0xf410
21 #define SOC_98DX3336_ID 0xf400
22 #define SOC_98DX4251_ID 0xfc00
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-xp-mv78230.dtsi63 #size-cells = <0>;
66 cpu@0 {
69 reg = <0>;
70 clocks = <&cpuclk 0>;
85 * MV78230 has 2 PCIe units Gen2.0: One unit can be
98 bus-range = <0x00 0xff>;
101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
[all …]
H A Darmada-xp-mv78260.dtsi64 #size-cells = <0>;
67 cpu@0 {
70 reg = <0>;
71 clocks = <&cpuclk 0>;
86 * MV78260 has 3 PCIe units Gen2.0: Two units can be
99 bus-range = <0x00 0xff>;
102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi65 #size-cells = <0>;
68 cpu@0 {
71 reg = <0>;
72 clocks = <&cpuclk 0>;
103 * MV78460 has 4 PCIe units Gen2.0: Two units can be
116 bus-range = <0x00 0xff>;
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-375.dtsi71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #size-cells = <0>;
87 cpu@0 {
90 reg = <0>;
111 pcie-mem-aperture = <0xe0000000 0x8000000>;
112 pcie-io-aperture = <0xe8000000 0x100000>;
116 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
121 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Darmada-38x.dtsi41 pcie-mem-aperture = <0xe0000000 0x8000000>;
42 pcie-io-aperture = <0xe8000000 0x100000>;
46 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
51 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
52 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
55 clocks = <&coreclk 0>;
61 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
62 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
65 clocks = <&coreclk 0>;
71 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx25xx.dtsi21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
86 /* 16M internal register @ 0x7f00_0000 */
87 ranges = <0x0 0x0 0x7f000000 0x1000000>;
92 reg = <0x12000 0x100>;
102 reg = <0x12100 0x100>;
112 reg = <0x12200 0x100>;
122 reg = <0x12300 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78230.dtsi26 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
33 clocks = <&cpuclk 0>;
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
[all …]
H A Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]
H A Darmada-370.dtsi35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
47 bus-range = <0x00 0xff>;
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
57 pcie0: pcie@1,0 {
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
[all …]
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sm8250.c36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]
H A Dgcc-sc7280.c44 .offset = 0x0,
47 .enable_reg = 0x52010,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 { 0x3, 3 },
88 .offset = 0x0,
105 .offset = 0x1000,
108 .enable_reg = 0x52010,
122 .offset = 0x1e000,
[all …]
H A Dgcc-sm8350.c44 .offset = 0x0,
47 .enable_reg = 0x52018,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 .offset = 0x76000,
86 .enable_reg = 0x52018,
101 .offset = 0x1c000,
104 .enable_reg = 0x52018,
119 { P_BI_TCXO, 0 },
[all …]