Lines Matching +full:0 +full:x18140
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
86 /* 16M internal register @ 0x7f00_0000 */
87 ranges = <0x0 0x0 0x7f000000 0x1000000>;
92 reg = <0x12000 0x100>;
102 reg = <0x12100 0x100>;
112 reg = <0x12200 0x100>;
122 reg = <0x12300 0x100>;
132 #size-cells = <0>;
134 reg = <0x22004 0x4>;
140 reg = <0x11000 0x20>;
142 #size-cells = <0>;
150 pinctrl-0 = <&i2c0_pins>;
159 reg = <0x11100 0x20>;
161 #size-cells = <0>;
169 pinctrl-0 = <&i2c1_pins>;
178 reg = <0x18100 0x40>;
182 gpio-ranges = <&pinctrl0 0 0 32>;
183 marvell,pwm-offset = <0x1f0>;
193 reg = <0x18140 0x40>;
198 gpio-ranges = <&pinctrl0 0 32 14>;
199 marvell,pwm-offset = <0x1f0>;
213 #address-cells = <0x2>;
214 #size-cells = <0x2>;
215 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
216 /* Host phy ram starts at 0x200M */
217 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
222 reg = <0x0 0x20000 0x0 0x4000>;
231 reg = <0x0 0x24000 0x0 0x4000>;
240 reg = <0x0 0x80000 0x0 0x500>;
247 reg = <0x0 0xa0000 0x0 0x500>;
255 reg = <0 0x80020100 0 0x20>;
280 reg = <0x0 0x805a0000 0x0 0x50>;
281 #address-cells = <0x1>;
282 #size-cells = <0x0>;
291 reg = <0x0 0x805a8000 0x0 0x50>;
292 #address-cells = <0x1>;
293 #size-cells = <0x0>;
302 reg = <0x0 0x805b0000 0x0 0x00000054>;
303 #address-cells = <0x1>;
304 #size-cells = <0x0>;
314 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
315 <0x0 0x80660000 0x0 0x40000>; /* GICR */
323 #clock-cells = <0>;
329 #clock-cells = <0>;
335 #clock-cells = <0>;