Lines Matching +full:0 +full:x18140
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #size-cells = <0>;
87 cpu@0 {
90 reg = <0>;
111 pcie-mem-aperture = <0xe0000000 0x8000000>;
112 pcie-io-aperture = <0xe8000000 0x100000>;
116 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
121 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
125 clocks = <&coreclk 0>;
131 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
132 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
135 clocks = <&coreclk 0>;
141 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
142 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
145 clocks = <&coreclk 0>;
151 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
152 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
155 clocks = <&coreclk 0>;
161 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
162 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
165 clocks = <&coreclk 0>;
174 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
178 reg = <0x8000 0x1000>;
182 arm,double-linefill-wrap = <0>;
189 reg = <0xc000 0x58>;
194 reg = <0xc600 0x20>;
202 #size-cells = <0>;
204 reg = <0xd000 0x1000>,
205 <0xc100 0x100>;
210 #size-cells = <0>;
212 reg = <0xc0054 0x4>;
219 reg = <0xf0000 0xa000>, /* Packet Processor regs */
220 <0xc0000 0x3060>, /* LMS regs */
221 <0xc4000 0x100>, /* eth0 regs */
222 <0xc5000 0x100>; /* eth1 regs */
229 port-id = <0>;
242 reg = <0x10300 0x20>;
249 reg = <0x10600 0x50>;
251 #size-cells = <0>;
252 cell-index = <0>;
254 clocks = <&coreclk 0>;
261 reg = <0x10680 0x50>;
263 #size-cells = <0>;
266 clocks = <&coreclk 0>;
272 reg = <0x11000 0x20>;
274 #size-cells = <0>;
277 clocks = <&coreclk 0>;
283 reg = <0x11100 0x20>;
285 #size-cells = <0>;
288 clocks = <&coreclk 0>;
294 reg = <0x12000 0x100>;
298 clocks = <&coreclk 0>;
304 reg = <0x12100 0x100>;
308 clocks = <&coreclk 0>;
314 reg = <0x18000 0x24>;
350 reg = <0x18100 0x40>;
364 reg = <0x18140 0x40>;
378 reg = <0x18180 0x40>;
389 reg = <0x18200 0x100>;
394 reg = <0x18220 0x4>;
395 clocks = <&coreclk 0>;
401 reg = <0x18400 0x4>;
407 reg = <0x20000 0x100>, <0x20180 0x20>;
412 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
422 reg = <0x20300 0x30>, <0x21040 0x30>;
429 clocks = <&coreclk 0>, <&refclk>;
435 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
436 clocks = <&coreclk 0>, <&refclk>;
442 reg = <0x20800 0x10>;
447 reg = <0x21010 0x1c>;
452 reg = <0x50000 0x500>;
462 reg = <0x54000 0x500>;
470 reg = <0x58000 0x20000>,<0x5b880 0x80>;
480 reg = <0x60800 0x100
481 0x60A00 0x100>;
500 reg = <0x60900 0x100
501 0x60b00 0x100>;
520 reg = <0x90000 0x10000>;
530 marvell,crypto-sram-size = <0x800>;
535 reg = <0xa0000 0x5000>;
538 clock-names = "0", "1";
544 reg = <0xd0000 0x54>;
554 reg = <0xd4000 0x200>;
566 reg = <0xe8078 0x4>, <0xe807c 0x8>;
572 reg = <0xe8204 0x04>;
578 reg = <0xe8250 0xc>;
594 bus-range = <0x00 0xff>;
597 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
598 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
599 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
600 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
601 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
602 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
604 pcie0: pcie@1,0 {
606 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
607 reg = <0x0800 0 0 0 0>;
611 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
612 0x81000000 0 0 0x81000000 0x1 0 1 0>;
613 bus-range = <0x00 0xff>;
614 interrupt-map-mask = <0 0 0 0>;
615 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
616 marvell,pcie-port = <0>;
617 marvell,pcie-lane = <0>;
622 pcie1: pcie@2,0 {
624 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
625 reg = <0x1000 0 0 0 0>;
629 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
630 0x81000000 0 0 0x81000000 0x2 0 1 0>;
631 bus-range = <0x00 0xff>;
632 interrupt-map-mask = <0 0 0 0>;
633 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 marvell,pcie-port = <0>;
644 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
648 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
653 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
657 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;