arm/dts/armada-xp-mv78230.dtsi

63 		#size-cells = <0>;
66 		cpu@0 {
69 			reg = <0>;
70 			clocks = <&cpuclk 0>;
85 		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
98 			bus-range = <0x00 0xff>;
101 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
102 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
103 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
104 				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
105 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
106 				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
107 				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
108 				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
109 				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
110 				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
111 				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
112 				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
113 				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
114 				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
115 				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;
117 			pcie1: pcie@1,0 {
119 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
120 				reg = <0x0800 0 0 0 0>;
124 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
125 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
126 				bus-range = <0x00 0xff>;
127 				interrupt-map-mask = <0 0 0 0>;
128 				interrupt-map = <0 0 0 0 &mpic 58>;
129 				marvell,pcie-port = <0>;
130 				marvell,pcie-lane = <0>;
135 			pcie2: pcie@2,0 {
137 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
138 				reg = <0x1000 0 0 0 0>;
142 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
143 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
144 				bus-range = <0x00 0xff>;
145 				interrupt-map-mask = <0 0 0 0>;
146 				interrupt-map = <0 0 0 0 &mpic 59>;
147 				marvell,pcie-port = <0>;
153 			pcie3: pcie@3,0 {
155 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
156 				reg = <0x1800 0 0 0 0>;
160 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
161 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
162 				bus-range = <0x00 0xff>;
163 				interrupt-map-mask = <0 0 0 0>;
164 				interrupt-map = <0 0 0 0 &mpic 60>;
165 				marvell,pcie-port = <0>;
171 			pcie4: pcie@4,0 {
173 				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
174 				reg = <0x2000 0 0 0 0>;
178 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
179 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
180 				bus-range = <0x00 0xff>;
181 				interrupt-map-mask = <0 0 0 0>;
182 				interrupt-map = <0 0 0 0 &mpic 61>;
183 				marvell,pcie-port = <0>;
189 			pcie5: pcie@5,0 {
191 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
192 				reg = <0x2800 0 0 0 0>;
196 				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
197 					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
198 				bus-range = <0x00 0xff>;
199 				interrupt-map-mask = <0 0 0 0>;
200 				interrupt-map = <0 0 0 0 &mpic 62>;
202 				marvell,pcie-lane = <0>;
211 				reg = <0x18100 0x40>;
222 				reg = <0x18140 0x40>;