include/mach/soc.h

13 #define SOC_MV78230_ID		0x7823
14 #define SOC_MV78260_ID		0x7826
15 #define SOC_MV78460_ID		0x7846
16 #define SOC_88F6720_ID		0x6720
17 #define SOC_88F6810_ID		0x6810
18 #define SOC_88F6820_ID		0x6820
19 #define SOC_88F6828_ID		0x6828
20 #define SOC_98DX3236_ID		0xf410
21 #define SOC_98DX3336_ID		0xf400
22 #define SOC_98DX4251_ID		0xfc00
25 #define MV_88F67XX_A0_ID	0x3
28 #define MV_88F68XX_Z1_ID	0x0
29 #define MV_88F68XX_A0_ID	0x4
30 #define MV_88F68XX_B0_ID	0xa
38 #define INTREG_BASE		0xd0000000
39 #define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
48 #define SOC_REGS_PHY_BASE	0xd0000000
50 #define SOC_REGS_PHY_BASE	0xf0000000
52 #define SOC_REGS_PHY_BASE	0xf1000000
56 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
57 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
59 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
60 #define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
61 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
62 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
63 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
64 #define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
65 #define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
66 #define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
67 #define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
68 #define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
69 #define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
70 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
71 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
72 #define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
73 #define MVEBU_REG_PCIE0_BASE	(MVEBU_REGISTER(0x80000))
74 #define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
75 #define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
76 #define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
77 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
78 #define MVEBU_LCD_BASE		(MVEBU_REGISTER(0xe0000))
79 #define MVEBU_DFX_BASE		(MVEBU_REGISTER(0xe4000))
81 #define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
84 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
85 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
87 #define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
88 #define NAND_EN			BIT(0)
91 #define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
92 #define GE0_PUP_EN		BIT(0)
98 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
99 #define MVEBU_DFX_DIV_CLK_CTRL(i)	(MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
101 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
104 #define SDRAM_ADDR_MASK		0xFF000000
111 #define COMPHY_REFCLK_ALIGNMENT	(MVEBU_REGISTER(0x182f8))
114 #define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
116 #define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
117 #define BOOTROM_ERR_MODE_UART	0x6
118 #define BOOTROM_ERR_CODE_OFFS	0
119 #define BOOTROM_ERR_CODE_MASK	(0xf << BOOTROM_ERR_CODE_OFFS)
123 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0xe8200))
124 #define CONFIG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
127 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
130 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
132 #define BOOT_FROM_UART		0x30
133 #define BOOT_FROM_SPI		0x38
136 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18600))
139 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
141 #define SAR_BOOT_DEVICE_MASK	(0x1f << SAR_BOOT_DEVICE_OFFS)
144 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
146 #define BOOT_FROM_NAND		0x0A
147 #define BOOT_FROM_UART		0x28
148 #define BOOT_FROM_UART_ALT	0x3f
149 #define BOOT_FROM_SPI		0x32
150 #define BOOT_FROM_MMC		0x30
151 #define BOOT_FROM_MMC_ALT	0x31
154 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
155 #define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))
158 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
160 #define SAR_FFC_FREQ_MASK	(0xf << SAR_FFC_FREQ_OFFS)
162 #define SAR2_CPU_FREQ_MASK	(0x1 << SAR2_CPU_FREQ_OFFS)
164 #define SAR_BOOT_DEVICE_MASK	(0xf << SAR_BOOT_DEVICE_OFFS)
167 #define BOOT_DEV_SEL_MASK	(0xf << BOOT_DEV_SEL_OFFS)
169 #define BOOT_FROM_UART		0x2
170 #define BOOT_FROM_SPI		0x3