Lines Matching +full:0 +full:x18140
44 .offset = 0x0,
47 .enable_reg = 0x52010,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 { 0x3, 3 },
88 .offset = 0x0,
105 .offset = 0x1000,
108 .enable_reg = 0x52010,
122 .offset = 0x1e000,
125 .enable_reg = 0x52010,
139 .offset = 0x76000,
142 .enable_reg = 0x52010,
156 .offset = 0x1c000,
159 .enable_reg = 0x52010,
175 .enable_reg = 0x52000,
190 { P_BI_TCXO, 0 },
202 { P_BI_TCXO, 0 },
216 { P_BI_TCXO, 0 },
226 { P_BI_TCXO, 0 },
234 { P_BI_TCXO, 0 },
250 { P_BI_TCXO, 0 },
260 { P_BI_TCXO, 0 },
276 { P_BI_TCXO, 0 },
294 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
304 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
314 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
324 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
334 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
344 { P_BI_TCXO, 0 },
354 .reg = 0x6b054,
369 .reg = 0x8d054,
384 .reg = 0x77058,
385 .shift = 0,
399 .reg = 0x770c8,
400 .shift = 0,
414 .reg = 0x77048,
415 .shift = 0,
429 .reg = 0xf060,
430 .shift = 0,
444 .reg = 0x9e060,
445 .shift = 0,
459 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
460 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
461 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
466 .cmd_rcgr = 0x64004,
480 .cmd_rcgr = 0x65004,
494 .cmd_rcgr = 0x66004,
508 F(9600000, P_BI_TCXO, 2, 0, 0),
509 F(19200000, P_BI_TCXO, 1, 0, 0),
514 .cmd_rcgr = 0x6b058,
528 F(19200000, P_BI_TCXO, 1, 0, 0),
529 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
534 .cmd_rcgr = 0x6b03c,
535 .mnd_width = 0,
548 .cmd_rcgr = 0x8d058,
562 .cmd_rcgr = 0x8d03c,
563 .mnd_width = 0,
577 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
582 .cmd_rcgr = 0x33010,
583 .mnd_width = 0,
597 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
598 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
599 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
600 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
605 .cmd_rcgr = 0x4b00c,
606 .mnd_width = 0,
621 F(19200000, P_BI_TCXO, 1, 0, 0),
626 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
629 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
633 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
645 .cmd_rcgr = 0x17010,
661 .cmd_rcgr = 0x17140,
672 F(19200000, P_BI_TCXO, 1, 0, 0),
678 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
681 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
693 .cmd_rcgr = 0x17270,
709 .cmd_rcgr = 0x173a0,
725 .cmd_rcgr = 0x174d0,
741 .cmd_rcgr = 0x17600,
757 .cmd_rcgr = 0x17730,
773 .cmd_rcgr = 0x17860,
789 .cmd_rcgr = 0x18010,
805 .cmd_rcgr = 0x18140,
821 .cmd_rcgr = 0x18270,
837 .cmd_rcgr = 0x183a0,
853 .cmd_rcgr = 0x184d0,
869 .cmd_rcgr = 0x18600,
885 .cmd_rcgr = 0x18730,
901 .cmd_rcgr = 0x18860,
912 F(19200000, P_BI_TCXO, 1, 0, 0),
914 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
915 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
916 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
917 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
918 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
923 .cmd_rcgr = 0x7500c,
937 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
938 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
939 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
944 .cmd_rcgr = 0x7502c,
945 .mnd_width = 0,
959 F(19200000, P_BI_TCXO, 1, 0, 0),
960 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
961 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
962 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
963 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
968 .cmd_rcgr = 0x1400c,
984 F(19200000, P_BI_TCXO, 1, 0, 0),
985 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
986 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
987 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
992 .cmd_rcgr = 0x1600c,
1006 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1009 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1014 .cmd_rcgr = 0x77024,
1028 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1029 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1030 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1035 .cmd_rcgr = 0x7706c,
1036 .mnd_width = 0,
1049 .cmd_rcgr = 0x770a0,
1050 .mnd_width = 0,
1063 .cmd_rcgr = 0x77084,
1064 .mnd_width = 0,
1077 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1078 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1079 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1080 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1085 .cmd_rcgr = 0xf020,
1099 F(19200000, P_BI_TCXO, 1, 0, 0),
1104 .cmd_rcgr = 0xf038,
1105 .mnd_width = 0,
1118 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1119 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1124 .cmd_rcgr = 0x9e020,
1138 .cmd_rcgr = 0x9e038,
1139 .mnd_width = 0,
1152 .cmd_rcgr = 0xf064,
1153 .mnd_width = 0,
1166 .cmd_rcgr = 0x9e064,
1167 .mnd_width = 0,
1180 F(4800000, P_BI_TCXO, 4, 0, 0),
1181 F(19200000, P_BI_TCXO, 1, 0, 0),
1186 .cmd_rcgr = 0x3d02c,
1187 .mnd_width = 0,
1200 .reg = 0xf050,
1201 .shift = 0,
1215 .reg = 0x9e050,
1216 .shift = 0,
1230 .halt_reg = 0x8c004,
1233 .enable_reg = 0x8c004,
1234 .enable_mask = BIT(0),
1243 .halt_reg = 0x8c008,
1246 .enable_reg = 0x8c008,
1247 .enable_mask = BIT(0),
1256 .halt_reg = 0x6b080,
1258 .hwcg_reg = 0x6b080,
1261 .enable_reg = 0x52000,
1271 .halt_reg = 0x8d084,
1273 .hwcg_reg = 0x8d084,
1276 .enable_reg = 0x52000,
1286 .halt_reg = 0x90010,
1288 .hwcg_reg = 0x90010,
1291 .enable_reg = 0x52000,
1301 .halt_reg = 0x8d088,
1303 .hwcg_reg = 0x8d088,
1306 .enable_reg = 0x52008,
1316 .halt_reg = 0x770cc,
1318 .hwcg_reg = 0x770cc,
1321 .enable_reg = 0x770cc,
1322 .enable_mask = BIT(0),
1336 .halt_reg = 0xf080,
1338 .hwcg_reg = 0xf080,
1341 .enable_reg = 0xf080,
1342 .enable_mask = BIT(0),
1356 .halt_reg = 0x9e080,
1358 .hwcg_reg = 0x9e080,
1361 .enable_reg = 0x9e080,
1362 .enable_mask = BIT(0),
1376 .halt_reg = 0x26010,
1378 .hwcg_reg = 0x26010,
1381 .enable_reg = 0x26010,
1382 .enable_mask = BIT(0),
1391 .halt_reg = 0x2601c,
1393 .hwcg_reg = 0x2601c,
1396 .enable_reg = 0x2601c,
1397 .enable_mask = BIT(0),
1406 .halt_reg = 0xf07c,
1408 .hwcg_reg = 0xf07c,
1411 .enable_reg = 0xf07c,
1412 .enable_mask = BIT(0),
1426 .halt_reg = 0x9e07c,
1428 .hwcg_reg = 0x9e07c,
1431 .enable_reg = 0x9e07c,
1432 .enable_mask = BIT(0),
1446 .halt_reg = 0x71154,
1448 .hwcg_reg = 0x71154,
1451 .enable_reg = 0x71154,
1452 .enable_mask = BIT(0),
1461 .halt_reg = 0x8d080,
1463 .hwcg_reg = 0x8d080,
1466 .enable_reg = 0x52000,
1478 .enable_reg = 0x52000,
1493 .halt_reg = 0x2700c,
1495 .hwcg_reg = 0x2700c,
1498 .enable_reg = 0x2700c,
1499 .enable_mask = BIT(0),
1508 .halt_reg = 0x27014,
1510 .hwcg_reg = 0x27014,
1513 .enable_reg = 0x27014,
1514 .enable_mask = BIT(0),
1523 .halt_reg = 0x64000,
1526 .enable_reg = 0x64000,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x65000,
1544 .enable_reg = 0x65000,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x66000,
1562 .enable_reg = 0x66000,
1563 .enable_mask = BIT(0),
1579 .enable_reg = 0x52000,
1596 .enable_reg = 0x52000,
1611 .halt_reg = 0x8c014,
1614 .enable_reg = 0x8c014,
1615 .enable_mask = BIT(0),
1624 .halt_reg = 0x7100c,
1626 .hwcg_reg = 0x7100c,
1629 .enable_reg = 0x7100c,
1630 .enable_mask = BIT(0),
1639 .halt_reg = 0x71018,
1642 .enable_reg = 0x71018,
1643 .enable_mask = BIT(0),
1652 .halt_reg = 0x6b038,
1655 .enable_reg = 0x52000,
1670 .halt_reg = 0x8d038,
1673 .enable_reg = 0x52000,
1688 .halt_reg = 0x6b028,
1691 .enable_reg = 0x52008,
1706 .halt_reg = 0x6b024,
1708 .hwcg_reg = 0x6b024,
1711 .enable_reg = 0x52008,
1721 .halt_reg = 0x6b01c,
1724 .enable_reg = 0x52008,
1734 .halt_reg = 0x6b030,
1737 .enable_reg = 0x52008,
1752 .halt_reg = 0x6b014,
1755 .enable_reg = 0x52008,
1756 .enable_mask = BIT(0),
1765 .halt_reg = 0x6b010,
1768 .enable_reg = 0x52008,
1778 .halt_reg = 0x8d028,
1781 .enable_reg = 0x52000,
1796 .halt_reg = 0x8d024,
1798 .hwcg_reg = 0x8d024,
1801 .enable_reg = 0x52000,
1811 .halt_reg = 0x8d01c,
1814 .enable_reg = 0x52000,
1824 .halt_reg = 0x8d030,
1827 .enable_reg = 0x52000,
1842 .halt_reg = 0x8d014,
1845 .enable_reg = 0x52000,
1855 .halt_reg = 0x8d010,
1858 .enable_reg = 0x52000,
1868 .halt_reg = 0x90018,
1870 .hwcg_reg = 0x90018,
1873 .enable_reg = 0x52000,
1883 .halt_reg = 0x3300c,
1886 .enable_reg = 0x3300c,
1887 .enable_mask = BIT(0),
1901 .halt_reg = 0x33004,
1903 .hwcg_reg = 0x33004,
1906 .enable_reg = 0x33004,
1907 .enable_mask = BIT(0),
1916 .halt_reg = 0x33008,
1919 .enable_reg = 0x33008,
1920 .enable_mask = BIT(0),
1929 .halt_reg = 0x26008,
1931 .hwcg_reg = 0x26008,
1934 .enable_reg = 0x26008,
1935 .enable_mask = BIT(0),
1944 .halt_reg = 0x2600c,
1946 .hwcg_reg = 0x2600c,
1949 .enable_reg = 0x2600c,
1950 .enable_mask = BIT(0),
1959 .halt_reg = 0x27008,
1962 .enable_reg = 0x27008,
1963 .enable_mask = BIT(0),
1972 .halt_reg = 0x28008,
1974 .hwcg_reg = 0x28008,
1977 .enable_reg = 0x28008,
1978 .enable_mask = BIT(0),
1987 .halt_reg = 0x4b004,
1989 .hwcg_reg = 0x4b004,
1992 .enable_reg = 0x4b004,
1993 .enable_mask = BIT(0),
2002 .halt_reg = 0x4b008,
2005 .enable_reg = 0x4b008,
2006 .enable_mask = BIT(0),
2020 .halt_reg = 0x23008,
2023 .enable_reg = 0x52008,
2033 .halt_reg = 0x23000,
2036 .enable_reg = 0x52008,
2046 .halt_reg = 0x1700c,
2049 .enable_reg = 0x52008,
2064 .halt_reg = 0x1713c,
2067 .enable_reg = 0x52008,
2082 .halt_reg = 0x1726c,
2085 .enable_reg = 0x52008,
2100 .halt_reg = 0x1739c,
2103 .enable_reg = 0x52008,
2118 .halt_reg = 0x174cc,
2121 .enable_reg = 0x52008,
2136 .halt_reg = 0x175fc,
2139 .enable_reg = 0x52008,
2154 .halt_reg = 0x1772c,
2157 .enable_reg = 0x52008,
2172 .halt_reg = 0x1785c,
2175 .enable_reg = 0x52008,
2190 .halt_reg = 0x23140,
2193 .enable_reg = 0x52008,
2203 .halt_reg = 0x23138,
2206 .enable_reg = 0x52008,
2216 .halt_reg = 0x1800c,
2219 .enable_reg = 0x52008,
2234 .halt_reg = 0x1813c,
2237 .enable_reg = 0x52008,
2252 .halt_reg = 0x1826c,
2255 .enable_reg = 0x52008,
2270 .halt_reg = 0x1839c,
2273 .enable_reg = 0x52008,
2288 .halt_reg = 0x184cc,
2291 .enable_reg = 0x52008,
2306 .halt_reg = 0x185fc,
2309 .enable_reg = 0x52008,
2324 .halt_reg = 0x1872c,
2327 .enable_reg = 0x52000,
2342 .halt_reg = 0x1885c,
2345 .enable_reg = 0x52000,
2360 .halt_reg = 0x17004,
2362 .hwcg_reg = 0x17004,
2365 .enable_reg = 0x52008,
2375 .halt_reg = 0x17008,
2377 .hwcg_reg = 0x17008,
2380 .enable_reg = 0x52008,
2390 .halt_reg = 0x18004,
2392 .hwcg_reg = 0x18004,
2395 .enable_reg = 0x52008,
2405 .halt_reg = 0x18008,
2407 .hwcg_reg = 0x18008,
2410 .enable_reg = 0x52008,
2420 .halt_reg = 0x75004,
2423 .enable_reg = 0x75004,
2424 .enable_mask = BIT(0),
2433 .halt_reg = 0x75008,
2436 .enable_reg = 0x75008,
2437 .enable_mask = BIT(0),
2451 .halt_reg = 0x75024,
2453 .hwcg_reg = 0x75024,
2456 .enable_reg = 0x75024,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x14008,
2474 .enable_reg = 0x14008,
2475 .enable_mask = BIT(0),
2484 .halt_reg = 0x14004,
2487 .enable_reg = 0x14004,
2488 .enable_mask = BIT(0),
2502 .halt_reg = 0x16008,
2505 .enable_reg = 0x16008,
2506 .enable_mask = BIT(0),
2515 .halt_reg = 0x16004,
2518 .enable_reg = 0x16004,
2519 .enable_mask = BIT(0),
2533 .halt_reg = 0x9001c,
2536 .enable_reg = 0x9001c,
2537 .enable_mask = BIT(0),
2546 .halt_reg = 0x26024,
2548 .hwcg_reg = 0x26024,
2551 .enable_reg = 0x26024,
2552 .enable_mask = BIT(0),
2561 .halt_reg = 0x26018,
2563 .hwcg_reg = 0x26018,
2566 .enable_reg = 0x26018,
2567 .enable_mask = BIT(0),
2576 .halt_reg = 0x8c000,
2579 .enable_reg = 0x8c000,
2580 .enable_mask = BIT(0),
2589 .halt_reg = 0x77018,
2591 .hwcg_reg = 0x77018,
2594 .enable_reg = 0x77018,
2595 .enable_mask = BIT(0),
2604 .halt_reg = 0x77010,
2606 .hwcg_reg = 0x77010,
2609 .enable_reg = 0x77010,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x77064,
2626 .hwcg_reg = 0x77064,
2629 .enable_reg = 0x77064,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x7709c,
2646 .hwcg_reg = 0x7709c,
2649 .enable_reg = 0x7709c,
2650 .enable_mask = BIT(0),
2664 .halt_reg = 0x77020,
2667 .enable_reg = 0x77020,
2668 .enable_mask = BIT(0),
2682 .halt_reg = 0x770b8,
2685 .enable_reg = 0x770b8,
2686 .enable_mask = BIT(0),
2700 .halt_reg = 0x7701c,
2703 .enable_reg = 0x7701c,
2704 .enable_mask = BIT(0),
2718 .halt_reg = 0x7705c,
2720 .hwcg_reg = 0x7705c,
2723 .enable_reg = 0x7705c,
2724 .enable_mask = BIT(0),
2738 .halt_reg = 0xf010,
2741 .enable_reg = 0xf010,
2742 .enable_mask = BIT(0),
2756 .halt_reg = 0xf01c,
2759 .enable_reg = 0xf01c,
2760 .enable_mask = BIT(0),
2774 .halt_reg = 0xf018,
2777 .enable_reg = 0xf018,
2778 .enable_mask = BIT(0),
2787 .halt_reg = 0x9e010,
2790 .enable_reg = 0x9e010,
2791 .enable_mask = BIT(0),
2805 .halt_reg = 0x9e01c,
2808 .enable_reg = 0x9e01c,
2809 .enable_mask = BIT(0),
2823 .halt_reg = 0x9e018,
2826 .enable_reg = 0x9e018,
2827 .enable_mask = BIT(0),
2836 .halt_reg = 0xf054,
2839 .enable_reg = 0xf054,
2840 .enable_mask = BIT(0),
2854 .halt_reg = 0xf058,
2857 .enable_reg = 0xf058,
2858 .enable_mask = BIT(0),
2872 .halt_reg = 0xf05c,
2874 .hwcg_reg = 0xf05c,
2877 .enable_reg = 0xf05c,
2878 .enable_mask = BIT(0),
2892 .halt_reg = 0x47020,
2895 .enable_reg = 0x47020,
2896 .enable_mask = BIT(0),
2904 .halt_reg = 0x8a000,
2907 .enable_reg = 0x8a000,
2908 .enable_mask = BIT(0),
2917 .halt_reg = 0x8a004,
2920 .enable_reg = 0x8a004,
2921 .enable_mask = BIT(0),
2930 .halt_reg = 0x8a154,
2933 .enable_reg = 0x8a154,
2934 .enable_mask = BIT(0),
2943 .halt_reg = 0x8a158,
2946 .enable_reg = 0x8a158,
2947 .enable_mask = BIT(0),
2956 .reg = 0x8a2a4,
2957 .shift = 0,
2971 .halt_reg = 0x9e054,
2974 .enable_reg = 0x9e054,
2975 .enable_mask = BIT(0),
2989 .halt_reg = 0x9e058,
2992 .enable_reg = 0x9e058,
2993 .enable_mask = BIT(0),
3007 .halt_reg = 0x9e05c,
3009 .hwcg_reg = 0x9e05c,
3012 .enable_reg = 0x9e05c,
3013 .enable_mask = BIT(0),
3027 .halt_reg = 0x2800c,
3029 .hwcg_reg = 0x2800c,
3032 .enable_reg = 0x2800c,
3033 .enable_mask = BIT(0),
3042 .halt_reg = 0x28010,
3044 .hwcg_reg = 0x28010,
3047 .enable_reg = 0x28010,
3048 .enable_mask = BIT(0),
3057 .halt_reg = 0x9d154,
3060 .enable_reg = 0x9d154,
3061 .enable_mask = BIT(0),
3070 .halt_reg = 0x9d158,
3073 .enable_reg = 0x9d158,
3074 .enable_mask = BIT(0),
3083 .halt_reg = 0x9d16c,
3086 .enable_reg = 0x9d16c,
3087 .enable_mask = BIT(0),
3096 .gdscr = 0x6b004,
3105 .gdscr = 0x8d004,
3114 .gdscr = 0x77004,
3123 .gdscr = 0xf004,
3132 .gdscr = 0x9e004,
3141 .gdscr = 0x7d050,
3150 .gdscr = 0x7d058,
3159 .gdscr = 0x7d054,
3168 .gdscr = 0x7d05c,
3177 .gdscr = 0x7d060,
3386 [GCC_PCIE_0_BCR] = { 0x6b000 },
3387 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3388 [GCC_PCIE_1_BCR] = { 0x8d000 },
3389 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3390 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3391 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3392 [GCC_SDCC1_BCR] = { 0x75000 },
3393 [GCC_SDCC2_BCR] = { 0x14000 },
3394 [GCC_SDCC4_BCR] = { 0x16000 },
3395 [GCC_UFS_PHY_BCR] = { 0x77000 },
3396 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3397 [GCC_USB30_SEC_BCR] = { 0x9e000 },
3398 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3399 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3400 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3401 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3427 .max_register = 0x9f128,
3461 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3462 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); in gcc_sc7280_probe()
3463 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3464 regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); in gcc_sc7280_probe()
3465 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3466 regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); in gcc_sc7280_probe()
3467 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3468 regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); in gcc_sc7280_probe()