Lines Matching +full:0 +full:x18140
65 #size-cells = <0>;
68 cpu@0 {
71 reg = <0>;
72 clocks = <&cpuclk 0>;
103 * MV78460 has 4 PCIe units Gen2.0: Two units can be
116 bus-range = <0x00 0xff>;
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
129 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
130 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
131 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
132 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
133 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
134 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
135 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
136 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
138 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
139 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
140 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
141 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
142 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
143 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
144 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
145 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
147 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
148 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
150 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
151 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
153 pcie1: pcie@1,0 {
155 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
156 reg = <0x0800 0 0 0 0>;
160 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
161 0x81000000 0 0 0x81000000 0x1 0 1 0>;
162 bus-range = <0x00 0xff>;
163 interrupt-map-mask = <0 0 0 0>;
164 interrupt-map = <0 0 0 0 &mpic 58>;
165 marvell,pcie-port = <0>;
166 marvell,pcie-lane = <0>;
171 pcie2: pcie@2,0 {
173 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
174 reg = <0x1000 0 0 0 0>;
178 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
179 0x81000000 0 0 0x81000000 0x2 0 1 0>;
180 bus-range = <0x00 0xff>;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 59>;
183 marvell,pcie-port = <0>;
189 pcie3: pcie@3,0 {
191 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
192 reg = <0x1800 0 0 0 0>;
196 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
197 0x81000000 0 0 0x81000000 0x3 0 1 0>;
198 bus-range = <0x00 0xff>;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 60>;
201 marvell,pcie-port = <0>;
207 pcie4: pcie@4,0 {
209 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
210 reg = <0x2000 0 0 0 0>;
214 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
215 0x81000000 0 0 0x81000000 0x4 0 1 0>;
216 bus-range = <0x00 0xff>;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 61>;
219 marvell,pcie-port = <0>;
225 pcie5: pcie@5,0 {
227 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
228 reg = <0x2800 0 0 0 0>;
232 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
233 0x81000000 0 0 0x81000000 0x5 0 1 0>;
234 bus-range = <0x00 0xff>;
235 interrupt-map-mask = <0 0 0 0>;
236 interrupt-map = <0 0 0 0 &mpic 62>;
238 marvell,pcie-lane = <0>;
243 pcie6: pcie@6,0 {
245 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
246 reg = <0x3000 0 0 0 0>;
250 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
251 0x81000000 0 0 0x81000000 0x6 0 1 0>;
252 bus-range = <0x00 0xff>;
253 interrupt-map-mask = <0 0 0 0>;
254 interrupt-map = <0 0 0 0 &mpic 63>;
261 pcie7: pcie@7,0 {
263 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
264 reg = <0x3800 0 0 0 0>;
268 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
269 0x81000000 0 0 0x81000000 0x7 0 1 0>;
270 bus-range = <0x00 0xff>;
271 interrupt-map-mask = <0 0 0 0>;
272 interrupt-map = <0 0 0 0 &mpic 64>;
279 pcie8: pcie@8,0 {
281 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
282 reg = <0x4000 0 0 0 0>;
286 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
287 0x81000000 0 0 0x81000000 0x8 0 1 0>;
288 bus-range = <0x00 0xff>;
289 interrupt-map-mask = <0 0 0 0>;
290 interrupt-map = <0 0 0 0 &mpic 65>;
297 pcie9: pcie@9,0 {
299 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
300 reg = <0x4800 0 0 0 0>;
304 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
305 0x81000000 0 0 0x81000000 0x9 0 1 0>;
306 bus-range = <0x00 0xff>;
307 interrupt-map-mask = <0 0 0 0>;
308 interrupt-map = <0 0 0 0 &mpic 99>;
310 marvell,pcie-lane = <0>;
315 pcie10: pcie@a,0 {
317 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
318 reg = <0x5000 0 0 0 0>;
322 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
323 0x81000000 0 0 0x81000000 0xa 0 1 0>;
324 bus-range = <0x00 0xff>;
325 interrupt-map-mask = <0 0 0 0>;
326 interrupt-map = <0 0 0 0 &mpic 103>;
328 marvell,pcie-lane = <0>;
337 reg = <0x18100 0x40>;
348 reg = <0x18140 0x40>;
359 reg = <0x18180 0x40>;
370 reg = <0x34000 0x4000>;