Lines Matching +full:0 +full:x18140
36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
127 { P_BI_TCXO, 0 },
141 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
159 { P_BI_TCXO, 0 },
175 { P_BI_TCXO, 0 },
189 F(19200000, P_BI_TCXO, 1, 0, 0),
194 .cmd_rcgr = 0x48010,
195 .mnd_width = 0,
209 F(19200000, P_BI_TCXO, 1, 0, 0),
210 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
211 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
212 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
213 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
218 .cmd_rcgr = 0x64004,
232 .cmd_rcgr = 0x65004,
246 .cmd_rcgr = 0x66004,
260 F(9600000, P_BI_TCXO, 2, 0, 0),
261 F(19200000, P_BI_TCXO, 1, 0, 0),
266 .cmd_rcgr = 0x6b038,
280 .cmd_rcgr = 0x8d038,
294 .cmd_rcgr = 0x6038,
308 F(19200000, P_BI_TCXO, 1, 0, 0),
309 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
314 .cmd_rcgr = 0x6f014,
315 .mnd_width = 0,
328 F(9600000, P_BI_TCXO, 2, 0, 0),
329 F(19200000, P_BI_TCXO, 1, 0, 0),
330 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
335 .cmd_rcgr = 0x33010,
336 .mnd_width = 0,
351 F(19200000, P_BI_TCXO, 1, 0, 0),
355 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
357 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
360 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
364 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
376 .cmd_rcgr = 0x17010,
392 .cmd_rcgr = 0x17140,
403 F(19200000, P_BI_TCXO, 1, 0, 0),
407 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
409 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
412 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
424 .cmd_rcgr = 0x17270,
440 .cmd_rcgr = 0x173a0,
456 .cmd_rcgr = 0x174d0,
472 .cmd_rcgr = 0x17600,
488 .cmd_rcgr = 0x17730,
504 .cmd_rcgr = 0x17860,
520 .cmd_rcgr = 0x18010,
536 .cmd_rcgr = 0x18140,
552 .cmd_rcgr = 0x18270,
568 .cmd_rcgr = 0x183a0,
584 .cmd_rcgr = 0x184d0,
600 .cmd_rcgr = 0x18600,
616 .cmd_rcgr = 0x1e010,
632 .cmd_rcgr = 0x1e140,
648 .cmd_rcgr = 0x1e270,
664 .cmd_rcgr = 0x1e3a0,
680 .cmd_rcgr = 0x1e4d0,
696 .cmd_rcgr = 0x1e600,
706 F(19200000, P_BI_TCXO, 1, 0, 0),
707 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
708 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
709 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
710 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
715 .cmd_rcgr = 0x1400c,
731 F(19200000, P_BI_TCXO, 1, 0, 0),
732 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
733 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
734 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
739 .cmd_rcgr = 0x1600c,
758 .cmd_rcgr = 0x36010,
772 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
773 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
774 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
775 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
780 .cmd_rcgr = 0x75024,
794 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
795 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
796 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
797 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
802 .cmd_rcgr = 0x7506c,
803 .mnd_width = 0,
816 F(19200000, P_BI_TCXO, 1, 0, 0),
821 .cmd_rcgr = 0x750a0,
822 .mnd_width = 0,
835 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
836 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
837 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
842 .cmd_rcgr = 0x75084,
843 .mnd_width = 0,
856 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
857 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
858 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
859 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
860 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
865 .cmd_rcgr = 0x77024,
879 .cmd_rcgr = 0x7706c,
880 .mnd_width = 0,
893 .cmd_rcgr = 0x770a0,
894 .mnd_width = 0,
907 .cmd_rcgr = 0x77084,
908 .mnd_width = 0,
921 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
922 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
923 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
924 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
925 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
930 .cmd_rcgr = 0xf020,
944 .cmd_rcgr = 0xf038,
945 .mnd_width = 0,
958 .cmd_rcgr = 0x10020,
972 .cmd_rcgr = 0x10038,
973 .mnd_width = 0,
986 .cmd_rcgr = 0xf064,
987 .mnd_width = 0,
1000 .cmd_rcgr = 0x10064,
1001 .mnd_width = 0,
1014 .reg = 0x48028,
1015 .shift = 0,
1029 .reg = 0xf050,
1030 .shift = 0,
1044 .reg = 0x10050,
1045 .shift = 0,
1059 .halt_reg = 0x9000c,
1062 .enable_reg = 0x9000c,
1063 .enable_mask = BIT(0),
1072 .halt_reg = 0x750cc,
1074 .hwcg_reg = 0x750cc,
1077 .enable_reg = 0x750cc,
1078 .enable_mask = BIT(0),
1092 .halt_reg = 0x770cc,
1094 .hwcg_reg = 0x770cc,
1097 .enable_reg = 0x770cc,
1098 .enable_mask = BIT(0),
1112 .halt_reg = 0xf080,
1115 .enable_reg = 0xf080,
1116 .enable_mask = BIT(0),
1130 .halt_reg = 0x10080,
1133 .enable_reg = 0x10080,
1134 .enable_mask = BIT(0),
1148 .halt_reg = 0x38004,
1150 .hwcg_reg = 0x38004,
1153 .enable_reg = 0x52000,
1163 .halt_reg = 0xb02c,
1166 .enable_reg = 0xb02c,
1167 .enable_mask = BIT(0),
1176 .halt_reg = 0xb030,
1179 .enable_reg = 0xb030,
1180 .enable_mask = BIT(0),
1189 .halt_reg = 0xb040,
1192 .enable_reg = 0xb040,
1193 .enable_mask = BIT(0),
1202 .halt_reg = 0xf07c,
1205 .enable_reg = 0xf07c,
1206 .enable_mask = BIT(0),
1220 .halt_reg = 0x1007c,
1223 .enable_reg = 0x1007c,
1224 .enable_mask = BIT(0),
1238 .halt_reg = 0x48000,
1241 .enable_reg = 0x52000,
1256 .halt_reg = 0x48004,
1259 .enable_reg = 0x48004,
1260 .enable_mask = BIT(0),
1269 .halt_reg = 0x71154,
1272 .enable_reg = 0x71154,
1273 .enable_mask = BIT(0),
1282 .halt_reg = 0x8d058,
1285 .enable_reg = 0x8d058,
1286 .enable_mask = BIT(0),
1295 .halt_reg = 0xb034,
1298 .enable_reg = 0xb034,
1299 .enable_mask = BIT(0),
1308 .halt_reg = 0xb038,
1311 .enable_reg = 0xb038,
1312 .enable_mask = BIT(0),
1321 .halt_reg = 0xb044,
1324 .enable_reg = 0xb044,
1325 .enable_mask = BIT(0),
1334 .halt_reg = 0x64000,
1337 .enable_reg = 0x64000,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x65000,
1355 .enable_reg = 0x65000,
1356 .enable_mask = BIT(0),
1370 .halt_reg = 0x66000,
1373 .enable_reg = 0x66000,
1374 .enable_mask = BIT(0),
1390 .enable_reg = 0x52000,
1407 .enable_reg = 0x52000,
1422 .halt_reg = 0x8c014,
1425 .enable_reg = 0x8c014,
1426 .enable_mask = BIT(0),
1435 .halt_reg = 0x7100c,
1438 .enable_reg = 0x7100c,
1439 .enable_mask = BIT(0),
1448 .halt_reg = 0x71018,
1451 .enable_reg = 0x71018,
1452 .enable_mask = BIT(0),
1461 .halt_reg = 0x4d008,
1464 .enable_reg = 0x4d008,
1465 .enable_mask = BIT(0),
1474 .halt_reg = 0x73008,
1477 .enable_reg = 0x73008,
1478 .enable_mask = BIT(0),
1487 .halt_reg = 0x73004,
1490 .enable_reg = 0x73004,
1491 .enable_mask = BIT(0),
1500 .halt_reg = 0x4d004,
1502 .hwcg_reg = 0x4d004,
1505 .enable_reg = 0x4d004,
1506 .enable_mask = BIT(0),
1515 .halt_reg = 0x4d00c,
1518 .enable_reg = 0x4d00c,
1519 .enable_mask = BIT(0),
1530 .enable_reg = 0x52000,
1547 .enable_reg = 0x52000,
1562 .halt_reg = 0x6f02c,
1565 .enable_reg = 0x6f02c,
1566 .enable_mask = BIT(0),
1580 .halt_reg = 0x6f030,
1583 .enable_reg = 0x6f030,
1584 .enable_mask = BIT(0),
1598 .halt_reg = 0x6f034,
1601 .enable_reg = 0x6f034,
1602 .enable_mask = BIT(0),
1616 .halt_reg = 0x6b028,
1619 .enable_reg = 0x52008,
1634 .halt_reg = 0x6b024,
1636 .hwcg_reg = 0x6b024,
1639 .enable_reg = 0x52008,
1649 .halt_reg = 0x6b01c,
1652 .enable_reg = 0x52008,
1662 .halt_reg = 0x6b02c,
1665 .enable_reg = 0x52008,
1675 .halt_reg = 0x6b014,
1677 .hwcg_reg = 0x6b014,
1680 .enable_reg = 0x52008,
1681 .enable_mask = BIT(0),
1690 .halt_reg = 0x6b010,
1693 .enable_reg = 0x52008,
1703 .halt_reg = 0x8d028,
1706 .enable_reg = 0x52000,
1721 .halt_reg = 0x8d024,
1723 .hwcg_reg = 0x8d024,
1726 .enable_reg = 0x52000,
1736 .halt_reg = 0x8d01c,
1739 .enable_reg = 0x52000,
1749 .halt_reg = 0x8d02c,
1752 .enable_reg = 0x52000,
1762 .halt_reg = 0x8d014,
1764 .hwcg_reg = 0x8d014,
1767 .enable_reg = 0x52000,
1777 .halt_reg = 0x8d010,
1780 .enable_reg = 0x52000,
1790 .halt_reg = 0x6028,
1793 .enable_reg = 0x52010,
1808 .halt_reg = 0x6024,
1810 .hwcg_reg = 0x6024,
1813 .enable_reg = 0x52010,
1823 .halt_reg = 0x601c,
1826 .enable_reg = 0x52010,
1836 .halt_reg = 0x602c,
1839 .enable_reg = 0x52010,
1849 .halt_reg = 0x6014,
1851 .hwcg_reg = 0x6014,
1854 .enable_reg = 0x52010,
1864 .halt_reg = 0x6010,
1867 .enable_reg = 0x52010,
1877 .halt_reg = 0x8c00c,
1880 .enable_reg = 0x8c00c,
1881 .enable_mask = BIT(0),
1890 .halt_reg = 0x6f004,
1893 .enable_reg = 0x6f004,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x8c004,
1911 .enable_reg = 0x8c004,
1912 .enable_mask = BIT(0),
1921 .halt_reg = 0x8c008,
1924 .enable_reg = 0x8c008,
1925 .enable_mask = BIT(0),
1934 .halt_reg = 0x3300c,
1937 .enable_reg = 0x3300c,
1938 .enable_mask = BIT(0),
1952 .halt_reg = 0x33004,
1954 .hwcg_reg = 0x33004,
1957 .enable_reg = 0x33004,
1958 .enable_mask = BIT(0),
1967 .halt_reg = 0x33008,
1970 .enable_reg = 0x33008,
1971 .enable_mask = BIT(0),
1980 .halt_reg = 0x34004,
1983 .enable_reg = 0x52000,
1993 .halt_reg = 0xb018,
1995 .hwcg_reg = 0xb018,
1998 .enable_reg = 0xb018,
1999 .enable_mask = BIT(0),
2008 .halt_reg = 0xb01c,
2010 .hwcg_reg = 0xb01c,
2013 .enable_reg = 0xb01c,
2014 .enable_mask = BIT(0),
2023 .halt_reg = 0xb020,
2025 .hwcg_reg = 0xb020,
2028 .enable_reg = 0xb020,
2029 .enable_mask = BIT(0),
2038 .halt_reg = 0xb010,
2040 .hwcg_reg = 0xb010,
2043 .enable_reg = 0xb010,
2044 .enable_mask = BIT(0),
2053 .halt_reg = 0xb014,
2055 .hwcg_reg = 0xb014,
2058 .enable_reg = 0xb014,
2059 .enable_mask = BIT(0),
2068 .halt_reg = 0x23008,
2071 .enable_reg = 0x52008,
2081 .halt_reg = 0x23000,
2084 .enable_reg = 0x52008,
2094 .halt_reg = 0x1700c,
2097 .enable_reg = 0x52008,
2112 .halt_reg = 0x1713c,
2115 .enable_reg = 0x52008,
2130 .halt_reg = 0x1726c,
2133 .enable_reg = 0x52008,
2148 .halt_reg = 0x1739c,
2151 .enable_reg = 0x52008,
2166 .halt_reg = 0x174cc,
2169 .enable_reg = 0x52008,
2184 .halt_reg = 0x175fc,
2187 .enable_reg = 0x52008,
2202 .halt_reg = 0x1772c,
2205 .enable_reg = 0x52008,
2220 .halt_reg = 0x1785c,
2223 .enable_reg = 0x52008,
2238 .halt_reg = 0x23140,
2241 .enable_reg = 0x52008,
2251 .halt_reg = 0x23138,
2254 .enable_reg = 0x52008,
2264 .halt_reg = 0x1800c,
2267 .enable_reg = 0x52008,
2282 .halt_reg = 0x1813c,
2285 .enable_reg = 0x52008,
2300 .halt_reg = 0x1826c,
2303 .enable_reg = 0x52008,
2318 .halt_reg = 0x1839c,
2321 .enable_reg = 0x52008,
2336 .halt_reg = 0x184cc,
2339 .enable_reg = 0x52008,
2354 .halt_reg = 0x185fc,
2357 .enable_reg = 0x52008,
2372 .halt_reg = 0x23278,
2375 .enable_reg = 0x52010,
2385 .halt_reg = 0x23270,
2388 .enable_reg = 0x52010,
2389 .enable_mask = BIT(0),
2398 .halt_reg = 0x1e00c,
2401 .enable_reg = 0x52010,
2416 .halt_reg = 0x1e13c,
2419 .enable_reg = 0x52010,
2434 .halt_reg = 0x1e26c,
2437 .enable_reg = 0x52010,
2452 .halt_reg = 0x1e39c,
2455 .enable_reg = 0x52010,
2470 .halt_reg = 0x1e4cc,
2473 .enable_reg = 0x52010,
2488 .halt_reg = 0x1e5fc,
2491 .enable_reg = 0x52010,
2506 .halt_reg = 0x17004,
2509 .enable_reg = 0x52008,
2519 .halt_reg = 0x17008,
2521 .hwcg_reg = 0x17008,
2524 .enable_reg = 0x52008,
2534 .halt_reg = 0x18004,
2537 .enable_reg = 0x52008,
2547 .halt_reg = 0x18008,
2549 .hwcg_reg = 0x18008,
2552 .enable_reg = 0x52008,
2562 .halt_reg = 0x1e004,
2565 .enable_reg = 0x52010,
2575 .halt_reg = 0x1e008,
2577 .hwcg_reg = 0x1e008,
2580 .enable_reg = 0x52010,
2590 .halt_reg = 0x14008,
2593 .enable_reg = 0x14008,
2594 .enable_mask = BIT(0),
2603 .halt_reg = 0x14004,
2606 .enable_reg = 0x14004,
2607 .enable_mask = BIT(0),
2621 .halt_reg = 0x16008,
2624 .enable_reg = 0x16008,
2625 .enable_mask = BIT(0),
2634 .halt_reg = 0x16004,
2637 .enable_reg = 0x16004,
2638 .enable_mask = BIT(0),
2652 .halt_reg = 0x36004,
2655 .enable_reg = 0x36004,
2656 .enable_mask = BIT(0),
2665 .halt_reg = 0x3600c,
2668 .enable_reg = 0x3600c,
2669 .enable_mask = BIT(0),
2678 .halt_reg = 0x36008,
2681 .enable_reg = 0x36008,
2682 .enable_mask = BIT(0),
2696 .halt_reg = 0x8c000,
2699 .enable_reg = 0x8c000,
2700 .enable_mask = BIT(0),
2709 .halt_reg = 0x75018,
2711 .hwcg_reg = 0x75018,
2714 .enable_reg = 0x75018,
2715 .enable_mask = BIT(0),
2724 .halt_reg = 0x75010,
2726 .hwcg_reg = 0x75010,
2729 .enable_reg = 0x75010,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x75064,
2746 .hwcg_reg = 0x75064,
2749 .enable_reg = 0x75064,
2750 .enable_mask = BIT(0),
2764 .halt_reg = 0x7509c,
2766 .hwcg_reg = 0x7509c,
2769 .enable_reg = 0x7509c,
2770 .enable_mask = BIT(0),
2784 .halt_reg = 0x75020,
2787 .enable_reg = 0x75020,
2788 .enable_mask = BIT(0),
2797 .halt_reg = 0x750b8,
2800 .enable_reg = 0x750b8,
2801 .enable_mask = BIT(0),
2810 .halt_reg = 0x7501c,
2813 .enable_reg = 0x7501c,
2814 .enable_mask = BIT(0),
2823 .halt_reg = 0x7505c,
2825 .hwcg_reg = 0x7505c,
2828 .enable_reg = 0x7505c,
2829 .enable_mask = BIT(0),
2843 .halt_reg = 0x77018,
2845 .hwcg_reg = 0x77018,
2848 .enable_reg = 0x77018,
2849 .enable_mask = BIT(0),
2858 .halt_reg = 0x77010,
2860 .hwcg_reg = 0x77010,
2863 .enable_reg = 0x77010,
2864 .enable_mask = BIT(0),
2878 .halt_reg = 0x77064,
2880 .hwcg_reg = 0x77064,
2883 .enable_reg = 0x77064,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0x7709c,
2900 .hwcg_reg = 0x7709c,
2903 .enable_reg = 0x7709c,
2904 .enable_mask = BIT(0),
2918 .halt_reg = 0x77020,
2921 .enable_reg = 0x77020,
2922 .enable_mask = BIT(0),
2931 .halt_reg = 0x770b8,
2934 .enable_reg = 0x770b8,
2935 .enable_mask = BIT(0),
2944 .halt_reg = 0x7701c,
2947 .enable_reg = 0x7701c,
2948 .enable_mask = BIT(0),
2957 .halt_reg = 0x7705c,
2959 .hwcg_reg = 0x7705c,
2962 .enable_reg = 0x7705c,
2963 .enable_mask = BIT(0),
2977 .halt_reg = 0xf010,
2980 .enable_reg = 0xf010,
2981 .enable_mask = BIT(0),
2995 .halt_reg = 0xf01c,
2998 .enable_reg = 0xf01c,
2999 .enable_mask = BIT(0),
3013 .halt_reg = 0xf018,
3016 .enable_reg = 0xf018,
3017 .enable_mask = BIT(0),
3026 .halt_reg = 0x10010,
3029 .enable_reg = 0x10010,
3030 .enable_mask = BIT(0),
3044 .halt_reg = 0x1001c,
3047 .enable_reg = 0x1001c,
3048 .enable_mask = BIT(0),
3062 .halt_reg = 0x10018,
3065 .enable_reg = 0x10018,
3066 .enable_mask = BIT(0),
3075 .halt_reg = 0xf054,
3078 .enable_reg = 0xf054,
3079 .enable_mask = BIT(0),
3093 .halt_reg = 0xf058,
3096 .enable_reg = 0xf058,
3097 .enable_mask = BIT(0),
3111 .halt_reg = 0xf05c,
3114 .enable_reg = 0xf05c,
3115 .enable_mask = BIT(0),
3124 .halt_reg = 0x8c010,
3127 .enable_reg = 0x8c010,
3128 .enable_mask = BIT(0),
3137 .halt_reg = 0x10054,
3140 .enable_reg = 0x10054,
3141 .enable_mask = BIT(0),
3155 .halt_reg = 0x10058,
3158 .enable_reg = 0x10058,
3159 .enable_mask = BIT(0),
3173 .halt_reg = 0x1005c,
3176 .enable_reg = 0x1005c,
3177 .enable_mask = BIT(0),
3186 .halt_reg = 0xb024,
3189 .enable_reg = 0xb024,
3190 .enable_mask = BIT(0),
3199 .halt_reg = 0xb028,
3202 .enable_reg = 0xb028,
3203 .enable_mask = BIT(0),
3212 .halt_reg = 0xb03c,
3215 .enable_reg = 0xb03c,
3216 .enable_mask = BIT(0),
3225 .gdscr = 0x6b004,
3233 .gdscr = 0x8d004,
3241 .gdscr = 0x6004,
3249 .gdscr = 0x75004,
3257 .gdscr = 0x77004,
3265 .gdscr = 0xf004,
3273 .gdscr = 0x10004,
3281 .gdscr = 0x7d050,
3290 .gdscr = 0x7d058,
3299 .gdscr = 0x7d054,
3308 .gdscr = 0x7d06c,
3536 [GCC_GPU_BCR] = { 0x71000 },
3537 [GCC_MMSS_BCR] = { 0xb000 },
3538 [GCC_NPU_BWMON_BCR] = { 0x73000 },
3539 [GCC_NPU_BCR] = { 0x4d000 },
3540 [GCC_PCIE_0_BCR] = { 0x6b000 },
3541 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3542 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3543 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3544 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3545 [GCC_PCIE_1_BCR] = { 0x8d000 },
3546 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3547 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3548 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3549 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3550 [GCC_PCIE_2_BCR] = { 0x6000 },
3551 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
3552 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
3553 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
3554 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
3555 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3556 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3557 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3558 [GCC_PDM_BCR] = { 0x33000 },
3559 [GCC_PRNG_BCR] = { 0x34000 },
3560 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3561 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3562 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3563 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3564 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3565 [GCC_SDCC2_BCR] = { 0x14000 },
3566 [GCC_SDCC4_BCR] = { 0x16000 },
3567 [GCC_TSIF_BCR] = { 0x36000 },
3568 [GCC_UFS_CARD_BCR] = { 0x75000 },
3569 [GCC_UFS_PHY_BCR] = { 0x77000 },
3570 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3571 [GCC_USB30_SEC_BCR] = { 0x10000 },
3572 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3573 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3574 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3575 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3576 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3577 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3578 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3579 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
3580 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
3610 .max_register = 0x9c100,
3643 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8250_probe()
3644 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8250_probe()
3652 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3653 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); in gcc_sm8250_probe()
3654 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3655 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3656 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3657 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); in gcc_sm8250_probe()