/openbmc/linux/drivers/net/phy/ |
H A D | dp83867.c | 443 phydev_err(phydev, in dp83867_set_downshift() 518 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg() 526 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg() 571 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); in dp83867_of_init_io_impedance() 600 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init() 620 phydev_err(phydev, in dp83867_of_init() 630 phydev_err(phydev, in dp83867_of_init() 653 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init() 664 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
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H A D | nxp-c45-tja11xx.c | 324 phydev_err(phydev, "Trying to read a reg field of size 0.\n"); in nxp_c45_read_reg_field() 349 phydev_err(phydev, "Trying to write a reg field of size 0.\n"); in nxp_c45_write_reg_field() 366 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_set_reg_field() 377 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_clear_reg_field() 1398 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay() 1403 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay() 1492 phydev_err(phydev, in nxp_c45_get_delays() 1508 phydev_err(phydev, in nxp_c45_get_delays() 1527 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode() 1538 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode() [all …]
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H A D | dp83869.c | 351 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol() 368 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol() 378 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol() 388 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol() 460 phydev_err(phydev, in dp83869_set_downshift() 701 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); in dp83869_configure_mode()
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H A D | cortina.c | 68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
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H A D | mxl-gpy.c | 341 phydev_err(phydev, "Error: MDIO register access failed: %d\n", in gpy_2500basex_chk() 363 phydev_err(phydev, "Error: MMD register access failed: %d\n", in gpy_sgmii_aneg_en() 529 phydev_err(phydev, in gpy_update_interface() 548 phydev_err(phydev, in gpy_update_interface()
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H A D | at803x.c | 672 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators() 678 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators() 754 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt() 762 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt() 784 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt() 823 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt() 842 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at803x_parse_dt()
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H A D | phy_device.c | 626 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module() 997 phydev_err(phydev, "failed to initialize\n"); in phy_device_register() 1003 phydev_err(phydev, "failed to add\n"); in phy_device_register() 1451 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct() 1470 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct() 1515 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct() 2412 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa() 2414 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa() 2969 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay() 2991 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
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H A D | rockchip.c | 116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
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H A D | microchip_t1s.c | 233 phydev_err(phydev, "PHY reset failed\n"); in lan867x_revb1_config_init()
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H A D | micrel.c | 523 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led() 542 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable() 562 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable() 576 phydev_err(phydev, in kszphy_config_reset() 1156 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init() 1964 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_parse_led_mode() 2097 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe() 2389 phydev_err(phydev, "Error: phy_write has returned error %d\n", in lanphy_write_page_reg() 3289 phydev_err(phydev, "ptp_clock_register failed %lu\n", in lan8814_ptp_probe_once() 4688 phydev_err(phydev, "ptp_clock_register failed: %lu\n", in lan8841_probe()
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H A D | adin.c | 461 phydev_err(phydev, "invalid adi,phy-output-clock\n"); in adin_config_clk_out() 568 phydev_err(phydev, in adin_cl45_to_adin_reg()
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H A D | aquantia_main.c | 228 phydev_err(phydev, "Reading HW Statistics failed for %s\n", in aqr107_get_stats() 673 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); in aqr107_wait_processor_intensive_op()
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H A D | mediatek-ge-soc.c | 347 phydev_err(phydev, "Calibration cycle timeout\n"); in cal_cycle() 1063 phydev_err(phydev, "cal %d failed\n", cal_item); in start_cal() 1090 phydev_err(phydev, "invalid efuse data\n"); in mt798x_phy_calibration()
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H A D | phy.c | 524 phydev_err(phydev, "Error while aborting cable test"); in phy_abort_cable_test() 1223 phydev_err(phydev, "PHY-device data unsafe context\n"); in phy_process_error()
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H A D | motorcomm.c | 1144 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in ytphy_utp_read_lpa() 1146 phydev_err(phydev, "Master/Slave resolution failed\n"); in ytphy_utp_read_lpa()
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H A D | marvell10g.c | 808 phydev_err(phydev, "MACTYPE configuration invalid\n"); in mv3310_config_init()
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H A D | marvell.c | 2055 phydev_err(phydev, "Timeout while waiting for cable test to finish\n"); in marvell_vct5_wait_complete()
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/openbmc/linux/net/ethtool/ |
H A D | cabletest.c | 51 phydev_err(phydev, "%s: Error %pe\n", __func__, ERR_PTR(err)); in ethnl_cable_test_started()
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/openbmc/linux/include/linux/ |
H A D | phy.h | 1254 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1353 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1777 #define phydev_err(_phydev, format, args...) \ macro
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/openbmc/linux/drivers/net/phy/mscc/ |
H A D | mscc_main.c | 264 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set() 423 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
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H A D | mscc_ptp.c | 1570 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n", in vsc8584_ptp_probe()
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