1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/bitfield.h>
11 #include <linux/hwmon.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/polynomial.h>
15 #include <linux/property.h>
16 #include <linux/netdevice.h>
17
18 /* PHY ID */
19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21 #define PHY_ID_GPY2xx 0x67C9DC00
22 #define PHY_ID_GPY115B 0x67C9DF00
23 #define PHY_ID_GPY115C 0x67C9DF10
24 #define PHY_ID_GPY211B 0x67C9DE08
25 #define PHY_ID_GPY211C 0x67C9DE10
26 #define PHY_ID_GPY212B 0x67C9DE09
27 #define PHY_ID_GPY212C 0x67C9DE20
28 #define PHY_ID_GPY215B 0x67C9DF04
29 #define PHY_ID_GPY215C 0x67C9DF20
30 #define PHY_ID_GPY241B 0x67C9DE40
31 #define PHY_ID_GPY241BM 0x67C9DE80
32 #define PHY_ID_GPY245B 0x67C9DEC0
33
34 #define PHY_CTL1 0x13
35 #define PHY_CTL1_MDICD BIT(3)
36 #define PHY_CTL1_MDIAB BIT(2)
37 #define PHY_CTL1_AMDIX BIT(0)
38 #define PHY_MIISTAT 0x18 /* MII state */
39 #define PHY_IMASK 0x19 /* interrupt mask */
40 #define PHY_ISTAT 0x1A /* interrupt status */
41 #define PHY_FWV 0x1E /* firmware version */
42
43 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
44 #define PHY_MIISTAT_DPX BIT(3)
45 #define PHY_MIISTAT_LS BIT(10)
46
47 #define PHY_MIISTAT_SPD_10 0
48 #define PHY_MIISTAT_SPD_100 1
49 #define PHY_MIISTAT_SPD_1000 2
50 #define PHY_MIISTAT_SPD_2500 4
51
52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
55 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
56 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */
57 #define PHY_IMASK_LSTC BIT(0) /* Link state change */
58 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
59 PHY_IMASK_LSPC | \
60 PHY_IMASK_DXMC | \
61 PHY_IMASK_ADSC | \
62 PHY_IMASK_ANC)
63
64 #define PHY_FWV_REL_MASK BIT(15)
65 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
66 #define PHY_FWV_MINOR_MASK GENMASK(7, 0)
67
68 #define PHY_PMA_MGBT_POLARITY 0x82
69 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
70 #define PHY_MDI_MDI_X_NORMAL 0x3
71 #define PHY_MDI_MDI_X_AB 0x2
72 #define PHY_MDI_MDI_X_CD 0x1
73 #define PHY_MDI_MDI_X_CROSS 0x0
74
75 /* SGMII */
76 #define VSPEC1_SGMII_CTRL 0x08
77 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
78 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
79 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
80 VSPEC1_SGMII_CTRL_ANRS)
81
82 /* Temperature sensor */
83 #define VSPEC1_TEMP_STA 0x0E
84 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
85
86 /* Mailbox */
87 #define VSPEC1_MBOX_DATA 0x5
88 #define VSPEC1_MBOX_ADDRLO 0x6
89 #define VSPEC1_MBOX_CMD 0x7
90 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
91 #define VSPEC1_MBOX_CMD_RD (0 << 8)
92 #define VSPEC1_MBOX_CMD_READY BIT(15)
93
94 /* WoL */
95 #define VPSPEC2_WOL_CTL 0x0E06
96 #define VPSPEC2_WOL_AD01 0x0E08
97 #define VPSPEC2_WOL_AD23 0x0E09
98 #define VPSPEC2_WOL_AD45 0x0E0A
99 #define WOL_EN BIT(0)
100
101 /* Internal registers, access via mbox */
102 #define REG_GPIO0_OUT 0xd3ce00
103
104 struct gpy_priv {
105 /* serialize mailbox acesses */
106 struct mutex mbox_lock;
107
108 u8 fw_major;
109 u8 fw_minor;
110 u32 wolopts;
111
112 /* It takes 3 seconds to fully switch out of loopback mode before
113 * it can safely re-enter loopback mode. Record the time when
114 * loopback is disabled. Check and wait if necessary before loopback
115 * is enabled.
116 */
117 u64 lb_dis_to;
118 };
119
120 static const struct {
121 int major;
122 int minor;
123 } ver_need_sgmii_reaneg[] = {
124 {7, 0x6D},
125 {8, 0x6D},
126 {9, 0x73},
127 };
128
129 #if IS_ENABLED(CONFIG_HWMON)
130 /* The original translation formulae of the temperature (in degrees of Celsius)
131 * are as follows:
132 *
133 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
134 * 3.0762e-1*(N^1) + -5.2156e1
135 *
136 * where [-52.156, 137.961]C and N = [0, 1023].
137 *
138 * They must be accordingly altered to be suitable for the integer arithmetics.
139 * The technique is called 'factor redistribution', which just makes sure the
140 * multiplications and divisions are made so to have a result of the operations
141 * within the integer numbers limit. In addition we need to translate the
142 * formulae to accept millidegrees of Celsius. Here what it looks like after
143 * the alterations:
144 *
145 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
146 * 307620e-3*(N^1) + -52156
147 *
148 * where T = [-52156, 137961]mC and N = [0, 1023].
149 */
150 static const struct polynomial poly_N_to_temp = {
151 .terms = {
152 {4, -25761, 1000, 1},
153 {3, 97332, 1000, 1},
154 {2, -191650, 1000, 1},
155 {1, 307620, 1000, 1},
156 {0, -52156, 1, 1}
157 }
158 };
159
gpy_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)160 static int gpy_hwmon_read(struct device *dev,
161 enum hwmon_sensor_types type,
162 u32 attr, int channel, long *value)
163 {
164 struct phy_device *phydev = dev_get_drvdata(dev);
165 int ret;
166
167 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
168 if (ret < 0)
169 return ret;
170 if (!ret)
171 return -ENODATA;
172
173 *value = polynomial_calc(&poly_N_to_temp,
174 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
175
176 return 0;
177 }
178
gpy_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)179 static umode_t gpy_hwmon_is_visible(const void *data,
180 enum hwmon_sensor_types type,
181 u32 attr, int channel)
182 {
183 return 0444;
184 }
185
186 static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
187 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
188 NULL
189 };
190
191 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
192 .is_visible = gpy_hwmon_is_visible,
193 .read = gpy_hwmon_read,
194 };
195
196 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
197 .ops = &gpy_hwmon_hwmon_ops,
198 .info = gpy_hwmon_info,
199 };
200
gpy_hwmon_register(struct phy_device * phydev)201 static int gpy_hwmon_register(struct phy_device *phydev)
202 {
203 struct device *dev = &phydev->mdio.dev;
204 struct device *hwmon_dev;
205 char *hwmon_name;
206
207 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
208 if (IS_ERR(hwmon_name))
209 return PTR_ERR(hwmon_name);
210
211 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
212 phydev,
213 &gpy_hwmon_chip_info,
214 NULL);
215
216 return PTR_ERR_OR_ZERO(hwmon_dev);
217 }
218 #else
gpy_hwmon_register(struct phy_device * phydev)219 static int gpy_hwmon_register(struct phy_device *phydev)
220 {
221 return 0;
222 }
223 #endif
224
gpy_ack_interrupt(struct phy_device * phydev)225 static int gpy_ack_interrupt(struct phy_device *phydev)
226 {
227 int ret;
228
229 /* Clear all pending interrupts */
230 ret = phy_read(phydev, PHY_ISTAT);
231 return ret < 0 ? ret : 0;
232 }
233
gpy_mbox_read(struct phy_device * phydev,u32 addr)234 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
235 {
236 struct gpy_priv *priv = phydev->priv;
237 int val, ret;
238 u16 cmd;
239
240 mutex_lock(&priv->mbox_lock);
241
242 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
243 addr);
244 if (ret)
245 goto out;
246
247 cmd = VSPEC1_MBOX_CMD_RD;
248 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
249
250 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
251 if (ret)
252 goto out;
253
254 /* The mbox read is used in the interrupt workaround. It was observed
255 * that a read might take up to 2.5ms. This is also the time for which
256 * the interrupt line is stuck low. To be on the safe side, poll the
257 * ready bit for 10ms.
258 */
259 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
260 VSPEC1_MBOX_CMD, val,
261 (val & VSPEC1_MBOX_CMD_READY),
262 500, 10000, false);
263 if (ret)
264 goto out;
265
266 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
267
268 out:
269 mutex_unlock(&priv->mbox_lock);
270 return ret;
271 }
272
gpy_config_init(struct phy_device * phydev)273 static int gpy_config_init(struct phy_device *phydev)
274 {
275 /* Nothing to configure. Configuration Requirement Placeholder */
276 return 0;
277 }
278
gpy_probe(struct phy_device * phydev)279 static int gpy_probe(struct phy_device *phydev)
280 {
281 struct device *dev = &phydev->mdio.dev;
282 struct gpy_priv *priv;
283 int fw_version;
284 int ret;
285
286 if (!phydev->is_c45) {
287 ret = phy_get_c45_ids(phydev);
288 if (ret < 0)
289 return ret;
290 }
291
292 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
293 if (!priv)
294 return -ENOMEM;
295 phydev->priv = priv;
296 mutex_init(&priv->mbox_lock);
297
298 if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
299 phydev->dev_flags |= PHY_F_NO_IRQ;
300
301 fw_version = phy_read(phydev, PHY_FWV);
302 if (fw_version < 0)
303 return fw_version;
304 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
305 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
306
307 ret = gpy_hwmon_register(phydev);
308 if (ret)
309 return ret;
310
311 /* Show GPY PHY FW version in dmesg */
312 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
313 priv->fw_major, priv->fw_minor, fw_version,
314 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
315
316 return 0;
317 }
318
gpy_sgmii_need_reaneg(struct phy_device * phydev)319 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
320 {
321 struct gpy_priv *priv = phydev->priv;
322 size_t i;
323
324 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
325 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
326 continue;
327 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
328 return true;
329 break;
330 }
331
332 return false;
333 }
334
gpy_2500basex_chk(struct phy_device * phydev)335 static bool gpy_2500basex_chk(struct phy_device *phydev)
336 {
337 int ret;
338
339 ret = phy_read(phydev, PHY_MIISTAT);
340 if (ret < 0) {
341 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
342 ret);
343 return false;
344 }
345
346 if (!(ret & PHY_MIISTAT_LS) ||
347 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
348 return false;
349
350 phydev->speed = SPEED_2500;
351 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
352 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
353 VSPEC1_SGMII_CTRL_ANEN, 0);
354 return true;
355 }
356
gpy_sgmii_aneg_en(struct phy_device * phydev)357 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
358 {
359 int ret;
360
361 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
362 if (ret < 0) {
363 phydev_err(phydev, "Error: MMD register access failed: %d\n",
364 ret);
365 return true;
366 }
367
368 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
369 }
370
gpy_config_mdix(struct phy_device * phydev,u8 ctrl)371 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
372 {
373 int ret;
374 u16 val;
375
376 switch (ctrl) {
377 case ETH_TP_MDI_AUTO:
378 val = PHY_CTL1_AMDIX;
379 break;
380 case ETH_TP_MDI_X:
381 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
382 break;
383 case ETH_TP_MDI:
384 val = 0;
385 break;
386 default:
387 return 0;
388 }
389
390 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
391 PHY_CTL1_MDICD, val);
392 if (ret < 0)
393 return ret;
394
395 return genphy_c45_restart_aneg(phydev);
396 }
397
gpy_config_aneg(struct phy_device * phydev)398 static int gpy_config_aneg(struct phy_device *phydev)
399 {
400 bool changed = false;
401 u32 adv;
402 int ret;
403
404 if (phydev->autoneg == AUTONEG_DISABLE) {
405 /* Configure half duplex with genphy_setup_forced,
406 * because genphy_c45_pma_setup_forced does not support.
407 */
408 return phydev->duplex != DUPLEX_FULL
409 ? genphy_setup_forced(phydev)
410 : genphy_c45_pma_setup_forced(phydev);
411 }
412
413 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
414 if (ret < 0)
415 return ret;
416
417 ret = genphy_c45_an_config_aneg(phydev);
418 if (ret < 0)
419 return ret;
420 if (ret > 0)
421 changed = true;
422
423 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
424 ret = phy_modify_changed(phydev, MII_CTRL1000,
425 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
426 adv);
427 if (ret < 0)
428 return ret;
429 if (ret > 0)
430 changed = true;
431
432 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
433 if (ret < 0)
434 return ret;
435
436 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
437 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
438 return 0;
439
440 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
441 * disabled.
442 */
443 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
444 !gpy_sgmii_aneg_en(phydev))
445 return 0;
446
447 /* There is a design constraint in GPY2xx device where SGMII AN is
448 * only triggered when there is change of speed. If, PHY link
449 * partner`s speed is still same even after PHY TPI is down and up
450 * again, SGMII AN is not triggered and hence no new in-band message
451 * from GPY to MAC side SGMII.
452 * This could cause an issue during power up, when PHY is up prior to
453 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
454 * wouldn`t receive new in-band message from GPY with correct link
455 * status, speed and duplex info.
456 *
457 * 1) If PHY is already up and TPI link status is still down (such as
458 * hard reboot), TPI link status is polled for 4 seconds before
459 * retriggerring SGMII AN.
460 * 2) If PHY is already up and TPI link status is also up (such as soft
461 * reboot), polling of TPI link status is not needed and SGMII AN is
462 * immediately retriggered.
463 * 3) Other conditions such as PHY is down, speed change etc, skip
464 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
465 * initiate SGMII AN.
466 */
467
468 if (phydev->state != PHY_UP)
469 return 0;
470
471 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
472 20000, 4000000, false);
473 if (ret == -ETIMEDOUT)
474 return 0;
475 else if (ret < 0)
476 return ret;
477
478 /* Trigger SGMII AN. */
479 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
480 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
481 }
482
gpy_update_mdix(struct phy_device * phydev)483 static int gpy_update_mdix(struct phy_device *phydev)
484 {
485 int ret;
486
487 ret = phy_read(phydev, PHY_CTL1);
488 if (ret < 0)
489 return ret;
490
491 if (ret & PHY_CTL1_AMDIX)
492 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
493 else
494 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
495 phydev->mdix_ctrl = ETH_TP_MDI_X;
496 else
497 phydev->mdix_ctrl = ETH_TP_MDI;
498
499 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
500 if (ret < 0)
501 return ret;
502
503 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
504 phydev->mdix = ETH_TP_MDI_X;
505 else
506 phydev->mdix = ETH_TP_MDI;
507
508 return 0;
509 }
510
gpy_update_interface(struct phy_device * phydev)511 static int gpy_update_interface(struct phy_device *phydev)
512 {
513 int ret;
514
515 /* Interface mode is fixed for USXGMII and integrated PHY */
516 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
517 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
518 return -EINVAL;
519
520 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
521 * according to speed. Disable ANEG in 2500-BaseX mode.
522 */
523 switch (phydev->speed) {
524 case SPEED_2500:
525 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
526 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
527 VSPEC1_SGMII_CTRL_ANEN, 0);
528 if (ret < 0) {
529 phydev_err(phydev,
530 "Error: Disable of SGMII ANEG failed: %d\n",
531 ret);
532 return ret;
533 }
534 break;
535 case SPEED_1000:
536 case SPEED_100:
537 case SPEED_10:
538 phydev->interface = PHY_INTERFACE_MODE_SGMII;
539 if (gpy_sgmii_aneg_en(phydev))
540 break;
541 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
542 * if ANEG is disabled (in 2500-BaseX mode).
543 */
544 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
545 VSPEC1_SGMII_ANEN_ANRS,
546 VSPEC1_SGMII_ANEN_ANRS);
547 if (ret < 0) {
548 phydev_err(phydev,
549 "Error: Enable of SGMII ANEG failed: %d\n",
550 ret);
551 return ret;
552 }
553 break;
554 }
555
556 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
557 ret = genphy_read_master_slave(phydev);
558 if (ret < 0)
559 return ret;
560 }
561
562 return gpy_update_mdix(phydev);
563 }
564
gpy_read_status(struct phy_device * phydev)565 static int gpy_read_status(struct phy_device *phydev)
566 {
567 int ret;
568
569 ret = genphy_update_link(phydev);
570 if (ret)
571 return ret;
572
573 phydev->speed = SPEED_UNKNOWN;
574 phydev->duplex = DUPLEX_UNKNOWN;
575 phydev->pause = 0;
576 phydev->asym_pause = 0;
577
578 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
579 ret = genphy_c45_read_lpa(phydev);
580 if (ret < 0)
581 return ret;
582
583 /* Read the link partner's 1G advertisement */
584 ret = phy_read(phydev, MII_STAT1000);
585 if (ret < 0)
586 return ret;
587 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
588 } else if (phydev->autoneg == AUTONEG_DISABLE) {
589 linkmode_zero(phydev->lp_advertising);
590 }
591
592 ret = phy_read(phydev, PHY_MIISTAT);
593 if (ret < 0)
594 return ret;
595
596 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
597 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
598 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
599 case PHY_MIISTAT_SPD_10:
600 phydev->speed = SPEED_10;
601 break;
602 case PHY_MIISTAT_SPD_100:
603 phydev->speed = SPEED_100;
604 break;
605 case PHY_MIISTAT_SPD_1000:
606 phydev->speed = SPEED_1000;
607 break;
608 case PHY_MIISTAT_SPD_2500:
609 phydev->speed = SPEED_2500;
610 break;
611 }
612
613 if (phydev->link) {
614 ret = gpy_update_interface(phydev);
615 if (ret < 0)
616 return ret;
617 }
618
619 return 0;
620 }
621
gpy_config_intr(struct phy_device * phydev)622 static int gpy_config_intr(struct phy_device *phydev)
623 {
624 struct gpy_priv *priv = phydev->priv;
625 u16 mask = 0;
626 int ret;
627
628 ret = gpy_ack_interrupt(phydev);
629 if (ret)
630 return ret;
631
632 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
633 mask = PHY_IMASK_MASK;
634
635 if (priv->wolopts & WAKE_MAGIC)
636 mask |= PHY_IMASK_WOL;
637
638 if (priv->wolopts & WAKE_PHY)
639 mask |= PHY_IMASK_LSTC;
640
641 return phy_write(phydev, PHY_IMASK, mask);
642 }
643
gpy_handle_interrupt(struct phy_device * phydev)644 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
645 {
646 int reg;
647
648 reg = phy_read(phydev, PHY_ISTAT);
649 if (reg < 0) {
650 phy_error(phydev);
651 return IRQ_NONE;
652 }
653
654 if (!(reg & PHY_IMASK_MASK))
655 return IRQ_NONE;
656
657 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
658 * is read. To avoid interrupt storms, delay the interrupt handling as
659 * long as the PHY drives the interrupt line. An internal bus read will
660 * stall as long as the interrupt line is asserted, thus just read a
661 * random register here.
662 * Because we cannot access the internal bus at all while the interrupt
663 * is driven by the PHY, there is no way to make the interrupt line
664 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
665 * frame. Therefore, polling is the best we can do and won't do any more
666 * harm.
667 * It was observed that this bug happens on link state and link speed
668 * changes independent of the firmware version.
669 */
670 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
671 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
672 if (reg < 0) {
673 phy_error(phydev);
674 return IRQ_NONE;
675 }
676 }
677
678 phy_trigger_machine(phydev);
679
680 return IRQ_HANDLED;
681 }
682
gpy_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)683 static int gpy_set_wol(struct phy_device *phydev,
684 struct ethtool_wolinfo *wol)
685 {
686 struct net_device *attach_dev = phydev->attached_dev;
687 struct gpy_priv *priv = phydev->priv;
688 int ret;
689
690 if (wol->wolopts & WAKE_MAGIC) {
691 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
692 * VPSPEC2_WOL_AD45 = Byte0:Byte1
693 * VPSPEC2_WOL_AD23 = Byte2:Byte3
694 * VPSPEC2_WOL_AD01 = Byte4:Byte5
695 */
696 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
697 VPSPEC2_WOL_AD45,
698 ((attach_dev->dev_addr[0] << 8) |
699 attach_dev->dev_addr[1]));
700 if (ret < 0)
701 return ret;
702
703 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
704 VPSPEC2_WOL_AD23,
705 ((attach_dev->dev_addr[2] << 8) |
706 attach_dev->dev_addr[3]));
707 if (ret < 0)
708 return ret;
709
710 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
711 VPSPEC2_WOL_AD01,
712 ((attach_dev->dev_addr[4] << 8) |
713 attach_dev->dev_addr[5]));
714 if (ret < 0)
715 return ret;
716
717 /* Enable the WOL interrupt */
718 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
719 if (ret < 0)
720 return ret;
721
722 /* Enable magic packet matching */
723 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
724 VPSPEC2_WOL_CTL,
725 WOL_EN);
726 if (ret < 0)
727 return ret;
728
729 /* Clear the interrupt status register.
730 * Only WoL is enabled so clear all.
731 */
732 ret = phy_read(phydev, PHY_ISTAT);
733 if (ret < 0)
734 return ret;
735
736 priv->wolopts |= WAKE_MAGIC;
737 } else {
738 /* Disable magic packet matching */
739 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
740 VPSPEC2_WOL_CTL,
741 WOL_EN);
742 if (ret < 0)
743 return ret;
744
745 /* Disable the WOL interrupt */
746 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL);
747 if (ret < 0)
748 return ret;
749
750 priv->wolopts &= ~WAKE_MAGIC;
751 }
752
753 if (wol->wolopts & WAKE_PHY) {
754 /* Enable the link state change interrupt */
755 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
756 if (ret < 0)
757 return ret;
758
759 /* Clear the interrupt status register */
760 ret = phy_read(phydev, PHY_ISTAT);
761 if (ret < 0)
762 return ret;
763
764 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
765 phy_trigger_machine(phydev);
766
767 priv->wolopts |= WAKE_PHY;
768 return 0;
769 }
770
771 priv->wolopts &= ~WAKE_PHY;
772 /* Disable the link state change interrupt */
773 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
774 }
775
gpy_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)776 static void gpy_get_wol(struct phy_device *phydev,
777 struct ethtool_wolinfo *wol)
778 {
779 struct gpy_priv *priv = phydev->priv;
780
781 wol->supported = WAKE_MAGIC | WAKE_PHY;
782 wol->wolopts = priv->wolopts;
783 }
784
gpy_loopback(struct phy_device * phydev,bool enable)785 static int gpy_loopback(struct phy_device *phydev, bool enable)
786 {
787 struct gpy_priv *priv = phydev->priv;
788 u16 set = 0;
789 int ret;
790
791 if (enable) {
792 u64 now = get_jiffies_64();
793
794 /* wait until 3 seconds from last disable */
795 if (time_before64(now, priv->lb_dis_to))
796 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
797
798 set = BMCR_LOOPBACK;
799 }
800
801 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
802 if (ret <= 0)
803 return ret;
804
805 if (enable) {
806 /* It takes some time for PHY device to switch into
807 * loopback mode.
808 */
809 msleep(100);
810 } else {
811 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
812 }
813
814 return 0;
815 }
816
gpy115_loopback(struct phy_device * phydev,bool enable)817 static int gpy115_loopback(struct phy_device *phydev, bool enable)
818 {
819 struct gpy_priv *priv = phydev->priv;
820
821 if (enable)
822 return gpy_loopback(phydev, enable);
823
824 if (priv->fw_minor > 0x76)
825 return gpy_loopback(phydev, 0);
826
827 return genphy_soft_reset(phydev);
828 }
829
830 static struct phy_driver gpy_drivers[] = {
831 {
832 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
833 .name = "Maxlinear Ethernet GPY2xx",
834 .get_features = genphy_c45_pma_read_abilities,
835 .config_init = gpy_config_init,
836 .probe = gpy_probe,
837 .suspend = genphy_suspend,
838 .resume = genphy_resume,
839 .config_aneg = gpy_config_aneg,
840 .aneg_done = genphy_c45_aneg_done,
841 .read_status = gpy_read_status,
842 .config_intr = gpy_config_intr,
843 .handle_interrupt = gpy_handle_interrupt,
844 .set_wol = gpy_set_wol,
845 .get_wol = gpy_get_wol,
846 .set_loopback = gpy_loopback,
847 },
848 {
849 .phy_id = PHY_ID_GPY115B,
850 .phy_id_mask = PHY_ID_GPYx15B_MASK,
851 .name = "Maxlinear Ethernet GPY115B",
852 .get_features = genphy_c45_pma_read_abilities,
853 .config_init = gpy_config_init,
854 .probe = gpy_probe,
855 .suspend = genphy_suspend,
856 .resume = genphy_resume,
857 .config_aneg = gpy_config_aneg,
858 .aneg_done = genphy_c45_aneg_done,
859 .read_status = gpy_read_status,
860 .config_intr = gpy_config_intr,
861 .handle_interrupt = gpy_handle_interrupt,
862 .set_wol = gpy_set_wol,
863 .get_wol = gpy_get_wol,
864 .set_loopback = gpy115_loopback,
865 },
866 {
867 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
868 .name = "Maxlinear Ethernet GPY115C",
869 .get_features = genphy_c45_pma_read_abilities,
870 .config_init = gpy_config_init,
871 .probe = gpy_probe,
872 .suspend = genphy_suspend,
873 .resume = genphy_resume,
874 .config_aneg = gpy_config_aneg,
875 .aneg_done = genphy_c45_aneg_done,
876 .read_status = gpy_read_status,
877 .config_intr = gpy_config_intr,
878 .handle_interrupt = gpy_handle_interrupt,
879 .set_wol = gpy_set_wol,
880 .get_wol = gpy_get_wol,
881 .set_loopback = gpy115_loopback,
882 },
883 {
884 .phy_id = PHY_ID_GPY211B,
885 .phy_id_mask = PHY_ID_GPY21xB_MASK,
886 .name = "Maxlinear Ethernet GPY211B",
887 .get_features = genphy_c45_pma_read_abilities,
888 .config_init = gpy_config_init,
889 .probe = gpy_probe,
890 .suspend = genphy_suspend,
891 .resume = genphy_resume,
892 .config_aneg = gpy_config_aneg,
893 .aneg_done = genphy_c45_aneg_done,
894 .read_status = gpy_read_status,
895 .config_intr = gpy_config_intr,
896 .handle_interrupt = gpy_handle_interrupt,
897 .set_wol = gpy_set_wol,
898 .get_wol = gpy_get_wol,
899 .set_loopback = gpy_loopback,
900 },
901 {
902 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
903 .name = "Maxlinear Ethernet GPY211C",
904 .get_features = genphy_c45_pma_read_abilities,
905 .config_init = gpy_config_init,
906 .probe = gpy_probe,
907 .suspend = genphy_suspend,
908 .resume = genphy_resume,
909 .config_aneg = gpy_config_aneg,
910 .aneg_done = genphy_c45_aneg_done,
911 .read_status = gpy_read_status,
912 .config_intr = gpy_config_intr,
913 .handle_interrupt = gpy_handle_interrupt,
914 .set_wol = gpy_set_wol,
915 .get_wol = gpy_get_wol,
916 .set_loopback = gpy_loopback,
917 },
918 {
919 .phy_id = PHY_ID_GPY212B,
920 .phy_id_mask = PHY_ID_GPY21xB_MASK,
921 .name = "Maxlinear Ethernet GPY212B",
922 .get_features = genphy_c45_pma_read_abilities,
923 .config_init = gpy_config_init,
924 .probe = gpy_probe,
925 .suspend = genphy_suspend,
926 .resume = genphy_resume,
927 .config_aneg = gpy_config_aneg,
928 .aneg_done = genphy_c45_aneg_done,
929 .read_status = gpy_read_status,
930 .config_intr = gpy_config_intr,
931 .handle_interrupt = gpy_handle_interrupt,
932 .set_wol = gpy_set_wol,
933 .get_wol = gpy_get_wol,
934 .set_loopback = gpy_loopback,
935 },
936 {
937 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
938 .name = "Maxlinear Ethernet GPY212C",
939 .get_features = genphy_c45_pma_read_abilities,
940 .config_init = gpy_config_init,
941 .probe = gpy_probe,
942 .suspend = genphy_suspend,
943 .resume = genphy_resume,
944 .config_aneg = gpy_config_aneg,
945 .aneg_done = genphy_c45_aneg_done,
946 .read_status = gpy_read_status,
947 .config_intr = gpy_config_intr,
948 .handle_interrupt = gpy_handle_interrupt,
949 .set_wol = gpy_set_wol,
950 .get_wol = gpy_get_wol,
951 .set_loopback = gpy_loopback,
952 },
953 {
954 .phy_id = PHY_ID_GPY215B,
955 .phy_id_mask = PHY_ID_GPYx15B_MASK,
956 .name = "Maxlinear Ethernet GPY215B",
957 .get_features = genphy_c45_pma_read_abilities,
958 .config_init = gpy_config_init,
959 .probe = gpy_probe,
960 .suspend = genphy_suspend,
961 .resume = genphy_resume,
962 .config_aneg = gpy_config_aneg,
963 .aneg_done = genphy_c45_aneg_done,
964 .read_status = gpy_read_status,
965 .config_intr = gpy_config_intr,
966 .handle_interrupt = gpy_handle_interrupt,
967 .set_wol = gpy_set_wol,
968 .get_wol = gpy_get_wol,
969 .set_loopback = gpy_loopback,
970 },
971 {
972 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
973 .name = "Maxlinear Ethernet GPY215C",
974 .get_features = genphy_c45_pma_read_abilities,
975 .config_init = gpy_config_init,
976 .probe = gpy_probe,
977 .suspend = genphy_suspend,
978 .resume = genphy_resume,
979 .config_aneg = gpy_config_aneg,
980 .aneg_done = genphy_c45_aneg_done,
981 .read_status = gpy_read_status,
982 .config_intr = gpy_config_intr,
983 .handle_interrupt = gpy_handle_interrupt,
984 .set_wol = gpy_set_wol,
985 .get_wol = gpy_get_wol,
986 .set_loopback = gpy_loopback,
987 },
988 {
989 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
990 .name = "Maxlinear Ethernet GPY241B",
991 .get_features = genphy_c45_pma_read_abilities,
992 .config_init = gpy_config_init,
993 .probe = gpy_probe,
994 .suspend = genphy_suspend,
995 .resume = genphy_resume,
996 .config_aneg = gpy_config_aneg,
997 .aneg_done = genphy_c45_aneg_done,
998 .read_status = gpy_read_status,
999 .config_intr = gpy_config_intr,
1000 .handle_interrupt = gpy_handle_interrupt,
1001 .set_wol = gpy_set_wol,
1002 .get_wol = gpy_get_wol,
1003 .set_loopback = gpy_loopback,
1004 },
1005 {
1006 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
1007 .name = "Maxlinear Ethernet GPY241BM",
1008 .get_features = genphy_c45_pma_read_abilities,
1009 .config_init = gpy_config_init,
1010 .probe = gpy_probe,
1011 .suspend = genphy_suspend,
1012 .resume = genphy_resume,
1013 .config_aneg = gpy_config_aneg,
1014 .aneg_done = genphy_c45_aneg_done,
1015 .read_status = gpy_read_status,
1016 .config_intr = gpy_config_intr,
1017 .handle_interrupt = gpy_handle_interrupt,
1018 .set_wol = gpy_set_wol,
1019 .get_wol = gpy_get_wol,
1020 .set_loopback = gpy_loopback,
1021 },
1022 {
1023 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1024 .name = "Maxlinear Ethernet GPY245B",
1025 .get_features = genphy_c45_pma_read_abilities,
1026 .config_init = gpy_config_init,
1027 .probe = gpy_probe,
1028 .suspend = genphy_suspend,
1029 .resume = genphy_resume,
1030 .config_aneg = gpy_config_aneg,
1031 .aneg_done = genphy_c45_aneg_done,
1032 .read_status = gpy_read_status,
1033 .config_intr = gpy_config_intr,
1034 .handle_interrupt = gpy_handle_interrupt,
1035 .set_wol = gpy_set_wol,
1036 .get_wol = gpy_get_wol,
1037 .set_loopback = gpy_loopback,
1038 },
1039 };
1040 module_phy_driver(gpy_drivers);
1041
1042 static struct mdio_device_id __maybe_unused gpy_tbl[] = {
1043 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1044 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1045 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1046 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1047 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1048 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1049 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1050 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1051 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1052 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1053 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1054 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1055 { }
1056 };
1057 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1058
1059 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1060 MODULE_AUTHOR("Xu Liang");
1061 MODULE_LICENSE("GPL");
1062