1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+
220b2af32SRussell King /*
320b2af32SRussell King * Marvell 10G 88x3310 PHY driver
420b2af32SRussell King *
520b2af32SRussell King * Based upon the ID registers, this PHY appears to be a mixture of IPs
620b2af32SRussell King * from two different companies.
720b2af32SRussell King *
820b2af32SRussell King * There appears to be several different data paths through the PHY which
920b2af32SRussell King * are automatically managed by the PHY. The following has been determined
1005ca1b32SRussell King * via observation and experimentation for a setup using single-lane Serdes:
1120b2af32SRussell King *
1220b2af32SRussell King * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
1320b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
1420b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
1520b2af32SRussell King *
1605ca1b32SRussell King * With XAUI, observation shows:
1705ca1b32SRussell King *
1805ca1b32SRussell King * XAUI PHYXS -- <appropriate PCS as above>
1905ca1b32SRussell King *
2005ca1b32SRussell King * and no switching of the host interface mode occurs.
2105ca1b32SRussell King *
2220b2af32SRussell King * If both the fiber and copper ports are connected, the first to gain
2320b2af32SRussell King * link takes priority and the other port is completely locked out.
2420b2af32SRussell King */
254075a6a0SRussell King #include <linux/bitfield.h>
260d3ad854SRussell King #include <linux/ctype.h>
278d8963c3SRussell King #include <linux/delay.h>
280d3ad854SRussell King #include <linux/hwmon.h>
29952b6b3bSAntoine Tenart #include <linux/marvell_phy.h>
300d3ad854SRussell King #include <linux/phy.h>
3136023da1SRussell King #include <linux/sfp.h>
3208041a9aSVoon Weifeng #include <linux/netdevice.h>
3320b2af32SRussell King
34c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
35c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
36c47455f9SMaxime Chevallier
374075a6a0SRussell King #define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
384075a6a0SRussell King
3920b2af32SRussell King enum {
40dd649b4fSRussell King MV_PMA_FW_VER0 = 0xc011,
41dd649b4fSRussell King MV_PMA_FW_VER1 = 0xc012,
429ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL = 0xc04a,
439ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
449ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
459ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
469ab0fbd0SMarek Behún MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
479ab0fbd0SMarek Behún MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
489ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
499ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
509ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
513d3ced2eSRussell King MV_PMA_BOOT = 0xc050,
523d3ced2eSRussell King MV_PMA_BOOT_FATAL = BIT(0),
533d3ced2eSRussell King
5420b2af32SRussell King MV_PCS_BASE_T = 0x0000,
5520b2af32SRussell King MV_PCS_BASE_R = 0x1000,
5620b2af32SRussell King MV_PCS_1000BASEX = 0x2000,
5720b2af32SRussell King
588d8963c3SRussell King MV_PCS_CSCR1 = 0x8000,
59a585c03eSRussell King MV_PCS_CSCR1_ED_MASK = 0x0300,
60a585c03eSRussell King MV_PCS_CSCR1_ED_OFF = 0x0000,
61a585c03eSRussell King MV_PCS_CSCR1_ED_RX = 0x0200,
62a585c03eSRussell King MV_PCS_CSCR1_ED_NLP = 0x0300,
638d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK = 0x0060,
648d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDI = 0x0000,
658d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
668d8963c3SRussell King MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
678d8963c3SRussell King
684075a6a0SRussell King MV_PCS_DSC1 = 0x8003,
694075a6a0SRussell King MV_PCS_DSC1_ENABLE = BIT(9),
704075a6a0SRussell King MV_PCS_DSC1_10GBT = 0x01c0,
714075a6a0SRussell King MV_PCS_DSC1_1GBR = 0x0038,
724075a6a0SRussell King MV_PCS_DSC1_100BTX = 0x0007,
734075a6a0SRussell King MV_PCS_DSC2 = 0x8004,
744075a6a0SRussell King MV_PCS_DSC2_2P5G = 0xf000,
754075a6a0SRussell King MV_PCS_DSC2_5G = 0x0f00,
764075a6a0SRussell King
77c84786faSRussell King MV_PCS_CSSR1 = 0x8008,
78c84786faSRussell King MV_PCS_CSSR1_SPD1_MASK = 0xc000,
79c84786faSRussell King MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
80c84786faSRussell King MV_PCS_CSSR1_SPD1_1000 = 0x8000,
81c84786faSRussell King MV_PCS_CSSR1_SPD1_100 = 0x4000,
82c84786faSRussell King MV_PCS_CSSR1_SPD1_10 = 0x0000,
83c84786faSRussell King MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
84c84786faSRussell King MV_PCS_CSSR1_RESOLVED = BIT(11),
85c84786faSRussell King MV_PCS_CSSR1_MDIX = BIT(6),
86c84786faSRussell King MV_PCS_CSSR1_SPD2_MASK = 0x000c,
87c84786faSRussell King MV_PCS_CSSR1_SPD2_5000 = 0x0008,
88c84786faSRussell King MV_PCS_CSSR1_SPD2_2500 = 0x0004,
89c84786faSRussell King MV_PCS_CSSR1_SPD2_10000 = 0x0000,
90ea4efe25SRussell King
91c3e302edSBaruch Siach /* Temperature read register (88E2110 only) */
92c3e302edSBaruch Siach MV_PCS_TEMP = 0x8042,
93c3e302edSBaruch Siach
94a5de4be0SMarek Behún /* Number of ports on the device */
95a5de4be0SMarek Behún MV_PCS_PORT_INFO = 0xd00d,
96a5de4be0SMarek Behún MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
97a5de4be0SMarek Behún MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
98a5de4be0SMarek Behún
99d6d29292SRussell King /* SerDes reinitialization 88E21X0 */
100d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2 = 0x800f,
101d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
102d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
103d6d29292SRussell King
10420b2af32SRussell King /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
10520b2af32SRussell King * registers appear to set themselves to the 0x800X when AN is
10620b2af32SRussell King * restarted, but status registers appear readable from either.
10720b2af32SRussell King */
10820b2af32SRussell King MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
10920b2af32SRussell King MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
1100d3ad854SRussell King
1110d3ad854SRussell King /* Vendor2 MMD registers */
112af3e28cbSAntoine Tenart MV_V2_PORT_CTRL = 0xf001,
1138f48c2acSRussell King MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
1149893f316SMarek Behún MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
1159893f316SMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
116f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
117f8ee45fcSMarek Behún MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
118f8ee45fcSMarek Behún MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
119f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
120f8ee45fcSMarek Behún MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
121f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
122f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
123f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
124f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
12508041a9aSVoon Weifeng MV_V2_PORT_INTR_STS = 0xf040,
12608041a9aSVoon Weifeng MV_V2_PORT_INTR_MASK = 0xf043,
12708041a9aSVoon Weifeng MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
12808041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
12908041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
13008041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
13108041a9aSVoon Weifeng /* Wake on LAN registers */
13208041a9aSVoon Weifeng MV_V2_WOL_CTRL = 0xf06e,
13308041a9aSVoon Weifeng MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
13408041a9aSVoon Weifeng MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
135c3e302edSBaruch Siach /* Temperature control/read registers (88X3310 only) */
1360d3ad854SRussell King MV_V2_TEMP_CTRL = 0xf08a,
1370d3ad854SRussell King MV_V2_TEMP_CTRL_MASK = 0xc000,
1380d3ad854SRussell King MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
1390d3ad854SRussell King MV_V2_TEMP_CTRL_DISABLE = 0xc000,
1400d3ad854SRussell King MV_V2_TEMP = 0xf08c,
1410d3ad854SRussell King MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
1420d3ad854SRussell King };
1430d3ad854SRussell King
14497bbe3bdSMarek Behún struct mv3310_chip {
1454075a6a0SRussell King bool (*has_downshift)(struct phy_device *phydev);
146261a74c6SMarek Behún void (*init_supported_interfaces)(unsigned long *mask);
14797bbe3bdSMarek Behún int (*get_mactype)(struct phy_device *phydev);
148d6d29292SRussell King int (*set_mactype)(struct phy_device *phydev, int mactype);
149d6d29292SRussell King int (*select_mactype)(unsigned long *interfaces);
15097bbe3bdSMarek Behún int (*init_interface)(struct phy_device *phydev, int mactype);
151884d9a67SMarek Behún
152884d9a67SMarek Behún #ifdef CONFIG_HWMON
153884d9a67SMarek Behún int (*hwmon_read_temp_reg)(struct phy_device *phydev);
154884d9a67SMarek Behún #endif
15597bbe3bdSMarek Behún };
15697bbe3bdSMarek Behún
1570d3ad854SRussell King struct mv3310_priv {
158261a74c6SMarek Behún DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
159261a74c6SMarek Behún
160dd649b4fSRussell King u32 firmware_ver;
1614075a6a0SRussell King bool has_downshift;
162e1170333SBaruch Siach bool rate_match;
16397bbe3bdSMarek Behún phy_interface_t const_interface;
164dd649b4fSRussell King
1650d3ad854SRussell King struct device *hwmon_dev;
1660d3ad854SRussell King char *hwmon_name;
16720b2af32SRussell King };
16820b2af32SRussell King
to_mv3310_chip(struct phy_device * phydev)16997bbe3bdSMarek Behún static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
17097bbe3bdSMarek Behún {
17197bbe3bdSMarek Behún return phydev->drv->driver_data;
17297bbe3bdSMarek Behún }
17397bbe3bdSMarek Behún
1740d3ad854SRussell King #ifdef CONFIG_HWMON
mv3310_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)1750d3ad854SRussell King static umode_t mv3310_hwmon_is_visible(const void *data,
1760d3ad854SRussell King enum hwmon_sensor_types type,
1770d3ad854SRussell King u32 attr, int channel)
1780d3ad854SRussell King {
1790d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval)
1800d3ad854SRussell King return 0444;
1810d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input)
1820d3ad854SRussell King return 0444;
1830d3ad854SRussell King return 0;
1840d3ad854SRussell King }
1850d3ad854SRussell King
mv3310_hwmon_read_temp_reg(struct phy_device * phydev)186c3e302edSBaruch Siach static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
187c3e302edSBaruch Siach {
188c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
189c3e302edSBaruch Siach }
190c3e302edSBaruch Siach
mv2110_hwmon_read_temp_reg(struct phy_device * phydev)191c3e302edSBaruch Siach static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
192c3e302edSBaruch Siach {
193c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
194c3e302edSBaruch Siach }
195c3e302edSBaruch Siach
mv3310_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)1960d3ad854SRussell King static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
1970d3ad854SRussell King u32 attr, int channel, long *value)
1980d3ad854SRussell King {
1990d3ad854SRussell King struct phy_device *phydev = dev_get_drvdata(dev);
200884d9a67SMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev);
2010d3ad854SRussell King int temp;
2020d3ad854SRussell King
2030d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
2040d3ad854SRussell King *value = MSEC_PER_SEC;
2050d3ad854SRussell King return 0;
2060d3ad854SRussell King }
2070d3ad854SRussell King
2080d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) {
209884d9a67SMarek Behún temp = chip->hwmon_read_temp_reg(phydev);
2100d3ad854SRussell King if (temp < 0)
2110d3ad854SRussell King return temp;
2120d3ad854SRussell King
2130d3ad854SRussell King *value = ((temp & 0xff) - 75) * 1000;
2140d3ad854SRussell King
2150d3ad854SRussell King return 0;
2160d3ad854SRussell King }
2170d3ad854SRussell King
2180d3ad854SRussell King return -EOPNOTSUPP;
2190d3ad854SRussell King }
2200d3ad854SRussell King
2210d3ad854SRussell King static const struct hwmon_ops mv3310_hwmon_ops = {
2220d3ad854SRussell King .is_visible = mv3310_hwmon_is_visible,
2230d3ad854SRussell King .read = mv3310_hwmon_read,
2240d3ad854SRussell King };
2250d3ad854SRussell King
2260d3ad854SRussell King static u32 mv3310_hwmon_chip_config[] = {
2270d3ad854SRussell King HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
2280d3ad854SRussell King 0,
2290d3ad854SRussell King };
2300d3ad854SRussell King
2310d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_chip = {
2320d3ad854SRussell King .type = hwmon_chip,
2330d3ad854SRussell King .config = mv3310_hwmon_chip_config,
2340d3ad854SRussell King };
2350d3ad854SRussell King
2360d3ad854SRussell King static u32 mv3310_hwmon_temp_config[] = {
2370d3ad854SRussell King HWMON_T_INPUT,
2380d3ad854SRussell King 0,
2390d3ad854SRussell King };
2400d3ad854SRussell King
2410d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_temp = {
2420d3ad854SRussell King .type = hwmon_temp,
2430d3ad854SRussell King .config = mv3310_hwmon_temp_config,
2440d3ad854SRussell King };
2450d3ad854SRussell King
246ff0805e2SKrzysztof Kozlowski static const struct hwmon_channel_info * const mv3310_hwmon_info[] = {
2470d3ad854SRussell King &mv3310_hwmon_chip,
2480d3ad854SRussell King &mv3310_hwmon_temp,
2490d3ad854SRussell King NULL,
2500d3ad854SRussell King };
2510d3ad854SRussell King
2520d3ad854SRussell King static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
2530d3ad854SRussell King .ops = &mv3310_hwmon_ops,
2540d3ad854SRussell King .info = mv3310_hwmon_info,
2550d3ad854SRussell King };
2560d3ad854SRussell King
mv3310_hwmon_config(struct phy_device * phydev,bool enable)2570d3ad854SRussell King static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
2580d3ad854SRussell King {
2590d3ad854SRussell King u16 val;
2600d3ad854SRussell King int ret;
2610d3ad854SRussell King
262c3e302edSBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
263c3e302edSBaruch Siach return 0;
264c3e302edSBaruch Siach
2650d3ad854SRussell King ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
2660d3ad854SRussell King MV_V2_TEMP_UNKNOWN);
2670d3ad854SRussell King if (ret < 0)
2680d3ad854SRussell King return ret;
2690d3ad854SRussell King
2700d3ad854SRussell King val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
2710d3ad854SRussell King
272b06d8e5aSHeiner Kallweit return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
273b06d8e5aSHeiner Kallweit MV_V2_TEMP_CTRL_MASK, val);
2740d3ad854SRussell King }
2750d3ad854SRussell King
mv3310_hwmon_probe(struct phy_device * phydev)2760d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev)
2770d3ad854SRussell King {
2780d3ad854SRussell King struct device *dev = &phydev->mdio.dev;
2790d3ad854SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
2800d3ad854SRussell King int i, j, ret;
2810d3ad854SRussell King
2820d3ad854SRussell King priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
2830d3ad854SRussell King if (!priv->hwmon_name)
2840d3ad854SRussell King return -ENODEV;
2850d3ad854SRussell King
2860d3ad854SRussell King for (i = j = 0; priv->hwmon_name[i]; i++) {
2870d3ad854SRussell King if (isalnum(priv->hwmon_name[i])) {
2880d3ad854SRussell King if (i != j)
2890d3ad854SRussell King priv->hwmon_name[j] = priv->hwmon_name[i];
2900d3ad854SRussell King j++;
2910d3ad854SRussell King }
2920d3ad854SRussell King }
2930d3ad854SRussell King priv->hwmon_name[j] = '\0';
2940d3ad854SRussell King
2950d3ad854SRussell King ret = mv3310_hwmon_config(phydev, true);
2960d3ad854SRussell King if (ret)
2970d3ad854SRussell King return ret;
2980d3ad854SRussell King
2990d3ad854SRussell King priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
3000d3ad854SRussell King priv->hwmon_name, phydev,
3010d3ad854SRussell King &mv3310_hwmon_chip_info, NULL);
3020d3ad854SRussell King
3030d3ad854SRussell King return PTR_ERR_OR_ZERO(priv->hwmon_dev);
3040d3ad854SRussell King }
3050d3ad854SRussell King #else
mv3310_hwmon_config(struct phy_device * phydev,bool enable)3060d3ad854SRussell King static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
3070d3ad854SRussell King {
3080d3ad854SRussell King return 0;
3090d3ad854SRussell King }
3100d3ad854SRussell King
mv3310_hwmon_probe(struct phy_device * phydev)3110d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev)
3120d3ad854SRussell King {
3130d3ad854SRussell King return 0;
3140d3ad854SRussell King }
3150d3ad854SRussell King #endif
3160d3ad854SRussell King
mv3310_power_down(struct phy_device * phydev)317c9cc1c81SRussell King static int mv3310_power_down(struct phy_device *phydev)
318c9cc1c81SRussell King {
319c9cc1c81SRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
320c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN);
321c9cc1c81SRussell King }
322c9cc1c81SRussell King
mv3310_power_up(struct phy_device * phydev)323c9cc1c81SRussell King static int mv3310_power_up(struct phy_device *phydev)
324c9cc1c81SRussell King {
3258f48c2acSRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
3268f48c2acSRussell King int ret;
3278f48c2acSRussell King
3288f48c2acSRussell King ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
329c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN);
3308f48c2acSRussell King
331*c7b75beaSJiawen Wu /* Sometimes, the power down bit doesn't clear immediately, and
332*c7b75beaSJiawen Wu * a read of this register causes the bit not to clear. Delay
333*c7b75beaSJiawen Wu * 100us to allow the PHY to come out of power down mode before
334*c7b75beaSJiawen Wu * the next access.
335*c7b75beaSJiawen Wu */
336*c7b75beaSJiawen Wu udelay(100);
337*c7b75beaSJiawen Wu
338829e7573SBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
339829e7573SBaruch Siach priv->firmware_ver < 0x00030000)
3408f48c2acSRussell King return ret;
3418f48c2acSRussell King
3428f48c2acSRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
3439893f316SMarek Behún MV_V2_33X0_PORT_CTRL_SWRST);
344c9cc1c81SRussell King }
345c9cc1c81SRussell King
mv3310_reset(struct phy_device * phydev,u32 unit)3468d8963c3SRussell King static int mv3310_reset(struct phy_device *phydev, u32 unit)
3478d8963c3SRussell King {
3488964a217SDejin Zheng int val, err;
3498d8963c3SRussell King
3508d8963c3SRussell King err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
3518d8963c3SRussell King MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
3528d8963c3SRussell King if (err < 0)
3538d8963c3SRussell King return err;
3548d8963c3SRussell King
3558964a217SDejin Zheng return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
3568964a217SDejin Zheng unit + MDIO_CTRL1, val,
3578964a217SDejin Zheng !(val & MDIO_CTRL1_RESET),
3588964a217SDejin Zheng 5000, 100000, true);
3598d8963c3SRussell King }
3608d8963c3SRussell King
mv3310_get_downshift(struct phy_device * phydev,u8 * ds)3614075a6a0SRussell King static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
3624075a6a0SRussell King {
3634075a6a0SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
3644075a6a0SRussell King int val;
3654075a6a0SRussell King
3664075a6a0SRussell King if (!priv->has_downshift)
3674075a6a0SRussell King return -EOPNOTSUPP;
3684075a6a0SRussell King
3694075a6a0SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
3704075a6a0SRussell King if (val < 0)
3714075a6a0SRussell King return val;
3724075a6a0SRussell King
3734075a6a0SRussell King if (val & MV_PCS_DSC1_ENABLE)
3744075a6a0SRussell King /* assume that all fields are the same */
3754075a6a0SRussell King *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
3764075a6a0SRussell King else
3774075a6a0SRussell King *ds = DOWNSHIFT_DEV_DISABLE;
3784075a6a0SRussell King
3794075a6a0SRussell King return 0;
3804075a6a0SRussell King }
3814075a6a0SRussell King
mv3310_set_downshift(struct phy_device * phydev,u8 ds)3824075a6a0SRussell King static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
3834075a6a0SRussell King {
3844075a6a0SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
3854075a6a0SRussell King u16 val;
3864075a6a0SRussell King int err;
3874075a6a0SRussell King
3884075a6a0SRussell King if (!priv->has_downshift)
3894075a6a0SRussell King return -EOPNOTSUPP;
3904075a6a0SRussell King
3914075a6a0SRussell King if (ds == DOWNSHIFT_DEV_DISABLE)
3924075a6a0SRussell King return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
3934075a6a0SRussell King MV_PCS_DSC1_ENABLE);
3944075a6a0SRussell King
3954075a6a0SRussell King /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
3964075a6a0SRussell King * set the default settings for the PHY. However, it is used for
3974075a6a0SRussell King * "ethtool --set-phy-tunable ethN downshift on". The intention is
3984075a6a0SRussell King * to enable downshift at a default number of retries. The default
3994075a6a0SRussell King * settings for 88x3310 are for two retries with downshift disabled.
4004075a6a0SRussell King * So let's use two retries with downshift enabled.
4014075a6a0SRussell King */
4024075a6a0SRussell King if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
4034075a6a0SRussell King ds = 2;
4044075a6a0SRussell King
4054075a6a0SRussell King if (ds > 8)
4064075a6a0SRussell King return -E2BIG;
4074075a6a0SRussell King
4084075a6a0SRussell King ds -= 1;
4094075a6a0SRussell King val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
4104075a6a0SRussell King val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
4114075a6a0SRussell King err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
4124075a6a0SRussell King MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
4134075a6a0SRussell King if (err < 0)
4144075a6a0SRussell King return err;
4154075a6a0SRussell King
4164075a6a0SRussell King val = MV_PCS_DSC1_ENABLE;
4174075a6a0SRussell King val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
4184075a6a0SRussell King val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
4194075a6a0SRussell King val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
4204075a6a0SRussell King
4214075a6a0SRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
4224075a6a0SRussell King MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
4234075a6a0SRussell King MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
4244075a6a0SRussell King }
4254075a6a0SRussell King
mv3310_get_edpd(struct phy_device * phydev,u16 * edpd)426a585c03eSRussell King static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
427a585c03eSRussell King {
428a585c03eSRussell King int val;
429a585c03eSRussell King
430a585c03eSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
431a585c03eSRussell King if (val < 0)
432a585c03eSRussell King return val;
433a585c03eSRussell King
434a585c03eSRussell King switch (val & MV_PCS_CSCR1_ED_MASK) {
435a585c03eSRussell King case MV_PCS_CSCR1_ED_NLP:
436a585c03eSRussell King *edpd = 1000;
437a585c03eSRussell King break;
438a585c03eSRussell King case MV_PCS_CSCR1_ED_RX:
439a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_NO_TX;
440a585c03eSRussell King break;
441a585c03eSRussell King default:
442a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_DISABLE;
443a585c03eSRussell King break;
444a585c03eSRussell King }
445a585c03eSRussell King return 0;
446a585c03eSRussell King }
447a585c03eSRussell King
mv3310_set_edpd(struct phy_device * phydev,u16 edpd)448a585c03eSRussell King static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
449a585c03eSRussell King {
450a585c03eSRussell King u16 val;
451a585c03eSRussell King int err;
452a585c03eSRussell King
453a585c03eSRussell King switch (edpd) {
454a585c03eSRussell King case 1000:
455a585c03eSRussell King case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
456a585c03eSRussell King val = MV_PCS_CSCR1_ED_NLP;
457a585c03eSRussell King break;
458a585c03eSRussell King
459a585c03eSRussell King case ETHTOOL_PHY_EDPD_NO_TX:
460a585c03eSRussell King val = MV_PCS_CSCR1_ED_RX;
461a585c03eSRussell King break;
462a585c03eSRussell King
463a585c03eSRussell King case ETHTOOL_PHY_EDPD_DISABLE:
464a585c03eSRussell King val = MV_PCS_CSCR1_ED_OFF;
465a585c03eSRussell King break;
466a585c03eSRussell King
467a585c03eSRussell King default:
468a585c03eSRussell King return -EINVAL;
469a585c03eSRussell King }
470a585c03eSRussell King
471a585c03eSRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
472a585c03eSRussell King MV_PCS_CSCR1_ED_MASK, val);
473a585c03eSRussell King if (err > 0)
474a585c03eSRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T);
475a585c03eSRussell King
476a585c03eSRussell King return err;
477a585c03eSRussell King }
478a585c03eSRussell King
mv3310_sfp_insert(void * upstream,const struct sfp_eeprom_id * id)47936023da1SRussell King static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
48036023da1SRussell King {
48136023da1SRussell King struct phy_device *phydev = upstream;
48236023da1SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
483fd580c98SRussell King DECLARE_PHY_INTERFACE_MASK(interfaces);
48436023da1SRussell King phy_interface_t iface;
48536023da1SRussell King
486fd580c98SRussell King sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
487a4516c70SRussell King iface = sfp_select_interface(phydev->sfp_bus, support);
48836023da1SRussell King
489e0f909bcSRussell King if (iface != PHY_INTERFACE_MODE_10GBASER) {
49036023da1SRussell King dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
49136023da1SRussell King return -EINVAL;
49236023da1SRussell King }
49336023da1SRussell King return 0;
49436023da1SRussell King }
49536023da1SRussell King
49636023da1SRussell King static const struct sfp_upstream_ops mv3310_sfp_ops = {
49736023da1SRussell King .attach = phy_sfp_attach,
49836023da1SRussell King .detach = phy_sfp_detach,
49936023da1SRussell King .module_insert = mv3310_sfp_insert,
50036023da1SRussell King };
50136023da1SRussell King
mv3310_probe(struct phy_device * phydev)50220b2af32SRussell King static int mv3310_probe(struct phy_device *phydev)
50320b2af32SRussell King {
504261a74c6SMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev);
5050d3ad854SRussell King struct mv3310_priv *priv;
50620b2af32SRussell King u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
5070d3ad854SRussell King int ret;
50820b2af32SRussell King
50920b2af32SRussell King if (!phydev->is_c45 ||
51020b2af32SRussell King (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
51120b2af32SRussell King return -ENODEV;
51220b2af32SRussell King
5133d3ced2eSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
5143d3ced2eSRussell King if (ret < 0)
5153d3ced2eSRussell King return ret;
5163d3ced2eSRussell King
5173d3ced2eSRussell King if (ret & MV_PMA_BOOT_FATAL) {
5183d3ced2eSRussell King dev_warn(&phydev->mdio.dev,
5193d3ced2eSRussell King "PHY failed to boot firmware, status=%04x\n", ret);
5203d3ced2eSRussell King return -ENODEV;
5213d3ced2eSRussell King }
5223d3ced2eSRussell King
5230d3ad854SRussell King priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
5240d3ad854SRussell King if (!priv)
5250d3ad854SRussell King return -ENOMEM;
5260d3ad854SRussell King
5270d3ad854SRussell King dev_set_drvdata(&phydev->mdio.dev, priv);
5280d3ad854SRussell King
529dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
530dd649b4fSRussell King if (ret < 0)
531dd649b4fSRussell King return ret;
532dd649b4fSRussell King
533dd649b4fSRussell King priv->firmware_ver = ret << 16;
534dd649b4fSRussell King
535dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
536dd649b4fSRussell King if (ret < 0)
537dd649b4fSRussell King return ret;
538dd649b4fSRussell King
539dd649b4fSRussell King priv->firmware_ver |= ret;
540dd649b4fSRussell King
541dd649b4fSRussell King phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
542dd649b4fSRussell King priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
543dd649b4fSRussell King (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
544dd649b4fSRussell King
5454075a6a0SRussell King if (chip->has_downshift)
5464075a6a0SRussell King priv->has_downshift = chip->has_downshift(phydev);
5474075a6a0SRussell King
548c9cc1c81SRussell King /* Powering down the port when not in use saves about 600mW */
549c9cc1c81SRussell King ret = mv3310_power_down(phydev);
550c9cc1c81SRussell King if (ret)
551c9cc1c81SRussell King return ret;
552c9cc1c81SRussell King
5530d3ad854SRussell King ret = mv3310_hwmon_probe(phydev);
5540d3ad854SRussell King if (ret)
5550d3ad854SRussell King return ret;
5560d3ad854SRussell King
557261a74c6SMarek Behún chip->init_supported_interfaces(priv->supported_interfaces);
558261a74c6SMarek Behún
55936023da1SRussell King return phy_sfp_probe(phydev, &mv3310_sfp_ops);
56020b2af32SRussell King }
56120b2af32SRussell King
mv3310_remove(struct phy_device * phydev)5621b8ef142SMarek Behún static void mv3310_remove(struct phy_device *phydev)
5631b8ef142SMarek Behún {
5641b8ef142SMarek Behún mv3310_hwmon_config(phydev, false);
5651b8ef142SMarek Behún }
5661b8ef142SMarek Behún
mv3310_suspend(struct phy_device * phydev)5670d3ad854SRussell King static int mv3310_suspend(struct phy_device *phydev)
5680d3ad854SRussell King {
569c9cc1c81SRussell King return mv3310_power_down(phydev);
5700d3ad854SRussell King }
5710d3ad854SRussell King
mv3310_resume(struct phy_device * phydev)5720d3ad854SRussell King static int mv3310_resume(struct phy_device *phydev)
5730d3ad854SRussell King {
574af3e28cbSAntoine Tenart int ret;
575af3e28cbSAntoine Tenart
576c9cc1c81SRussell King ret = mv3310_power_up(phydev);
577af3e28cbSAntoine Tenart if (ret)
578af3e28cbSAntoine Tenart return ret;
579af3e28cbSAntoine Tenart
5800d3ad854SRussell King return mv3310_hwmon_config(phydev, true);
5810d3ad854SRussell King }
5820d3ad854SRussell King
583c47455f9SMaxime Chevallier /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
584c47455f9SMaxime Chevallier * don't set bit 14 in PMA Extended Abilities (1.11), although they do
585c47455f9SMaxime Chevallier * support 2.5GBASET and 5GBASET. For these models, we can still read their
586c47455f9SMaxime Chevallier * 2.5G/5G extended abilities register (1.21). We detect these models based on
587c47455f9SMaxime Chevallier * the PMA device identifier, with a mask matching models known to have this
588c47455f9SMaxime Chevallier * issue
589c47455f9SMaxime Chevallier */
mv3310_has_pma_ngbaset_quirk(struct phy_device * phydev)590c47455f9SMaxime Chevallier static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
591c47455f9SMaxime Chevallier {
592c47455f9SMaxime Chevallier if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
593c47455f9SMaxime Chevallier return false;
594c47455f9SMaxime Chevallier
595c47455f9SMaxime Chevallier /* Only some revisions of the 88X3310 family PMA seem to be impacted */
596c47455f9SMaxime Chevallier return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
597c47455f9SMaxime Chevallier MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
598c47455f9SMaxime Chevallier }
599c47455f9SMaxime Chevallier
mv2110_get_mactype(struct phy_device * phydev)60097bbe3bdSMarek Behún static int mv2110_get_mactype(struct phy_device *phydev)
60197bbe3bdSMarek Behún {
60297bbe3bdSMarek Behún int mactype;
60397bbe3bdSMarek Behún
60497bbe3bdSMarek Behún mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
60597bbe3bdSMarek Behún if (mactype < 0)
60697bbe3bdSMarek Behún return mactype;
60797bbe3bdSMarek Behún
60897bbe3bdSMarek Behún return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
60997bbe3bdSMarek Behún }
61097bbe3bdSMarek Behún
mv2110_set_mactype(struct phy_device * phydev,int mactype)611d6d29292SRussell King static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
612d6d29292SRussell King {
613d6d29292SRussell King int err, val;
614d6d29292SRussell King
615d6d29292SRussell King mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
616d6d29292SRussell King err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
617d6d29292SRussell King MV_PMA_21X0_PORT_CTRL_SWRST |
618d6d29292SRussell King MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
619d6d29292SRussell King MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
620d6d29292SRussell King if (err)
621d6d29292SRussell King return err;
622d6d29292SRussell King
623d6d29292SRussell King err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
624d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
625d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
626d6d29292SRussell King if (err)
627d6d29292SRussell King return err;
628d6d29292SRussell King
629d6d29292SRussell King err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
630d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2, val,
631d6d29292SRussell King !(val &
632d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
633d6d29292SRussell King 5000, 100000, true);
634d6d29292SRussell King if (err)
635d6d29292SRussell King return err;
636d6d29292SRussell King
637d6d29292SRussell King return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
638d6d29292SRussell King MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
639d6d29292SRussell King }
640d6d29292SRussell King
mv2110_select_mactype(unsigned long * interfaces)641d6d29292SRussell King static int mv2110_select_mactype(unsigned long *interfaces)
642d6d29292SRussell King {
643d6d29292SRussell King if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
644d6d29292SRussell King return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
645d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
646d6d29292SRussell King !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
647d6d29292SRussell King return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
648d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
649d6d29292SRussell King return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
650d6d29292SRussell King else
651d6d29292SRussell King return -1;
652d6d29292SRussell King }
653d6d29292SRussell King
mv3310_get_mactype(struct phy_device * phydev)65497bbe3bdSMarek Behún static int mv3310_get_mactype(struct phy_device *phydev)
65597bbe3bdSMarek Behún {
65697bbe3bdSMarek Behún int mactype;
65797bbe3bdSMarek Behún
65897bbe3bdSMarek Behún mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
65997bbe3bdSMarek Behún if (mactype < 0)
66097bbe3bdSMarek Behún return mactype;
66197bbe3bdSMarek Behún
66297bbe3bdSMarek Behún return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
66397bbe3bdSMarek Behún }
66497bbe3bdSMarek Behún
mv3310_set_mactype(struct phy_device * phydev,int mactype)665d6d29292SRussell King static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
666d6d29292SRussell King {
667d6d29292SRussell King int ret;
668d6d29292SRussell King
669d6d29292SRussell King mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
670d6d29292SRussell King ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
671d6d29292SRussell King MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
672d6d29292SRussell King mactype);
673d6d29292SRussell King if (ret <= 0)
674d6d29292SRussell King return ret;
675d6d29292SRussell King
676d6d29292SRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
677d6d29292SRussell King MV_V2_33X0_PORT_CTRL_SWRST);
678d6d29292SRussell King }
679d6d29292SRussell King
mv3310_select_mactype(unsigned long * interfaces)680d6d29292SRussell King static int mv3310_select_mactype(unsigned long *interfaces)
681d6d29292SRussell King {
682d6d29292SRussell King if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
683d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
684d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
685d6d29292SRussell King test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
686d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
687d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
688d6d29292SRussell King test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
689d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
690d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
691d6d29292SRussell King test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
692d6d29292SRussell King return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
693d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
694d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
695d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
696d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
697d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
698d6d29292SRussell King return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
699d6d29292SRussell King else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces))
700d6d29292SRussell King return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
701d6d29292SRussell King else
702d6d29292SRussell King return -1;
703d6d29292SRussell King }
704d6d29292SRussell King
mv2110_init_interface(struct phy_device * phydev,int mactype)70597bbe3bdSMarek Behún static int mv2110_init_interface(struct phy_device *phydev, int mactype)
70620b2af32SRussell King {
707e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
70897bbe3bdSMarek Behún
70997bbe3bdSMarek Behún priv->rate_match = false;
71097bbe3bdSMarek Behún
711ccbf2891SMarek Behún if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
71297bbe3bdSMarek Behún priv->rate_match = true;
713ccbf2891SMarek Behún
714ccbf2891SMarek Behún if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
715ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
716ccbf2891SMarek Behún else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
71797bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
718ccbf2891SMarek Behún else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
719ccbf2891SMarek Behún mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
720ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_NA;
721ccbf2891SMarek Behún else
722ccbf2891SMarek Behún return -EINVAL;
72397bbe3bdSMarek Behún
72497bbe3bdSMarek Behún return 0;
72597bbe3bdSMarek Behún }
72697bbe3bdSMarek Behún
mv3310_init_interface(struct phy_device * phydev,int mactype)72797bbe3bdSMarek Behún static int mv3310_init_interface(struct phy_device *phydev, int mactype)
72897bbe3bdSMarek Behún {
72997bbe3bdSMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
73097bbe3bdSMarek Behún
73197bbe3bdSMarek Behún priv->rate_match = false;
73297bbe3bdSMarek Behún
73397bbe3bdSMarek Behún if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
73497bbe3bdSMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
73597bbe3bdSMarek Behún mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
73697bbe3bdSMarek Behún priv->rate_match = true;
73797bbe3bdSMarek Behún
738ccbf2891SMarek Behún if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
739ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
740ccbf2891SMarek Behún else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
741ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
742ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
74397bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
744ccbf2891SMarek Behún else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
745ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
74697bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
747ccbf2891SMarek Behún else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
748ccbf2891SMarek Behún mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
74997bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_XAUI;
750ccbf2891SMarek Behún else
751ccbf2891SMarek Behún return -EINVAL;
75297bbe3bdSMarek Behún
75397bbe3bdSMarek Behún return 0;
75497bbe3bdSMarek Behún }
75597bbe3bdSMarek Behún
mv3340_init_interface(struct phy_device * phydev,int mactype)7569885d016SMarek Behún static int mv3340_init_interface(struct phy_device *phydev, int mactype)
7579885d016SMarek Behún {
7589885d016SMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
7599885d016SMarek Behún int err = 0;
7609885d016SMarek Behún
7619885d016SMarek Behún priv->rate_match = false;
7629885d016SMarek Behún
7639885d016SMarek Behún if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
7649885d016SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
7659885d016SMarek Behún else
7669885d016SMarek Behún err = mv3310_init_interface(phydev, mactype);
7679885d016SMarek Behún
7689885d016SMarek Behún return err;
7699885d016SMarek Behún }
7709885d016SMarek Behún
mv3310_config_init(struct phy_device * phydev)77197bbe3bdSMarek Behún static int mv3310_config_init(struct phy_device *phydev)
77297bbe3bdSMarek Behún {
773261a74c6SMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
77497bbe3bdSMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev);
77597bbe3bdSMarek Behún int err, mactype;
776c9cc1c81SRussell King
77720b2af32SRussell King /* Check that the PHY interface type is compatible */
778261a74c6SMarek Behún if (!test_bit(phydev->interface, priv->supported_interfaces))
77920b2af32SRussell King return -ENODEV;
78020b2af32SRussell King
7818d8963c3SRussell King phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
7828d8963c3SRussell King
783c9cc1c81SRussell King /* Power up so reset works */
784c9cc1c81SRussell King err = mv3310_power_up(phydev);
785c9cc1c81SRussell King if (err)
786c9cc1c81SRussell King return err;
787c9cc1c81SRussell King
788d6d29292SRussell King /* If host provided host supported interface modes, try to select the
789d6d29292SRussell King * best one
790d6d29292SRussell King */
791d6d29292SRussell King if (!phy_interface_empty(phydev->host_interfaces)) {
792d6d29292SRussell King mactype = chip->select_mactype(phydev->host_interfaces);
793d6d29292SRussell King if (mactype >= 0) {
794d6d29292SRussell King phydev_info(phydev, "Changing MACTYPE to %i\n",
795d6d29292SRussell King mactype);
796d6d29292SRussell King err = chip->set_mactype(phydev, mactype);
797d6d29292SRussell King if (err)
798d6d29292SRussell King return err;
799d6d29292SRussell King }
800d6d29292SRussell King }
801d6d29292SRussell King
80297bbe3bdSMarek Behún mactype = chip->get_mactype(phydev);
80397bbe3bdSMarek Behún if (mactype < 0)
80497bbe3bdSMarek Behún return mactype;
80597bbe3bdSMarek Behún
80697bbe3bdSMarek Behún err = chip->init_interface(phydev, mactype);
807ccbf2891SMarek Behún if (err) {
808ccbf2891SMarek Behún phydev_err(phydev, "MACTYPE configuration invalid\n");
80997bbe3bdSMarek Behún return err;
810ccbf2891SMarek Behún }
811e1170333SBaruch Siach
812a585c03eSRussell King /* Enable EDPD mode - saving 600mW */
8134075a6a0SRussell King err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
8144075a6a0SRussell King if (err)
8154075a6a0SRussell King return err;
8164075a6a0SRussell King
8174075a6a0SRussell King /* Allow downshift */
8184075a6a0SRussell King err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
8194075a6a0SRussell King if (err && err != -EOPNOTSUPP)
8204075a6a0SRussell King return err;
8214075a6a0SRussell King
8224075a6a0SRussell King return 0;
82374145424SMaxime Chevallier }
82474145424SMaxime Chevallier
mv3310_get_features(struct phy_device * phydev)82574145424SMaxime Chevallier static int mv3310_get_features(struct phy_device *phydev)
82674145424SMaxime Chevallier {
82774145424SMaxime Chevallier int ret, val;
82874145424SMaxime Chevallier
829ac3f5533SMaxime Chevallier ret = genphy_c45_pma_read_abilities(phydev);
830ac3f5533SMaxime Chevallier if (ret)
831ac3f5533SMaxime Chevallier return ret;
83220b2af32SRussell King
833c47455f9SMaxime Chevallier if (mv3310_has_pma_ngbaset_quirk(phydev)) {
834c47455f9SMaxime Chevallier val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
835c47455f9SMaxime Chevallier MDIO_PMA_NG_EXTABLE);
836c47455f9SMaxime Chevallier if (val < 0)
837c47455f9SMaxime Chevallier return val;
838c47455f9SMaxime Chevallier
839c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
840c47455f9SMaxime Chevallier phydev->supported,
841c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_2_5GBT);
842c47455f9SMaxime Chevallier
843c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
844c47455f9SMaxime Chevallier phydev->supported,
845c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_5GBT);
846c47455f9SMaxime Chevallier }
847c47455f9SMaxime Chevallier
84820b2af32SRussell King return 0;
84920b2af32SRussell King }
85020b2af32SRussell King
mv3310_config_mdix(struct phy_device * phydev)8518d8963c3SRussell King static int mv3310_config_mdix(struct phy_device *phydev)
8528d8963c3SRussell King {
8538d8963c3SRussell King u16 val;
8548d8963c3SRussell King int err;
8558d8963c3SRussell King
8568d8963c3SRussell King switch (phydev->mdix_ctrl) {
8578d8963c3SRussell King case ETH_TP_MDI_AUTO:
8588d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_AUTO;
8598d8963c3SRussell King break;
8608d8963c3SRussell King case ETH_TP_MDI_X:
8618d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDIX;
8628d8963c3SRussell King break;
8638d8963c3SRussell King case ETH_TP_MDI:
8648d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDI;
8658d8963c3SRussell King break;
8668d8963c3SRussell King default:
8678d8963c3SRussell King return -EINVAL;
8688d8963c3SRussell King }
8698d8963c3SRussell King
8708d8963c3SRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
8718d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK, val);
8728d8963c3SRussell King if (err > 0)
8738d8963c3SRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T);
8748d8963c3SRussell King
8758d8963c3SRussell King return err;
8768d8963c3SRussell King }
8778d8963c3SRussell King
mv3310_config_aneg(struct phy_device * phydev)87820b2af32SRussell King static int mv3310_config_aneg(struct phy_device *phydev)
87920b2af32SRussell King {
88020b2af32SRussell King bool changed = false;
8813c1bcc86SAndrew Lunn u16 reg;
88220b2af32SRussell King int ret;
88320b2af32SRussell King
8848d8963c3SRussell King ret = mv3310_config_mdix(phydev);
8858d8963c3SRussell King if (ret < 0)
8868d8963c3SRussell King return ret;
887ea4efe25SRussell King
88830de65c3SHeiner Kallweit if (phydev->autoneg == AUTONEG_DISABLE)
88930de65c3SHeiner Kallweit return genphy_c45_pma_setup_forced(phydev);
89020b2af32SRussell King
8913de97f3cSAndrew Lunn ret = genphy_c45_an_config_aneg(phydev);
89220b2af32SRussell King if (ret < 0)
89320b2af32SRussell King return ret;
89420b2af32SRussell King if (ret > 0)
89520b2af32SRussell King changed = true;
89620b2af32SRussell King
8973de97f3cSAndrew Lunn /* Clause 45 has no standardized support for 1000BaseT, therefore
8983de97f3cSAndrew Lunn * use vendor registers for this mode.
8993de97f3cSAndrew Lunn */
9003c1bcc86SAndrew Lunn reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
901b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
9023c1bcc86SAndrew Lunn ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
90320b2af32SRussell King if (ret < 0)
90420b2af32SRussell King return ret;
90520b2af32SRussell King if (ret > 0)
90620b2af32SRussell King changed = true;
90720b2af32SRussell King
9086b4cb6cbSHeiner Kallweit return genphy_c45_check_and_restart_aneg(phydev, changed);
90920b2af32SRussell King }
91020b2af32SRussell King
mv3310_aneg_done(struct phy_device * phydev)91120b2af32SRussell King static int mv3310_aneg_done(struct phy_device *phydev)
91220b2af32SRussell King {
91320b2af32SRussell King int val;
91420b2af32SRussell King
91520b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
91620b2af32SRussell King if (val < 0)
91720b2af32SRussell King return val;
91820b2af32SRussell King
91920b2af32SRussell King if (val & MDIO_STAT1_LSTATUS)
92020b2af32SRussell King return 1;
92120b2af32SRussell King
92220b2af32SRussell King return genphy_c45_aneg_done(phydev);
92320b2af32SRussell King }
92420b2af32SRussell King
mv3310_update_interface(struct phy_device * phydev)92536c4449aSRussell King static void mv3310_update_interface(struct phy_device *phydev)
92636c4449aSRussell King {
927e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
928e1170333SBaruch Siach
929ccbf2891SMarek Behún if (!phydev->link)
930ccbf2891SMarek Behún return;
931ccbf2891SMarek Behún
93297bbe3bdSMarek Behún /* In all of the "* with Rate Matching" modes the PHY interface is fixed
93397bbe3bdSMarek Behún * at 10Gb. The PHY adapts the rate to actual wire speed with help of
934e1170333SBaruch Siach * internal 16KB buffer.
935ccbf2891SMarek Behún *
936ccbf2891SMarek Behún * In USXGMII mode the PHY interface mode is also fixed.
937e1170333SBaruch Siach */
938ccbf2891SMarek Behún if (priv->rate_match ||
939ccbf2891SMarek Behún priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
94097bbe3bdSMarek Behún phydev->interface = priv->const_interface;
941e1170333SBaruch Siach return;
942e1170333SBaruch Siach }
943e1170333SBaruch Siach
944ccbf2891SMarek Behún /* The PHY automatically switches its serdes interface (and active PHYXS
945ccbf2891SMarek Behún * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
946ccbf2891SMarek Behún * xaui / rxaui modes according to the speed.
947ccbf2891SMarek Behún * Florian suggests setting phydev->interface to communicate this to the
948ccbf2891SMarek Behún * MAC. Only do this if we are already in one of the above modes.
94936c4449aSRussell King */
950e555e5b1SMaxime Chevallier switch (phydev->speed) {
951e555e5b1SMaxime Chevallier case SPEED_10000:
952ccbf2891SMarek Behún phydev->interface = priv->const_interface;
953e555e5b1SMaxime Chevallier break;
9540d375542SMarek Behún case SPEED_5000:
9550d375542SMarek Behún phydev->interface = PHY_INTERFACE_MODE_5GBASER;
9560d375542SMarek Behún break;
957e555e5b1SMaxime Chevallier case SPEED_2500:
958e555e5b1SMaxime Chevallier phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
959e555e5b1SMaxime Chevallier break;
960e555e5b1SMaxime Chevallier case SPEED_1000:
961e555e5b1SMaxime Chevallier case SPEED_100:
962e555e5b1SMaxime Chevallier case SPEED_10:
96336c4449aSRussell King phydev->interface = PHY_INTERFACE_MODE_SGMII;
964e555e5b1SMaxime Chevallier break;
965e555e5b1SMaxime Chevallier default:
966e555e5b1SMaxime Chevallier break;
967e555e5b1SMaxime Chevallier }
96836c4449aSRussell King }
96936c4449aSRussell King
97020b2af32SRussell King /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
mv3310_read_status_10gbaser(struct phy_device * phydev)971c84786faSRussell King static int mv3310_read_status_10gbaser(struct phy_device *phydev)
97220b2af32SRussell King {
97320b2af32SRussell King phydev->link = 1;
97420b2af32SRussell King phydev->speed = SPEED_10000;
97520b2af32SRussell King phydev->duplex = DUPLEX_FULL;
9764217a64eSMichael Walle phydev->port = PORT_FIBRE;
97720b2af32SRussell King
97820b2af32SRussell King return 0;
97920b2af32SRussell King }
98020b2af32SRussell King
mv3310_read_status_copper(struct phy_device * phydev)981c84786faSRussell King static int mv3310_read_status_copper(struct phy_device *phydev)
98220b2af32SRussell King {
983c84786faSRussell King int cssr1, speed, val;
98420b2af32SRussell King
985998a8a83SHeiner Kallweit val = genphy_c45_read_link(phydev);
98620b2af32SRussell King if (val < 0)
98720b2af32SRussell King return val;
98820b2af32SRussell King
98920b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
99020b2af32SRussell King if (val < 0)
99120b2af32SRussell King return val;
99220b2af32SRussell King
993c84786faSRussell King cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
994c84786faSRussell King if (cssr1 < 0)
9950ed9704bSBaruch Siach return cssr1;
996c84786faSRussell King
997c84786faSRussell King /* If the link settings are not resolved, mark the link down */
998c84786faSRussell King if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
999c84786faSRussell King phydev->link = 0;
1000c84786faSRussell King return 0;
1001c84786faSRussell King }
1002c84786faSRussell King
1003c84786faSRussell King /* Read the copper link settings */
1004c84786faSRussell King speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
1005c84786faSRussell King if (speed == MV_PCS_CSSR1_SPD1_SPD2)
1006c84786faSRussell King speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
1007c84786faSRussell King
1008c84786faSRussell King switch (speed) {
1009c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
1010c84786faSRussell King phydev->speed = SPEED_10000;
1011c84786faSRussell King break;
1012c84786faSRussell King
1013c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
1014c84786faSRussell King phydev->speed = SPEED_5000;
1015c84786faSRussell King break;
1016c84786faSRussell King
1017c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
1018c84786faSRussell King phydev->speed = SPEED_2500;
1019c84786faSRussell King break;
1020c84786faSRussell King
1021c84786faSRussell King case MV_PCS_CSSR1_SPD1_1000:
1022c84786faSRussell King phydev->speed = SPEED_1000;
1023c84786faSRussell King break;
1024c84786faSRussell King
1025c84786faSRussell King case MV_PCS_CSSR1_SPD1_100:
1026c84786faSRussell King phydev->speed = SPEED_100;
1027c84786faSRussell King break;
1028c84786faSRussell King
1029c84786faSRussell King case MV_PCS_CSSR1_SPD1_10:
1030c84786faSRussell King phydev->speed = SPEED_10;
1031c84786faSRussell King break;
1032c84786faSRussell King }
1033c84786faSRussell King
1034c84786faSRussell King phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1035c84786faSRussell King DUPLEX_FULL : DUPLEX_HALF;
10364217a64eSMichael Walle phydev->port = PORT_TP;
1037c84786faSRussell King phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1038c84786faSRussell King ETH_TP_MDI_X : ETH_TP_MDI;
1039c84786faSRussell King
104020b2af32SRussell King if (val & MDIO_AN_STAT1_COMPLETE) {
104120b2af32SRussell King val = genphy_c45_read_lpa(phydev);
104220b2af32SRussell King if (val < 0)
104320b2af32SRussell King return val;
104420b2af32SRussell King
1045cc1122b0SColin Ian King /* Read the link partner's 1G advertisement */
104620b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
104720b2af32SRussell King if (val < 0)
104820b2af32SRussell King return val;
104920b2af32SRussell King
105078a24df3SAndrew Lunn mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
105120b2af32SRussell King
1052c84786faSRussell King /* Update the pause status */
1053c84786faSRussell King phy_resolve_aneg_pause(phydev);
105420b2af32SRussell King }
105520b2af32SRussell King
1056c84786faSRussell King return 0;
105720b2af32SRussell King }
105820b2af32SRussell King
mv3310_read_status(struct phy_device * phydev)1059c84786faSRussell King static int mv3310_read_status(struct phy_device *phydev)
1060c84786faSRussell King {
1061c84786faSRussell King int err, val;
1062ea4efe25SRussell King
1063c84786faSRussell King phydev->speed = SPEED_UNKNOWN;
1064c84786faSRussell King phydev->duplex = DUPLEX_UNKNOWN;
1065c84786faSRussell King linkmode_zero(phydev->lp_advertising);
1066c84786faSRussell King phydev->link = 0;
1067c84786faSRussell King phydev->pause = 0;
1068c84786faSRussell King phydev->asym_pause = 0;
1069ea4efe25SRussell King phydev->mdix = ETH_TP_MDI_INVALID;
1070ea4efe25SRussell King
1071c84786faSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1072c84786faSRussell King if (val < 0)
1073c84786faSRussell King return val;
1074c84786faSRussell King
1075c84786faSRussell King if (val & MDIO_STAT1_LSTATUS)
1076c84786faSRussell King err = mv3310_read_status_10gbaser(phydev);
1077c84786faSRussell King else
1078c84786faSRussell King err = mv3310_read_status_copper(phydev);
1079c84786faSRussell King if (err < 0)
1080c84786faSRussell King return err;
1081c84786faSRussell King
1082c84786faSRussell King if (phydev->link)
108336c4449aSRussell King mv3310_update_interface(phydev);
108420b2af32SRussell King
108520b2af32SRussell King return 0;
108620b2af32SRussell King }
108720b2af32SRussell King
mv3310_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)1088a585c03eSRussell King static int mv3310_get_tunable(struct phy_device *phydev,
1089a585c03eSRussell King struct ethtool_tunable *tuna, void *data)
1090a585c03eSRussell King {
1091a585c03eSRussell King switch (tuna->id) {
10924075a6a0SRussell King case ETHTOOL_PHY_DOWNSHIFT:
10934075a6a0SRussell King return mv3310_get_downshift(phydev, data);
1094a585c03eSRussell King case ETHTOOL_PHY_EDPD:
1095a585c03eSRussell King return mv3310_get_edpd(phydev, data);
1096a585c03eSRussell King default:
1097a585c03eSRussell King return -EOPNOTSUPP;
1098a585c03eSRussell King }
1099a585c03eSRussell King }
1100a585c03eSRussell King
mv3310_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)1101a585c03eSRussell King static int mv3310_set_tunable(struct phy_device *phydev,
1102a585c03eSRussell King struct ethtool_tunable *tuna, const void *data)
1103a585c03eSRussell King {
1104a585c03eSRussell King switch (tuna->id) {
11054075a6a0SRussell King case ETHTOOL_PHY_DOWNSHIFT:
11064075a6a0SRussell King return mv3310_set_downshift(phydev, *(u8 *)data);
1107a585c03eSRussell King case ETHTOOL_PHY_EDPD:
1108a585c03eSRussell King return mv3310_set_edpd(phydev, *(u16 *)data);
1109a585c03eSRussell King default:
1110a585c03eSRussell King return -EOPNOTSUPP;
1111a585c03eSRussell King }
1112a585c03eSRussell King }
1113a585c03eSRussell King
mv3310_has_downshift(struct phy_device * phydev)11144075a6a0SRussell King static bool mv3310_has_downshift(struct phy_device *phydev)
11154075a6a0SRussell King {
11164075a6a0SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
11174075a6a0SRussell King
11184075a6a0SRussell King /* Fails to downshift with firmware older than v0.3.5.0 */
11194075a6a0SRussell King return priv->firmware_ver >= MV_VERSION(0,3,5,0);
11204075a6a0SRussell King }
11214075a6a0SRussell King
mv3310_init_supported_interfaces(unsigned long * mask)1122261a74c6SMarek Behún static void mv3310_init_supported_interfaces(unsigned long *mask)
1123261a74c6SMarek Behún {
1124261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1125261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1126261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1127261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
1128261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1129261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1130261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1131261a74c6SMarek Behún }
1132261a74c6SMarek Behún
mv3340_init_supported_interfaces(unsigned long * mask)11339885d016SMarek Behún static void mv3340_init_supported_interfaces(unsigned long *mask)
11349885d016SMarek Behún {
11359885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
11369885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
11379885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
11389885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
11399885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
11409885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
11419885d016SMarek Behún }
11429885d016SMarek Behún
mv2110_init_supported_interfaces(unsigned long * mask)1143261a74c6SMarek Behún static void mv2110_init_supported_interfaces(unsigned long *mask)
1144261a74c6SMarek Behún {
1145261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1146261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1147261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1148261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1149261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1150261a74c6SMarek Behún }
1151261a74c6SMarek Behún
mv2111_init_supported_interfaces(unsigned long * mask)11520fca947cSMarek Behún static void mv2111_init_supported_interfaces(unsigned long *mask)
11530fca947cSMarek Behún {
11540fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
11550fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
11560fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
11570fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
11580fca947cSMarek Behún }
11590fca947cSMarek Behún
116097bbe3bdSMarek Behún static const struct mv3310_chip mv3310_type = {
11614075a6a0SRussell King .has_downshift = mv3310_has_downshift,
1162261a74c6SMarek Behún .init_supported_interfaces = mv3310_init_supported_interfaces,
116397bbe3bdSMarek Behún .get_mactype = mv3310_get_mactype,
1164d6d29292SRussell King .set_mactype = mv3310_set_mactype,
1165d6d29292SRussell King .select_mactype = mv3310_select_mactype,
116697bbe3bdSMarek Behún .init_interface = mv3310_init_interface,
1167884d9a67SMarek Behún
1168884d9a67SMarek Behún #ifdef CONFIG_HWMON
1169884d9a67SMarek Behún .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1170884d9a67SMarek Behún #endif
117197bbe3bdSMarek Behún };
117297bbe3bdSMarek Behún
11739885d016SMarek Behún static const struct mv3310_chip mv3340_type = {
11744075a6a0SRussell King .has_downshift = mv3310_has_downshift,
11759885d016SMarek Behún .init_supported_interfaces = mv3340_init_supported_interfaces,
11769885d016SMarek Behún .get_mactype = mv3310_get_mactype,
1177d6d29292SRussell King .set_mactype = mv3310_set_mactype,
1178d6d29292SRussell King .select_mactype = mv3310_select_mactype,
11799885d016SMarek Behún .init_interface = mv3340_init_interface,
11809885d016SMarek Behún
11819885d016SMarek Behún #ifdef CONFIG_HWMON
11829885d016SMarek Behún .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
11839885d016SMarek Behún #endif
11849885d016SMarek Behún };
11859885d016SMarek Behún
118697bbe3bdSMarek Behún static const struct mv3310_chip mv2110_type = {
1187261a74c6SMarek Behún .init_supported_interfaces = mv2110_init_supported_interfaces,
118897bbe3bdSMarek Behún .get_mactype = mv2110_get_mactype,
1189d6d29292SRussell King .set_mactype = mv2110_set_mactype,
1190d6d29292SRussell King .select_mactype = mv2110_select_mactype,
119197bbe3bdSMarek Behún .init_interface = mv2110_init_interface,
1192884d9a67SMarek Behún
1193884d9a67SMarek Behún #ifdef CONFIG_HWMON
1194884d9a67SMarek Behún .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1195884d9a67SMarek Behún #endif
119697bbe3bdSMarek Behún };
119797bbe3bdSMarek Behún
11980fca947cSMarek Behún static const struct mv3310_chip mv2111_type = {
11990fca947cSMarek Behún .init_supported_interfaces = mv2111_init_supported_interfaces,
12000fca947cSMarek Behún .get_mactype = mv2110_get_mactype,
1201d6d29292SRussell King .set_mactype = mv2110_set_mactype,
1202d6d29292SRussell King .select_mactype = mv2110_select_mactype,
12030fca947cSMarek Behún .init_interface = mv2110_init_interface,
12040fca947cSMarek Behún
12050fca947cSMarek Behún #ifdef CONFIG_HWMON
12060fca947cSMarek Behún .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
12070fca947cSMarek Behún #endif
12080fca947cSMarek Behún };
12090fca947cSMarek Behún
mv3310_get_number_of_ports(struct phy_device * phydev)1210a5de4be0SMarek Behún static int mv3310_get_number_of_ports(struct phy_device *phydev)
1211a5de4be0SMarek Behún {
1212a5de4be0SMarek Behún int ret;
1213a5de4be0SMarek Behún
1214a5de4be0SMarek Behún ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1215a5de4be0SMarek Behún if (ret < 0)
1216a5de4be0SMarek Behún return ret;
1217a5de4be0SMarek Behún
1218a5de4be0SMarek Behún ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1219a5de4be0SMarek Behún ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1220a5de4be0SMarek Behún
1221a5de4be0SMarek Behún return ret + 1;
1222a5de4be0SMarek Behún }
1223a5de4be0SMarek Behún
mv3310_match_phy_device(struct phy_device * phydev)1224a5de4be0SMarek Behún static int mv3310_match_phy_device(struct phy_device *phydev)
1225a5de4be0SMarek Behún {
12260d55649dSVladimir Oltean if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
12270d55649dSVladimir Oltean MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
12280d55649dSVladimir Oltean return 0;
12290d55649dSVladimir Oltean
1230a5de4be0SMarek Behún return mv3310_get_number_of_ports(phydev) == 1;
1231a5de4be0SMarek Behún }
1232a5de4be0SMarek Behún
mv3340_match_phy_device(struct phy_device * phydev)1233a5de4be0SMarek Behún static int mv3340_match_phy_device(struct phy_device *phydev)
1234a5de4be0SMarek Behún {
12350d55649dSVladimir Oltean if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
12360d55649dSVladimir Oltean MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
12370d55649dSVladimir Oltean return 0;
12380d55649dSVladimir Oltean
1239a5de4be0SMarek Behún return mv3310_get_number_of_ports(phydev) == 4;
1240a5de4be0SMarek Behún }
1241a5de4be0SMarek Behún
mv211x_match_phy_device(struct phy_device * phydev,bool has_5g)12420fca947cSMarek Behún static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
12430fca947cSMarek Behún {
12440fca947cSMarek Behún int val;
12450fca947cSMarek Behún
12460fca947cSMarek Behún if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
12470fca947cSMarek Behún MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
12480fca947cSMarek Behún return 0;
12490fca947cSMarek Behún
12500fca947cSMarek Behún val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
12510fca947cSMarek Behún if (val < 0)
12520fca947cSMarek Behún return val;
12530fca947cSMarek Behún
12540fca947cSMarek Behún return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
12550fca947cSMarek Behún }
12560fca947cSMarek Behún
mv2110_match_phy_device(struct phy_device * phydev)12570fca947cSMarek Behún static int mv2110_match_phy_device(struct phy_device *phydev)
12580fca947cSMarek Behún {
12590fca947cSMarek Behún return mv211x_match_phy_device(phydev, true);
12600fca947cSMarek Behún }
12610fca947cSMarek Behún
mv2111_match_phy_device(struct phy_device * phydev)12620fca947cSMarek Behún static int mv2111_match_phy_device(struct phy_device *phydev)
12630fca947cSMarek Behún {
12640fca947cSMarek Behún return mv211x_match_phy_device(phydev, false);
12650fca947cSMarek Behún }
12660fca947cSMarek Behún
mv3110_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)126708041a9aSVoon Weifeng static void mv3110_get_wol(struct phy_device *phydev,
126808041a9aSVoon Weifeng struct ethtool_wolinfo *wol)
126908041a9aSVoon Weifeng {
127008041a9aSVoon Weifeng int ret;
127108041a9aSVoon Weifeng
127208041a9aSVoon Weifeng wol->supported = WAKE_MAGIC;
127308041a9aSVoon Weifeng wol->wolopts = 0;
127408041a9aSVoon Weifeng
127508041a9aSVoon Weifeng ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
127608041a9aSVoon Weifeng if (ret < 0)
127708041a9aSVoon Weifeng return;
127808041a9aSVoon Weifeng
127908041a9aSVoon Weifeng if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
128008041a9aSVoon Weifeng wol->wolopts |= WAKE_MAGIC;
128108041a9aSVoon Weifeng }
128208041a9aSVoon Weifeng
mv3110_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)128308041a9aSVoon Weifeng static int mv3110_set_wol(struct phy_device *phydev,
128408041a9aSVoon Weifeng struct ethtool_wolinfo *wol)
128508041a9aSVoon Weifeng {
128608041a9aSVoon Weifeng int ret;
128708041a9aSVoon Weifeng
128808041a9aSVoon Weifeng if (wol->wolopts & WAKE_MAGIC) {
128908041a9aSVoon Weifeng /* Enable the WOL interrupt */
129008041a9aSVoon Weifeng ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
129108041a9aSVoon Weifeng MV_V2_PORT_INTR_MASK,
129208041a9aSVoon Weifeng MV_V2_PORT_INTR_STS_WOL_EN);
129308041a9aSVoon Weifeng if (ret < 0)
129408041a9aSVoon Weifeng return ret;
129508041a9aSVoon Weifeng
129608041a9aSVoon Weifeng /* Store the device address for the magic packet */
129708041a9aSVoon Weifeng ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
129808041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD2,
129908041a9aSVoon Weifeng ((phydev->attached_dev->dev_addr[5] << 8) |
130008041a9aSVoon Weifeng phydev->attached_dev->dev_addr[4]));
130108041a9aSVoon Weifeng if (ret < 0)
130208041a9aSVoon Weifeng return ret;
130308041a9aSVoon Weifeng
130408041a9aSVoon Weifeng ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
130508041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD1,
130608041a9aSVoon Weifeng ((phydev->attached_dev->dev_addr[3] << 8) |
130708041a9aSVoon Weifeng phydev->attached_dev->dev_addr[2]));
130808041a9aSVoon Weifeng if (ret < 0)
130908041a9aSVoon Weifeng return ret;
131008041a9aSVoon Weifeng
131108041a9aSVoon Weifeng ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
131208041a9aSVoon Weifeng MV_V2_MAGIC_PKT_WORD0,
131308041a9aSVoon Weifeng ((phydev->attached_dev->dev_addr[1] << 8) |
131408041a9aSVoon Weifeng phydev->attached_dev->dev_addr[0]));
131508041a9aSVoon Weifeng if (ret < 0)
131608041a9aSVoon Weifeng return ret;
131708041a9aSVoon Weifeng
131808041a9aSVoon Weifeng /* Clear WOL status and enable magic packet matching */
131908041a9aSVoon Weifeng ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
132008041a9aSVoon Weifeng MV_V2_WOL_CTRL,
132108041a9aSVoon Weifeng MV_V2_WOL_CTRL_MAGIC_PKT_EN |
132208041a9aSVoon Weifeng MV_V2_WOL_CTRL_CLEAR_STS);
132308041a9aSVoon Weifeng if (ret < 0)
132408041a9aSVoon Weifeng return ret;
132508041a9aSVoon Weifeng } else {
132608041a9aSVoon Weifeng /* Disable magic packet matching & reset WOL status bit */
132708041a9aSVoon Weifeng ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
132808041a9aSVoon Weifeng MV_V2_WOL_CTRL,
132908041a9aSVoon Weifeng MV_V2_WOL_CTRL_MAGIC_PKT_EN,
133008041a9aSVoon Weifeng MV_V2_WOL_CTRL_CLEAR_STS);
133108041a9aSVoon Weifeng if (ret < 0)
133208041a9aSVoon Weifeng return ret;
133308041a9aSVoon Weifeng }
133408041a9aSVoon Weifeng
133508041a9aSVoon Weifeng /* Reset the clear WOL status bit as it does not self-clear */
133608041a9aSVoon Weifeng return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
133708041a9aSVoon Weifeng MV_V2_WOL_CTRL,
133808041a9aSVoon Weifeng MV_V2_WOL_CTRL_CLEAR_STS);
133908041a9aSVoon Weifeng }
134008041a9aSVoon Weifeng
134120b2af32SRussell King static struct phy_driver mv3310_drivers[] = {
134220b2af32SRussell King {
1343631ba906SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88X3310,
1344a5de4be0SMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK,
1345a5de4be0SMarek Behún .match_phy_device = mv3310_match_phy_device,
134620b2af32SRussell King .name = "mv88x3310",
134797bbe3bdSMarek Behún .driver_data = &mv3310_type,
134874145424SMaxime Chevallier .get_features = mv3310_get_features,
134920b2af32SRussell King .config_init = mv3310_config_init,
13500d3ad854SRussell King .probe = mv3310_probe,
13510d3ad854SRussell King .suspend = mv3310_suspend,
13520d3ad854SRussell King .resume = mv3310_resume,
135320b2af32SRussell King .config_aneg = mv3310_config_aneg,
135420b2af32SRussell King .aneg_done = mv3310_aneg_done,
135520b2af32SRussell King .read_status = mv3310_read_status,
1356a585c03eSRussell King .get_tunable = mv3310_get_tunable,
1357a585c03eSRussell King .set_tunable = mv3310_set_tunable,
13581b8ef142SMarek Behún .remove = mv3310_remove,
1359d137c70dSWong Vee Khee .set_loopback = genphy_c45_loopback,
136008041a9aSVoon Weifeng .get_wol = mv3110_get_wol,
136108041a9aSVoon Weifeng .set_wol = mv3110_set_wol,
136220b2af32SRussell King },
136362d01535SMaxime Chevallier {
1364a5de4be0SMarek Behún .phy_id = MARVELL_PHY_ID_88X3310,
1365a5de4be0SMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK,
1366a5de4be0SMarek Behún .match_phy_device = mv3340_match_phy_device,
13679885d016SMarek Behún .name = "mv88x3340",
13689885d016SMarek Behún .driver_data = &mv3340_type,
13699885d016SMarek Behún .get_features = mv3310_get_features,
13709885d016SMarek Behún .config_init = mv3310_config_init,
13719885d016SMarek Behún .probe = mv3310_probe,
13729885d016SMarek Behún .suspend = mv3310_suspend,
13739885d016SMarek Behún .resume = mv3310_resume,
13749885d016SMarek Behún .config_aneg = mv3310_config_aneg,
13759885d016SMarek Behún .aneg_done = mv3310_aneg_done,
13769885d016SMarek Behún .read_status = mv3310_read_status,
13779885d016SMarek Behún .get_tunable = mv3310_get_tunable,
13789885d016SMarek Behún .set_tunable = mv3310_set_tunable,
13799885d016SMarek Behún .remove = mv3310_remove,
13809885d016SMarek Behún .set_loopback = genphy_c45_loopback,
13819885d016SMarek Behún },
13829885d016SMarek Behún {
138362d01535SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88E2110,
138462d01535SMaxime Chevallier .phy_id_mask = MARVELL_PHY_ID_MASK,
13850fca947cSMarek Behún .match_phy_device = mv2110_match_phy_device,
1386c89f27d4SMarek Behún .name = "mv88e2110",
138797bbe3bdSMarek Behún .driver_data = &mv2110_type,
138862d01535SMaxime Chevallier .probe = mv3310_probe,
1389e02c4a9dSAntoine Tenart .suspend = mv3310_suspend,
1390e02c4a9dSAntoine Tenart .resume = mv3310_resume,
139162d01535SMaxime Chevallier .config_init = mv3310_config_init,
139262d01535SMaxime Chevallier .config_aneg = mv3310_config_aneg,
139362d01535SMaxime Chevallier .aneg_done = mv3310_aneg_done,
139462d01535SMaxime Chevallier .read_status = mv3310_read_status,
1395a585c03eSRussell King .get_tunable = mv3310_get_tunable,
1396a585c03eSRussell King .set_tunable = mv3310_set_tunable,
13971b8ef142SMarek Behún .remove = mv3310_remove,
1398d137c70dSWong Vee Khee .set_loopback = genphy_c45_loopback,
139908041a9aSVoon Weifeng .get_wol = mv3110_get_wol,
140008041a9aSVoon Weifeng .set_wol = mv3110_set_wol,
140162d01535SMaxime Chevallier },
14020fca947cSMarek Behún {
14030fca947cSMarek Behún .phy_id = MARVELL_PHY_ID_88E2110,
14040fca947cSMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK,
14050fca947cSMarek Behún .match_phy_device = mv2111_match_phy_device,
14060fca947cSMarek Behún .name = "mv88e2111",
14070fca947cSMarek Behún .driver_data = &mv2111_type,
14080fca947cSMarek Behún .probe = mv3310_probe,
14090fca947cSMarek Behún .suspend = mv3310_suspend,
14100fca947cSMarek Behún .resume = mv3310_resume,
14110fca947cSMarek Behún .config_init = mv3310_config_init,
14120fca947cSMarek Behún .config_aneg = mv3310_config_aneg,
14130fca947cSMarek Behún .aneg_done = mv3310_aneg_done,
14140fca947cSMarek Behún .read_status = mv3310_read_status,
14150fca947cSMarek Behún .get_tunable = mv3310_get_tunable,
14160fca947cSMarek Behún .set_tunable = mv3310_set_tunable,
14170fca947cSMarek Behún .remove = mv3310_remove,
14180fca947cSMarek Behún .set_loopback = genphy_c45_loopback,
14190fca947cSMarek Behún },
142020b2af32SRussell King };
142120b2af32SRussell King
142220b2af32SRussell King module_phy_driver(mv3310_drivers);
142320b2af32SRussell King
142420b2af32SRussell King static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1425a5de4be0SMarek Behún { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
142662d01535SMaxime Chevallier { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
142720b2af32SRussell King { },
142820b2af32SRussell King };
142920b2af32SRussell King MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1430c7dce05eSMarek Behún MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
143120b2af32SRussell King MODULE_LICENSE("GPL");
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