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Searched refs:phydev (Results 1 – 25 of 151) sorted by relevance

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/openbmc/u-boot/drivers/net/phy/
H A Dmarvell.c105 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, in m88e1xxx_phy_extread() argument
108 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
111 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
112 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
118 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, in m88e1xxx_phy_extwrite() argument
121 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
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H A Dbroadcom.c36 static void bcm_phy_write_misc(struct phy_device *phydev, in bcm_phy_write_misc() argument
41 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
44 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
46 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
49 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
55 static int bcm5461_config(struct phy_device *phydev) in bcm5461_config() argument
59 phy_reset(phydev); in bcm5461_config()
64 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5461_config()
66 reg18 = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm5461_config()
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H A Datheros.c20 static int ar8021_config(struct phy_device *phydev) in ar8021_config() argument
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
24 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
26 phydev->supported = phydev->drv->features; in ar8021_config()
30 static int ar8031_config(struct phy_device *phydev) in ar8031_config() argument
32 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in ar8031_config()
33 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { in ar8031_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
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H A Drealtek.c61 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr, in rtl8211f_phy_extread() argument
64 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extread()
68 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extread()
69 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in rtl8211f_phy_extread()
70 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extread()
75 static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr, in rtl8211f_phy_extwrite() argument
78 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extwrite()
81 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extwrite()
82 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in rtl8211f_phy_extwrite()
83 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extwrite()
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H A Dphy.c35 static int genphy_config_advert(struct phy_device *phydev) in genphy_config_advert() argument
42 phydev->advertising &= phydev->supported; in genphy_config_advert()
43 advertise = phydev->advertising; in genphy_config_advert()
46 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
72 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
79 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
91 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
99 if (phydev->supported & (SUPPORTED_1000baseT_Half | in genphy_config_advert()
110 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
124 static int genphy_setup_forced(struct phy_device *phydev) in genphy_setup_forced() argument
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H A Dmicrel_ksz90x1.c40 static int ksz90xx_startup(struct phy_device *phydev) in ksz90xx_startup() argument
45 ret = genphy_update_link(phydev); in ksz90xx_startup()
49 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
52 phydev->duplex = DUPLEX_FULL; in ksz90xx_startup()
54 phydev->duplex = DUPLEX_HALF; in ksz90xx_startup()
57 phydev->speed = SPEED_1000; in ksz90xx_startup()
59 phydev->speed = SPEED_100; in ksz90xx_startup()
61 phydev->speed = SPEED_10; in ksz90xx_startup()
104 static int ksz90x1_of_config_group(struct phy_device *phydev, in ksz90x1_of_config_group() argument
107 struct udevice *dev = phydev->dev; in ksz90x1_of_config_group()
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H A Dti.c134 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, in phy_read_mmd_indirect() argument
140 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
143 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
146 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
149 value = phy_read(phydev, addr, MII_MMD_DATA); in phy_read_mmd_indirect()
169 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, in phy_write_mmd_indirect() argument
173 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
176 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
179 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
182 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
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H A Dvitesse.c71 static int vitesse_config(struct phy_device *phydev) in vitesse_config() argument
74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
80 genphy_config_aneg(phydev); in vitesse_config()
85 static int vitesse_parse_status(struct phy_device *phydev) in vitesse_parse_status() argument
90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
93 phydev->duplex = DUPLEX_FULL; in vitesse_parse_status()
95 phydev->duplex = DUPLEX_HALF; in vitesse_parse_status()
100 phydev->speed = SPEED_1000; in vitesse_parse_status()
103 phydev->speed = SPEED_100; in vitesse_parse_status()
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H A Dmeson-gxl.c31 int meson_gxl_startup(struct phy_device *phydev) in meson_gxl_startup() argument
37 ret = genphy_update_link(phydev); in meson_gxl_startup()
41 if (phydev->autoneg == AUTONEG_ENABLE) { in meson_gxl_startup()
43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
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H A Dmv88e61xx.c216 __weak int mv88e61xx_hw_reset(struct phy_device *phydev) in mv88e61xx_hw_reset() argument
255 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) in mv88e61xx_reg_read() argument
257 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_read()
291 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, in mv88e61xx_reg_write() argument
294 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_write()
330 static int mv88e61xx_phy_wait(struct phy_device *phydev) in mv88e61xx_phy_wait() argument
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
350 struct phy_device *phydev; in mv88e61xx_phy_read_indirect() local
353 phydev = (struct phy_device *)smi_wrapper->priv; in mv88e61xx_phy_read_indirect()
356 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_read_indirect()
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H A Dnatsemi.c18 static int dp83630_config(struct phy_device *phydev) in dp83630_config() argument
22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
31 genphy_config_aneg(phydev); in dp83630_config()
56 static int dp838xx_config(struct phy_device *phydev) in dp838xx_config() argument
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
59 genphy_config_aneg(phydev); in dp838xx_config()
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H A Dxilinx_phy.c33 static int xilinxphy_startup(struct phy_device *phydev) in xilinxphy_startup() argument
42 err = genphy_update_link(phydev); in xilinxphy_startup()
46 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup()
47 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
51 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
53 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup()
57 phydev->speed = SPEED_1000; in xilinxphy_startup()
61 phydev->speed = SPEED_100; in xilinxphy_startup()
65 phydev->speed = SPEED_10; in xilinxphy_startup()
69 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
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H A Daquantia.c132 static int aquantia_load_memory(struct phy_device *phydev, u32 addr, in aquantia_load_memory() argument
138 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC); in aquantia_load_memory()
139 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16); in aquantia_load_memory()
140 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc); in aquantia_load_memory()
147 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW, in aquantia_load_memory()
149 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW, in aquantia_load_memory()
152 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, in aquantia_load_memory()
160 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC); in aquantia_load_memory()
163 phydev->dev->name, crc, up_crc); in aquantia_load_memory()
174 static int aquantia_upload_firmware(struct phy_device *phydev) in aquantia_upload_firmware() argument
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H A Dgeneric_10g.c14 int gen10g_shutdown(struct phy_device *phydev) in gen10g_shutdown() argument
19 int gen10g_startup(struct phy_device *phydev) in gen10g_startup() argument
22 u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; in gen10g_startup()
24 phydev->link = 1; in gen10g_startup()
27 phydev->speed = SPEED_10000; in gen10g_startup()
28 phydev->duplex = DUPLEX_FULL; in gen10g_startup()
40 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
41 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
43 phydev->link = 0; in gen10g_startup()
49 int gen10g_discover_mmds(struct phy_device *phydev) in gen10g_discover_mmds() argument
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H A Dmicrel_ksz8xxx.c29 static int ksz_genconfig_bcastoff(struct phy_device *phydev) in ksz_genconfig_bcastoff() argument
33 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
37 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
42 return genphy_config(phydev); in ksz_genconfig_bcastoff()
61 static int ksz8051_config(struct phy_device *phydev) in ksz8051_config() argument
66 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
68 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
70 return genphy_config(phydev); in ksz8051_config()
107 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) in ksz8895_write_smireg() argument
109 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
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H A Det1011c.c27 static int et1011c_config(struct phy_device *phydev) in et1011c_config() argument
30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
38 return genphy_config_aneg(phydev); in et1011c_config()
41 static int et1011c_parse_status(struct phy_device *phydev) in et1011c_parse_status() argument
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
49 phydev->duplex = DUPLEX_FULL; in et1011c_parse_status()
51 phydev->duplex = DUPLEX_HALF; in et1011c_parse_status()
56 phydev->speed = SPEED_1000; in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
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H A Dteranetics.c15 int tn2020_config(struct phy_device *phydev) in tn2020_config() argument
17 if (phydev->port == PORT_FIBRE) { in tn2020_config()
29 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; in tn2020_config()
31 phy_write(phydev, 30, 93, 2); in tn2020_config()
32 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); in tn2020_config()
34 phy_write(phydev, 30, 93, 1); in tn2020_config()
41 int tn2020_startup(struct phy_device *phydev) in tn2020_startup() argument
56 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); in tn2020_startup()
59 "address %u\n", phydev->addr); in tn2020_startup()
72 "align.\n", phydev->addr); in tn2020_startup()
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H A Ddavicom.c27 static int dm9161_config(struct phy_device *phydev) in dm9161_config() argument
29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
37 genphy_config_aneg(phydev); in dm9161_config()
42 static int dm9161_parse_status(struct phy_device *phydev) in dm9161_parse_status() argument
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
49 phydev->speed = SPEED_100; in dm9161_parse_status()
51 phydev->speed = SPEED_10; in dm9161_parse_status()
54 phydev->duplex = DUPLEX_FULL; in dm9161_parse_status()
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H A Dlxt.c21 static int lxt971_parse_status(struct phy_device *phydev) in lxt971_parse_status() argument
26 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); in lxt971_parse_status()
31 phydev->speed = SPEED_10; in lxt971_parse_status()
32 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
35 phydev->speed = SPEED_10; in lxt971_parse_status()
36 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
39 phydev->speed = SPEED_100; in lxt971_parse_status()
40 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
43 phydev->speed = SPEED_100; in lxt971_parse_status()
44 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
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H A Dmscc.c271 int (*config_pre)(struct phy_device *phydev);
653 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
655 struct mii_dev *bus = phydev->bus; in vsc8574_config_pre_init()
660 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
662 addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8574_config_pre_init()
665 reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL); in vsc8574_config_pre_init()
667 phy0 = phydev->addr + addr; in vsc8574_config_pre_init()
669 phy0 = phydev->addr - addr; in vsc8574_config_pre_init()
852 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
854 struct mii_dev *bus = phydev->bus; in vsc8584_config_pre_init()
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H A Dcortina.c125 void cs4340_upload_firmware(struct phy_device *phydev) in cs4340_upload_firmware() argument
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
221 int cs4340_phy_init(struct phy_device *phydev) in cs4340_phy_init() argument
236 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); in cs4340_phy_init()
237 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); in cs4340_phy_init()
238 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); in cs4340_phy_init()
240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
254 cs4340_upload_firmware(phydev); in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
265 int cs4340_config(struct phy_device *phydev) in cs4340_config() argument
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H A Dfixed.c16 int fixedphy_probe(struct phy_device *phydev) in fixedphy_probe() argument
19 int ofnode = phydev->addr; in fixedphy_probe()
35 phydev->priv = priv; in fixedphy_probe()
43 phydev->flags |= PHY_FLAG_BROKEN_RESET; in fixedphy_probe()
48 int fixedphy_startup(struct phy_device *phydev) in fixedphy_startup() argument
50 struct fixed_link *priv = phydev->priv; in fixedphy_startup()
52 phydev->asym_pause = priv->asym_pause; in fixedphy_startup()
53 phydev->pause = priv->pause; in fixedphy_startup()
54 phydev->duplex = priv->duplex; in fixedphy_startup()
55 phydev->speed = priv->link_speed; in fixedphy_startup()
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/openbmc/u-boot/include/
H A Dphy.h90 int (*probe)(struct phy_device *phydev);
94 int (*config)(struct phy_device *phydev);
97 int (*startup)(struct phy_device *phydev);
100 int (*shutdown)(struct phy_device *phydev);
102 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
103 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
154 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) in phy_read() argument
156 struct mii_dev *bus = phydev->bus; in phy_read()
163 return bus->read(bus, phydev->addr, devad, regnum); in phy_read()
166 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, in phy_write() argument
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/openbmc/u-boot/board/spear/x600/
H A Dx600.c71 int board_phy_config(struct phy_device *phydev) in board_phy_config() argument
76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
86 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
91 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
96 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
101 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
113 phy_reset(phydev); in board_phy_config()
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/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dcl-som-imx7.c128 static void cl_som_imx7_rgmii_rework(struct phy_device *phydev) in cl_som_imx7_rgmii_rework() argument
135 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in cl_som_imx7_rgmii_rework()
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in cl_som_imx7_rgmii_rework()
147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
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