1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+
2ef82a306SJon Loeliger /*
3ef82a306SJon Loeliger * Driver for Vitesse PHYs
4ef82a306SJon Loeliger *
5ef82a306SJon Loeliger * Author: Kriston Carson
6ef82a306SJon Loeliger */
7ef82a306SJon Loeliger
8ef82a306SJon Loeliger #include <linux/kernel.h>
9ef82a306SJon Loeliger #include <linux/module.h>
10ef82a306SJon Loeliger #include <linux/mii.h>
11ef82a306SJon Loeliger #include <linux/ethtool.h>
12ef82a306SJon Loeliger #include <linux/phy.h>
13ef82a306SJon Loeliger
143fb69bcaSMadalin Bucur /* Vitesse Extended Page Magic Register(s) */
153fb69bcaSMadalin Bucur #define MII_VSC82X4_EXT_PAGE_16E 0x10
163fb69bcaSMadalin Bucur #define MII_VSC82X4_EXT_PAGE_17E 0x11
173fb69bcaSMadalin Bucur #define MII_VSC82X4_EXT_PAGE_18E 0x12
183fb69bcaSMadalin Bucur
19ef82a306SJon Loeliger /* Vitesse Extended Control Register 1 */
20ef82a306SJon Loeliger #define MII_VSC8244_EXT_CON1 0x17
21ef82a306SJon Loeliger #define MII_VSC8244_EXTCON1_INIT 0x0000
22af2d940dSAndy Fleming #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
23af2d940dSAndy Fleming #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
24af2d940dSAndy Fleming #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
25af2d940dSAndy Fleming #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
26ef82a306SJon Loeliger
27ef82a306SJon Loeliger /* Vitesse Interrupt Mask Register */
28ef82a306SJon Loeliger #define MII_VSC8244_IMASK 0x19
29ef82a306SJon Loeliger #define MII_VSC8244_IMASK_IEN 0x8000
30ef82a306SJon Loeliger #define MII_VSC8244_IMASK_SPEED 0x4000
31ef82a306SJon Loeliger #define MII_VSC8244_IMASK_LINK 0x2000
32ef82a306SJon Loeliger #define MII_VSC8244_IMASK_DUPLEX 0x1000
33ef82a306SJon Loeliger #define MII_VSC8244_IMASK_MASK 0xf000
34ef82a306SJon Loeliger
3511c6dd2cSTrent Piepho #define MII_VSC8221_IMASK_MASK 0xa000
3611c6dd2cSTrent Piepho
37ef82a306SJon Loeliger /* Vitesse Interrupt Status Register */
38ef82a306SJon Loeliger #define MII_VSC8244_ISTAT 0x1a
39ef82a306SJon Loeliger #define MII_VSC8244_ISTAT_STATUS 0x8000
40ef82a306SJon Loeliger #define MII_VSC8244_ISTAT_SPEED 0x4000
41ef82a306SJon Loeliger #define MII_VSC8244_ISTAT_LINK 0x2000
42ef82a306SJon Loeliger #define MII_VSC8244_ISTAT_DUPLEX 0x1000
43b606ad8fSIoana Ciornei #define MII_VSC8244_ISTAT_MASK (MII_VSC8244_ISTAT_SPEED | \
44b606ad8fSIoana Ciornei MII_VSC8244_ISTAT_LINK | \
45b606ad8fSIoana Ciornei MII_VSC8244_ISTAT_DUPLEX)
46b606ad8fSIoana Ciornei
47b606ad8fSIoana Ciornei #define MII_VSC8221_ISTAT_MASK MII_VSC8244_ISTAT_LINK
48ef82a306SJon Loeliger
49ef82a306SJon Loeliger /* Vitesse Auxiliary Control/Status Register */
50ef82a306SJon Loeliger #define MII_VSC8244_AUX_CONSTAT 0x1c
51af2d940dSAndy Fleming #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
52ef82a306SJon Loeliger #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
53ef82a306SJon Loeliger #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
54ef82a306SJon Loeliger #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
55ef82a306SJon Loeliger #define MII_VSC8244_AUXCONSTAT_100 0x0008
56ef82a306SJon Loeliger
5711c6dd2cSTrent Piepho #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
5811c6dd2cSTrent Piepho #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
5911c6dd2cSTrent Piepho
603fb69bcaSMadalin Bucur /* Vitesse Extended Page Access Register */
613fb69bcaSMadalin Bucur #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
623fb69bcaSMadalin Bucur
63955e1602SAlex /* Vitesse VSC8601 Extended PHY Control Register 1 */
64955e1602SAlex #define MII_VSC8601_EPHY_CTL 0x17
65955e1602SAlex #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
66955e1602SAlex
670508019cSAndy Fleming #define PHY_ID_VSC8234 0x000fc620
6811c6dd2cSTrent Piepho #define PHY_ID_VSC8244 0x000fc6c0
69dc855b3bSStephen Agate #define PHY_ID_VSC8572 0x000704d0
707729b053SMåns Rullgård #define PHY_ID_VSC8601 0x00070420
71975ae7c6SLinus Walleij #define PHY_ID_VSC7385 0x00070450
72975ae7c6SLinus Walleij #define PHY_ID_VSC7388 0x00070480
73975ae7c6SLinus Walleij #define PHY_ID_VSC7395 0x00070550
74975ae7c6SLinus Walleij #define PHY_ID_VSC7398 0x00070580
7506ae4f84SSandeep Singh #define PHY_ID_VSC8662 0x00070660
7611c6dd2cSTrent Piepho #define PHY_ID_VSC8221 0x000fc550
775a1cebd8SMichal Simek #define PHY_ID_VSC8211 0x000fc4b0
7811c6dd2cSTrent Piepho
79ef82a306SJon Loeliger MODULE_DESCRIPTION("Vitesse PHY driver");
80ef82a306SJon Loeliger MODULE_AUTHOR("Kriston Carson");
81ef82a306SJon Loeliger MODULE_LICENSE("GPL");
82ef82a306SJon Loeliger
vsc824x_add_skew(struct phy_device * phydev)83baec126cSstephen hemminger static int vsc824x_add_skew(struct phy_device *phydev)
84fddf86fcSAndy Fleming {
85fddf86fcSAndy Fleming int err;
86fddf86fcSAndy Fleming int extcon;
87fddf86fcSAndy Fleming
88fddf86fcSAndy Fleming extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
89fddf86fcSAndy Fleming
90fddf86fcSAndy Fleming if (extcon < 0)
91fddf86fcSAndy Fleming return extcon;
92fddf86fcSAndy Fleming
93fddf86fcSAndy Fleming extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
94fddf86fcSAndy Fleming MII_VSC8244_EXTCON1_RX_SKEW_MASK);
95fddf86fcSAndy Fleming
96fddf86fcSAndy Fleming extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
97fddf86fcSAndy Fleming MII_VSC8244_EXTCON1_RX_SKEW);
98fddf86fcSAndy Fleming
99fddf86fcSAndy Fleming err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
100fddf86fcSAndy Fleming
101fddf86fcSAndy Fleming return err;
102fddf86fcSAndy Fleming }
103fddf86fcSAndy Fleming
vsc824x_config_init(struct phy_device * phydev)104ef82a306SJon Loeliger static int vsc824x_config_init(struct phy_device *phydev)
105ef82a306SJon Loeliger {
106ef82a306SJon Loeliger int err;
107ef82a306SJon Loeliger
108ef82a306SJon Loeliger err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
109ef82a306SJon Loeliger MII_VSC8244_AUXCONSTAT_INIT);
110ef82a306SJon Loeliger if (err < 0)
111ef82a306SJon Loeliger return err;
112ef82a306SJon Loeliger
113af2d940dSAndy Fleming if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
114fddf86fcSAndy Fleming err = vsc824x_add_skew(phydev);
115af2d940dSAndy Fleming
116ef82a306SJon Loeliger return err;
117ef82a306SJon Loeliger }
118ef82a306SJon Loeliger
119975ae7c6SLinus Walleij #define VSC73XX_EXT_PAGE_ACCESS 0x1f
120975ae7c6SLinus Walleij
vsc73xx_read_page(struct phy_device * phydev)121975ae7c6SLinus Walleij static int vsc73xx_read_page(struct phy_device *phydev)
122975ae7c6SLinus Walleij {
123975ae7c6SLinus Walleij return __phy_read(phydev, VSC73XX_EXT_PAGE_ACCESS);
124975ae7c6SLinus Walleij }
125975ae7c6SLinus Walleij
vsc73xx_write_page(struct phy_device * phydev,int page)126975ae7c6SLinus Walleij static int vsc73xx_write_page(struct phy_device *phydev, int page)
127975ae7c6SLinus Walleij {
128975ae7c6SLinus Walleij return __phy_write(phydev, VSC73XX_EXT_PAGE_ACCESS, page);
129975ae7c6SLinus Walleij }
130975ae7c6SLinus Walleij
vsc73xx_config_init(struct phy_device * phydev)131975ae7c6SLinus Walleij static void vsc73xx_config_init(struct phy_device *phydev)
132975ae7c6SLinus Walleij {
133975ae7c6SLinus Walleij /* Receiver init */
134975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
135975ae7c6SLinus Walleij phy_modify(phydev, 0x0c, 0x0300, 0x0200);
136975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
137975ae7c6SLinus Walleij
138975ae7c6SLinus Walleij /* Config LEDs 0x61 */
139975ae7c6SLinus Walleij phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061);
140975ae7c6SLinus Walleij }
141975ae7c6SLinus Walleij
vsc738x_config_init(struct phy_device * phydev)142975ae7c6SLinus Walleij static int vsc738x_config_init(struct phy_device *phydev)
143975ae7c6SLinus Walleij {
144975ae7c6SLinus Walleij u16 rev;
145975ae7c6SLinus Walleij /* This magic sequence appear in the application note
146975ae7c6SLinus Walleij * "VSC7385/7388 PHY Configuration".
147975ae7c6SLinus Walleij *
148975ae7c6SLinus Walleij * Maybe one day we will get to know what it all means.
149975ae7c6SLinus Walleij */
150975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
151975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0200);
152975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x52b5);
153975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0xb68a);
154975ae7c6SLinus Walleij phy_modify(phydev, 0x12, 0xff07, 0x0003);
155975ae7c6SLinus Walleij phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
156975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0x968a);
157975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
158975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0000);
159975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
160975ae7c6SLinus Walleij
161975ae7c6SLinus Walleij /* Read revision */
162975ae7c6SLinus Walleij rev = phy_read(phydev, MII_PHYSID2);
163975ae7c6SLinus Walleij rev &= 0x0f;
164975ae7c6SLinus Walleij
165975ae7c6SLinus Walleij /* Special quirk for revision 0 */
166975ae7c6SLinus Walleij if (rev == 0) {
167975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
168975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0200);
169975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x52b5);
170975ae7c6SLinus Walleij phy_write(phydev, 0x12, 0x0000);
171975ae7c6SLinus Walleij phy_write(phydev, 0x11, 0x0689);
172975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0x8f92);
173975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x52b5);
174975ae7c6SLinus Walleij phy_write(phydev, 0x12, 0x0000);
175975ae7c6SLinus Walleij phy_write(phydev, 0x11, 0x0e35);
176975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0x9786);
177975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
178975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0000);
179975ae7c6SLinus Walleij phy_write(phydev, 0x17, 0xff80);
180975ae7c6SLinus Walleij phy_write(phydev, 0x17, 0x0000);
181975ae7c6SLinus Walleij }
182975ae7c6SLinus Walleij
183975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
184975ae7c6SLinus Walleij phy_write(phydev, 0x12, 0x0048);
185975ae7c6SLinus Walleij
186975ae7c6SLinus Walleij if (rev == 0) {
187975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
188975ae7c6SLinus Walleij phy_write(phydev, 0x14, 0x6600);
189975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
190975ae7c6SLinus Walleij phy_write(phydev, 0x18, 0xa24e);
191975ae7c6SLinus Walleij } else {
192975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
193975ae7c6SLinus Walleij phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
194975ae7c6SLinus Walleij phy_modify(phydev, 0x14, 0x6000, 0x4000);
195975ae7c6SLinus Walleij /* bits 14-15 in extended register 0x14 controls DACG amplitude
196975ae7c6SLinus Walleij * 6 = -8%, 2 is hardware default
197975ae7c6SLinus Walleij */
198975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0001);
199975ae7c6SLinus Walleij phy_modify(phydev, 0x14, 0xe000, 0x6000);
200975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
201975ae7c6SLinus Walleij }
202975ae7c6SLinus Walleij
203975ae7c6SLinus Walleij vsc73xx_config_init(phydev);
204975ae7c6SLinus Walleij
205c227ce44SHeiner Kallweit return 0;
206975ae7c6SLinus Walleij }
207975ae7c6SLinus Walleij
vsc739x_config_init(struct phy_device * phydev)208975ae7c6SLinus Walleij static int vsc739x_config_init(struct phy_device *phydev)
209975ae7c6SLinus Walleij {
210975ae7c6SLinus Walleij /* This magic sequence appears in the VSC7395 SparX-G5e application
211975ae7c6SLinus Walleij * note "VSC7395/VSC7398 PHY Configuration"
212975ae7c6SLinus Walleij *
213975ae7c6SLinus Walleij * Maybe one day we will get to know what it all means.
214975ae7c6SLinus Walleij */
215975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
216975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0200);
217975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x52b5);
218975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0xb68a);
219975ae7c6SLinus Walleij phy_modify(phydev, 0x12, 0xff07, 0x0003);
220975ae7c6SLinus Walleij phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
221975ae7c6SLinus Walleij phy_write(phydev, 0x10, 0x968a);
222975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
223975ae7c6SLinus Walleij phy_modify(phydev, 0x08, 0x0200, 0x0000);
224975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
225975ae7c6SLinus Walleij
226975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
227975ae7c6SLinus Walleij phy_write(phydev, 0x12, 0x0048);
228975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x2a30);
229975ae7c6SLinus Walleij phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
230975ae7c6SLinus Walleij phy_modify(phydev, 0x14, 0x6000, 0x4000);
231975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0001);
232975ae7c6SLinus Walleij phy_modify(phydev, 0x14, 0xe000, 0x6000);
233975ae7c6SLinus Walleij phy_write(phydev, 0x1f, 0x0000);
234975ae7c6SLinus Walleij
235975ae7c6SLinus Walleij vsc73xx_config_init(phydev);
236975ae7c6SLinus Walleij
237c227ce44SHeiner Kallweit return 0;
238975ae7c6SLinus Walleij }
239975ae7c6SLinus Walleij
vsc73xx_config_aneg(struct phy_device * phydev)240975ae7c6SLinus Walleij static int vsc73xx_config_aneg(struct phy_device *phydev)
241975ae7c6SLinus Walleij {
242975ae7c6SLinus Walleij /* The VSC73xx switches does not like to be instructed to
243975ae7c6SLinus Walleij * do autonegotiation in any way, it prefers that you just go
244975ae7c6SLinus Walleij * with the power-on/reset defaults. Writing some registers will
245975ae7c6SLinus Walleij * just make autonegotiation permanently fail.
246975ae7c6SLinus Walleij */
247975ae7c6SLinus Walleij return 0;
248975ae7c6SLinus Walleij }
249975ae7c6SLinus Walleij
250955e1602SAlex /* This adds a skew for both TX and RX clocks, so the skew should only be
251955e1602SAlex * applied to "rgmii-id" interfaces. It may not work as expected
252*1953feb0SWenpeng Liang * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces.
253*1953feb0SWenpeng Liang */
vsc8601_add_skew(struct phy_device * phydev)254955e1602SAlex static int vsc8601_add_skew(struct phy_device *phydev)
255955e1602SAlex {
256955e1602SAlex int ret;
257955e1602SAlex
258955e1602SAlex ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
259955e1602SAlex if (ret < 0)
260955e1602SAlex return ret;
261955e1602SAlex
262955e1602SAlex ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
263955e1602SAlex return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
264955e1602SAlex }
265955e1602SAlex
vsc8601_config_init(struct phy_device * phydev)266955e1602SAlex static int vsc8601_config_init(struct phy_device *phydev)
267955e1602SAlex {
268955e1602SAlex int ret = 0;
269955e1602SAlex
270955e1602SAlex if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
271955e1602SAlex ret = vsc8601_add_skew(phydev);
272955e1602SAlex
273955e1602SAlex if (ret < 0)
274955e1602SAlex return ret;
275955e1602SAlex
276c227ce44SHeiner Kallweit return 0;
277955e1602SAlex }
278955e1602SAlex
vsc82xx_config_intr(struct phy_device * phydev)27911c6dd2cSTrent Piepho static int vsc82xx_config_intr(struct phy_device *phydev)
280ef82a306SJon Loeliger {
281ef82a306SJon Loeliger int err;
282ef82a306SJon Loeliger
283ef82a306SJon Loeliger if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
284e96a0d97SIoana Ciornei /* Don't bother to ACK the interrupts since the 824x cannot
285e96a0d97SIoana Ciornei * clear the interrupts if they are disabled.
286e96a0d97SIoana Ciornei */
287ef82a306SJon Loeliger err = phy_write(phydev, MII_VSC8244_IMASK,
2880508019cSAndy Fleming (phydev->drv->phy_id == PHY_ID_VSC8234 ||
289c2efef74Sshaohui xie phydev->drv->phy_id == PHY_ID_VSC8244 ||
290dc855b3bSStephen Agate phydev->drv->phy_id == PHY_ID_VSC8572 ||
2917729b053SMåns Rullgård phydev->drv->phy_id == PHY_ID_VSC8601) ?
29211c6dd2cSTrent Piepho MII_VSC8244_IMASK_MASK :
29311c6dd2cSTrent Piepho MII_VSC8221_IMASK_MASK);
2941d5e83aaSAndy Fleming else {
2952a8626d1SMichal Simek /* The Vitesse PHY cannot clear the interrupt
2961d5e83aaSAndy Fleming * once it has disabled them, so we clear them first
2971d5e83aaSAndy Fleming */
2981d5e83aaSAndy Fleming err = phy_read(phydev, MII_VSC8244_ISTAT);
2991d5e83aaSAndy Fleming
30052cb1c2bSAndy Fleming if (err < 0)
3011d5e83aaSAndy Fleming return err;
3021d5e83aaSAndy Fleming
303ef82a306SJon Loeliger err = phy_write(phydev, MII_VSC8244_IMASK, 0);
3041d5e83aaSAndy Fleming }
3051d5e83aaSAndy Fleming
306ef82a306SJon Loeliger return err;
307ef82a306SJon Loeliger }
308ef82a306SJon Loeliger
vsc82xx_handle_interrupt(struct phy_device * phydev)309b606ad8fSIoana Ciornei static irqreturn_t vsc82xx_handle_interrupt(struct phy_device *phydev)
310b606ad8fSIoana Ciornei {
311b606ad8fSIoana Ciornei int irq_status, irq_mask;
312b606ad8fSIoana Ciornei
313b606ad8fSIoana Ciornei if (phydev->drv->phy_id == PHY_ID_VSC8244 ||
314b606ad8fSIoana Ciornei phydev->drv->phy_id == PHY_ID_VSC8572 ||
315b606ad8fSIoana Ciornei phydev->drv->phy_id == PHY_ID_VSC8601)
316b606ad8fSIoana Ciornei irq_mask = MII_VSC8244_ISTAT_MASK;
317b606ad8fSIoana Ciornei else
318b606ad8fSIoana Ciornei irq_mask = MII_VSC8221_ISTAT_MASK;
319b606ad8fSIoana Ciornei
320b606ad8fSIoana Ciornei irq_status = phy_read(phydev, MII_VSC8244_ISTAT);
321b606ad8fSIoana Ciornei if (irq_status < 0) {
322b606ad8fSIoana Ciornei phy_error(phydev);
323b606ad8fSIoana Ciornei return IRQ_NONE;
324b606ad8fSIoana Ciornei }
325b606ad8fSIoana Ciornei
326b606ad8fSIoana Ciornei if (!(irq_status & irq_mask))
327b606ad8fSIoana Ciornei return IRQ_NONE;
328b606ad8fSIoana Ciornei
329b606ad8fSIoana Ciornei phy_trigger_machine(phydev);
330b606ad8fSIoana Ciornei
331b606ad8fSIoana Ciornei return IRQ_HANDLED;
332b606ad8fSIoana Ciornei }
333b606ad8fSIoana Ciornei
vsc8221_config_init(struct phy_device * phydev)33411c6dd2cSTrent Piepho static int vsc8221_config_init(struct phy_device *phydev)
335ef82a306SJon Loeliger {
33611c6dd2cSTrent Piepho int err;
33711c6dd2cSTrent Piepho
33811c6dd2cSTrent Piepho err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
33911c6dd2cSTrent Piepho MII_VSC8221_AUXCONSTAT_INIT);
34011c6dd2cSTrent Piepho return err;
34111c6dd2cSTrent Piepho
34211c6dd2cSTrent Piepho /* Perhaps we should set EXT_CON1 based on the interface?
3432a8626d1SMichal Simek * Options are 802.3Z SerDes or SGMII
3442a8626d1SMichal Simek */
345ef82a306SJon Loeliger }
346ef82a306SJon Loeliger
3473fb69bcaSMadalin Bucur /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
3483fb69bcaSMadalin Bucur * @phydev: target phy_device struct
3493fb69bcaSMadalin Bucur *
3503fb69bcaSMadalin Bucur * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
3513fb69bcaSMadalin Bucur * special values in the VSC8234/VSC8244 extended reserved registers
3523fb69bcaSMadalin Bucur */
vsc82x4_config_autocross_enable(struct phy_device * phydev)3533fb69bcaSMadalin Bucur static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
3543fb69bcaSMadalin Bucur {
3553fb69bcaSMadalin Bucur int ret;
3563fb69bcaSMadalin Bucur
3573fb69bcaSMadalin Bucur if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
3583fb69bcaSMadalin Bucur return 0;
3593fb69bcaSMadalin Bucur
3603fb69bcaSMadalin Bucur /* map extended registers set 0x10 - 0x1e */
3613fb69bcaSMadalin Bucur ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
3623fb69bcaSMadalin Bucur if (ret >= 0)
3633fb69bcaSMadalin Bucur ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
3643fb69bcaSMadalin Bucur if (ret >= 0)
3653fb69bcaSMadalin Bucur ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
3663fb69bcaSMadalin Bucur if (ret >= 0)
3673fb69bcaSMadalin Bucur ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
3683fb69bcaSMadalin Bucur /* map standard registers set 0x10 - 0x1e */
3693fb69bcaSMadalin Bucur if (ret >= 0)
3703fb69bcaSMadalin Bucur ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
3713fb69bcaSMadalin Bucur else
3723fb69bcaSMadalin Bucur phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
3733fb69bcaSMadalin Bucur
3743fb69bcaSMadalin Bucur return ret;
3753fb69bcaSMadalin Bucur }
3763fb69bcaSMadalin Bucur
3773fb69bcaSMadalin Bucur /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
3783fb69bcaSMadalin Bucur * @phydev: target phy_device struct
3793fb69bcaSMadalin Bucur *
3803fb69bcaSMadalin Bucur * Description: If auto-negotiation is enabled, we configure the
3813fb69bcaSMadalin Bucur * advertising, and then restart auto-negotiation. If it is not
3823fb69bcaSMadalin Bucur * enabled, then we write the BMCR and also start the auto
3833fb69bcaSMadalin Bucur * MDI/MDI-X feature
3843fb69bcaSMadalin Bucur */
vsc82x4_config_aneg(struct phy_device * phydev)3853fb69bcaSMadalin Bucur static int vsc82x4_config_aneg(struct phy_device *phydev)
3863fb69bcaSMadalin Bucur {
3873fb69bcaSMadalin Bucur int ret;
3883fb69bcaSMadalin Bucur
3893fb69bcaSMadalin Bucur /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
3903fb69bcaSMadalin Bucur * writing special values in the VSC8234 extended reserved registers
3913fb69bcaSMadalin Bucur */
3923fb69bcaSMadalin Bucur if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
3933fb69bcaSMadalin Bucur ret = genphy_setup_forced(phydev);
3943fb69bcaSMadalin Bucur
3953fb69bcaSMadalin Bucur if (ret < 0) /* error */
3963fb69bcaSMadalin Bucur return ret;
3973fb69bcaSMadalin Bucur
3983fb69bcaSMadalin Bucur return vsc82x4_config_autocross_enable(phydev);
3993fb69bcaSMadalin Bucur }
4003fb69bcaSMadalin Bucur
4013fb69bcaSMadalin Bucur return genphy_config_aneg(phydev);
4023fb69bcaSMadalin Bucur }
4033fb69bcaSMadalin Bucur
4040508019cSAndy Fleming /* Vitesse 82xx */
405d5bf9071SChristian Hohnstaedt static struct phy_driver vsc82xx_driver[] = {
406d5bf9071SChristian Hohnstaedt {
4070508019cSAndy Fleming .phy_id = PHY_ID_VSC8234,
4080508019cSAndy Fleming .name = "Vitesse VSC8234",
4090508019cSAndy Fleming .phy_id_mask = 0x000ffff0,
410dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
4110508019cSAndy Fleming .config_init = &vsc824x_config_init,
4123fb69bcaSMadalin Bucur .config_aneg = &vsc82x4_config_aneg,
4130508019cSAndy Fleming .config_intr = &vsc82xx_config_intr,
414b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
4150508019cSAndy Fleming }, {
416d5bf9071SChristian Hohnstaedt .phy_id = PHY_ID_VSC8244,
417d5bf9071SChristian Hohnstaedt .name = "Vitesse VSC8244",
418d5bf9071SChristian Hohnstaedt .phy_id_mask = 0x000fffc0,
419dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
420d5bf9071SChristian Hohnstaedt .config_init = &vsc824x_config_init,
4213fb69bcaSMadalin Bucur .config_aneg = &vsc82x4_config_aneg,
422d5bf9071SChristian Hohnstaedt .config_intr = &vsc82xx_config_intr,
423b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
424d5bf9071SChristian Hohnstaedt }, {
425dc855b3bSStephen Agate .phy_id = PHY_ID_VSC8572,
426dc855b3bSStephen Agate .name = "Vitesse VSC8572",
427dc855b3bSStephen Agate .phy_id_mask = 0x000ffff0,
428dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
429dc855b3bSStephen Agate .config_init = &vsc824x_config_init,
430dc855b3bSStephen Agate .config_aneg = &vsc82x4_config_aneg,
431dc855b3bSStephen Agate .config_intr = &vsc82xx_config_intr,
432b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
433dc855b3bSStephen Agate }, {
4347729b053SMåns Rullgård .phy_id = PHY_ID_VSC8601,
4357729b053SMåns Rullgård .name = "Vitesse VSC8601",
4367729b053SMåns Rullgård .phy_id_mask = 0x000ffff0,
437dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
438955e1602SAlex .config_init = &vsc8601_config_init,
4397729b053SMåns Rullgård .config_intr = &vsc82xx_config_intr,
440b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
4417729b053SMåns Rullgård }, {
442975ae7c6SLinus Walleij .phy_id = PHY_ID_VSC7385,
443975ae7c6SLinus Walleij .name = "Vitesse VSC7385",
444975ae7c6SLinus Walleij .phy_id_mask = 0x000ffff0,
445dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
446975ae7c6SLinus Walleij .config_init = vsc738x_config_init,
447975ae7c6SLinus Walleij .config_aneg = vsc73xx_config_aneg,
448975ae7c6SLinus Walleij .read_page = vsc73xx_read_page,
449975ae7c6SLinus Walleij .write_page = vsc73xx_write_page,
450975ae7c6SLinus Walleij }, {
451975ae7c6SLinus Walleij .phy_id = PHY_ID_VSC7388,
452975ae7c6SLinus Walleij .name = "Vitesse VSC7388",
453975ae7c6SLinus Walleij .phy_id_mask = 0x000ffff0,
454dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
455975ae7c6SLinus Walleij .config_init = vsc738x_config_init,
456975ae7c6SLinus Walleij .config_aneg = vsc73xx_config_aneg,
457975ae7c6SLinus Walleij .read_page = vsc73xx_read_page,
458975ae7c6SLinus Walleij .write_page = vsc73xx_write_page,
459975ae7c6SLinus Walleij }, {
460975ae7c6SLinus Walleij .phy_id = PHY_ID_VSC7395,
461975ae7c6SLinus Walleij .name = "Vitesse VSC7395",
462975ae7c6SLinus Walleij .phy_id_mask = 0x000ffff0,
463dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
464975ae7c6SLinus Walleij .config_init = vsc739x_config_init,
465975ae7c6SLinus Walleij .config_aneg = vsc73xx_config_aneg,
466975ae7c6SLinus Walleij .read_page = vsc73xx_read_page,
467975ae7c6SLinus Walleij .write_page = vsc73xx_write_page,
468975ae7c6SLinus Walleij }, {
469975ae7c6SLinus Walleij .phy_id = PHY_ID_VSC7398,
470975ae7c6SLinus Walleij .name = "Vitesse VSC7398",
471975ae7c6SLinus Walleij .phy_id_mask = 0x000ffff0,
472dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
473975ae7c6SLinus Walleij .config_init = vsc739x_config_init,
474975ae7c6SLinus Walleij .config_aneg = vsc73xx_config_aneg,
475975ae7c6SLinus Walleij .read_page = vsc73xx_read_page,
476975ae7c6SLinus Walleij .write_page = vsc73xx_write_page,
477975ae7c6SLinus Walleij }, {
47806ae4f84SSandeep Singh .phy_id = PHY_ID_VSC8662,
47906ae4f84SSandeep Singh .name = "Vitesse VSC8662",
48006ae4f84SSandeep Singh .phy_id_mask = 0x000ffff0,
481dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
48206ae4f84SSandeep Singh .config_init = &vsc824x_config_init,
4833fb69bcaSMadalin Bucur .config_aneg = &vsc82x4_config_aneg,
48406ae4f84SSandeep Singh .config_intr = &vsc82xx_config_intr,
485b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
48606ae4f84SSandeep Singh }, {
48711c6dd2cSTrent Piepho /* Vitesse 8221 */
48811c6dd2cSTrent Piepho .phy_id = PHY_ID_VSC8221,
48911c6dd2cSTrent Piepho .phy_id_mask = 0x000ffff0,
49011c6dd2cSTrent Piepho .name = "Vitesse VSC8221",
491dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
49211c6dd2cSTrent Piepho .config_init = &vsc8221_config_init,
49311c6dd2cSTrent Piepho .config_intr = &vsc82xx_config_intr,
494b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
4955a1cebd8SMichal Simek }, {
4965a1cebd8SMichal Simek /* Vitesse 8211 */
4975a1cebd8SMichal Simek .phy_id = PHY_ID_VSC8211,
4985a1cebd8SMichal Simek .phy_id_mask = 0x000ffff0,
4995a1cebd8SMichal Simek .name = "Vitesse VSC8211",
500dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */
5015a1cebd8SMichal Simek .config_init = &vsc8221_config_init,
5025a1cebd8SMichal Simek .config_intr = &vsc82xx_config_intr,
503b606ad8fSIoana Ciornei .handle_interrupt = &vsc82xx_handle_interrupt,
504d5bf9071SChristian Hohnstaedt } };
50511c6dd2cSTrent Piepho
50650fd7150SJohan Hovold module_phy_driver(vsc82xx_driver);
5074e4f10f6SDavid Woodhouse
508cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
5090508019cSAndy Fleming { PHY_ID_VSC8234, 0x000ffff0 },
5104e4f10f6SDavid Woodhouse { PHY_ID_VSC8244, 0x000fffc0 },
511dc855b3bSStephen Agate { PHY_ID_VSC8572, 0x000ffff0 },
512975ae7c6SLinus Walleij { PHY_ID_VSC7385, 0x000ffff0 },
513975ae7c6SLinus Walleij { PHY_ID_VSC7388, 0x000ffff0 },
514975ae7c6SLinus Walleij { PHY_ID_VSC7395, 0x000ffff0 },
515975ae7c6SLinus Walleij { PHY_ID_VSC7398, 0x000ffff0 },
51606ae4f84SSandeep Singh { PHY_ID_VSC8662, 0x000ffff0 },
5174e4f10f6SDavid Woodhouse { PHY_ID_VSC8221, 0x000ffff0 },
5185a1cebd8SMichal Simek { PHY_ID_VSC8211, 0x000ffff0 },
5194e4f10f6SDavid Woodhouse { }
5204e4f10f6SDavid Woodhouse };
5214e4f10f6SDavid Woodhouse
5224e4f10f6SDavid Woodhouse MODULE_DEVICE_TABLE(mdio, vitesse_tbl);
523