1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+
2b560a58cSFlorian Fainelli /*
3b560a58cSFlorian Fainelli * Broadcom BCM7xxx internal transceivers support.
4b560a58cSFlorian Fainelli *
583ee102aSDoug Berger * Copyright (C) 2014-2017 Broadcom
6b560a58cSFlorian Fainelli */
7b560a58cSFlorian Fainelli
8b560a58cSFlorian Fainelli #include <linux/module.h>
9b560a58cSFlorian Fainelli #include <linux/phy.h>
10b560a58cSFlorian Fainelli #include <linux/delay.h>
11a1cba561SArun Parameswaran #include "bcm-phy-lib.h"
12b560a58cSFlorian Fainelli #include <linux/bitops.h>
13b560a58cSFlorian Fainelli #include <linux/brcmphy.h>
14ba4ee3c0SFlorian Fainelli #include <linux/clk.h>
15b8f9a029SFlorian Fainelli #include <linux/mdio.h>
16b560a58cSFlorian Fainelli
17b560a58cSFlorian Fainelli /* Broadcom BCM7xxx internal PHY registers */
18b560a58cSFlorian Fainelli
1983ee102aSDoug Berger /* EPHY only register definitions */
20b560a58cSFlorian Fainelli #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21b560a58cSFlorian Fainelli #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22b560a58cSFlorian Fainelli #define MII_BCM7XXX_100TX_DISC 0x14
23b560a58cSFlorian Fainelli #define MII_BCM7XXX_AUX_MODE 0x1d
243ccc3055SFlorian Fainelli #define MII_BCM7XXX_64CLK_MDIO BIT(12)
25b560a58cSFlorian Fainelli #define MII_BCM7XXX_TEST 0x1f
26b560a58cSFlorian Fainelli #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
2783ee102aSDoug Berger #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
2883ee102aSDoug Berger #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
2983ee102aSDoug Berger #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
32d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_SHD_3_EEE_CAP 0x2
3383ee102aSDoug Berger #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
34d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_SHD_3_EEE_LP 0x4
35d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_SHD_3_EEE_WK_ERR 0x5
3683ee102aSDoug Berger #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
3783ee102aSDoug Berger #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
3883ee102aSDoug Berger #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
3983ee102aSDoug Berger #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
4083ee102aSDoug Berger #define MII_BCM7XXX_AN_EEE_EN BIT(1)
4183ee102aSDoug Berger #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
4283ee102aSDoug Berger #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
4383ee102aSDoug Berger #define MII_BCM7XXX_SHD_3_TL4 0x23
4483ee102aSDoug Berger #define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
45b560a58cSFlorian Fainelli
46b23ce9e8SFlorian Fainelli struct bcm7xxx_phy_priv {
47b23ce9e8SFlorian Fainelli u64 *stats;
48b23ce9e8SFlorian Fainelli };
49b23ce9e8SFlorian Fainelli
bcm7xxx_28nm_d0_afe_config_init(struct phy_device * phydev)50a490631fSFlorian Fainelli static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
51a490631fSFlorian Fainelli {
52a490631fSFlorian Fainelli /* AFE_RXCONFIG_0 */
53a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
54a490631fSFlorian Fainelli
55a490631fSFlorian Fainelli /* AFE_RXCONFIG_1 */
56a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
57a490631fSFlorian Fainelli
58a490631fSFlorian Fainelli /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
59a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
60a490631fSFlorian Fainelli
61a490631fSFlorian Fainelli /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
62a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
63a490631fSFlorian Fainelli
646da8253bSFlorian Fainelli /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
65a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
66a490631fSFlorian Fainelli
67a490631fSFlorian Fainelli /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
68a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
69a490631fSFlorian Fainelli
70a490631fSFlorian Fainelli /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
71a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
72a490631fSFlorian Fainelli
73a490631fSFlorian Fainelli /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
74a490631fSFlorian Fainelli * offset for HT=0 code
75a490631fSFlorian Fainelli */
76a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
77a490631fSFlorian Fainelli
78a490631fSFlorian Fainelli /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
799200c27aSArun Parameswaran phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
80a490631fSFlorian Fainelli
81a490631fSFlorian Fainelli /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
82a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
83a490631fSFlorian Fainelli
84a490631fSFlorian Fainelli /* Reset R_CAL/RC_CAL engine */
85f878fe56SFlorian Fainelli bcm_phy_r_rc_cal_reset(phydev);
86a490631fSFlorian Fainelli
87a490631fSFlorian Fainelli return 0;
88a490631fSFlorian Fainelli }
89a490631fSFlorian Fainelli
bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device * phydev)900c2fdc25SFlorian Fainelli static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
910c2fdc25SFlorian Fainelli {
920c2fdc25SFlorian Fainelli /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
93a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
940c2fdc25SFlorian Fainelli
956da8253bSFlorian Fainelli /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
96a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
976da8253bSFlorian Fainelli
980c2fdc25SFlorian Fainelli /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
99a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
1000c2fdc25SFlorian Fainelli
1010c2fdc25SFlorian Fainelli /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
1020c2fdc25SFlorian Fainelli * offset for HT=0 code
1030c2fdc25SFlorian Fainelli */
104a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
1050c2fdc25SFlorian Fainelli
1060c2fdc25SFlorian Fainelli /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
1079200c27aSArun Parameswaran phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
1080c2fdc25SFlorian Fainelli
1090c2fdc25SFlorian Fainelli /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
110a1cba561SArun Parameswaran bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
1110c2fdc25SFlorian Fainelli
1120c2fdc25SFlorian Fainelli /* Reset R_CAL/RC_CAL engine */
113f878fe56SFlorian Fainelli bcm_phy_r_rc_cal_reset(phydev);
1140c2fdc25SFlorian Fainelli
1150c2fdc25SFlorian Fainelli return 0;
1160c2fdc25SFlorian Fainelli }
1170c2fdc25SFlorian Fainelli
bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device * phydev)118039a7b85SFlorian Fainelli static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
119039a7b85SFlorian Fainelli {
120039a7b85SFlorian Fainelli /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
121039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
122039a7b85SFlorian Fainelli
123039a7b85SFlorian Fainelli /* Cut master bias current by 2% to compensate for RC_CAL offset */
124039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
125039a7b85SFlorian Fainelli
126039a7b85SFlorian Fainelli /* Improve hybrid leakage */
127039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
128039a7b85SFlorian Fainelli
129039a7b85SFlorian Fainelli /* Change rx_on_tune 8 to 0xf */
130039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
131039a7b85SFlorian Fainelli
132039a7b85SFlorian Fainelli /* Change 100Tx EEE bandwidth */
133039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
134039a7b85SFlorian Fainelli
135039a7b85SFlorian Fainelli /* Enable ffe zero detection for Vitesse interoperability */
136039a7b85SFlorian Fainelli bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
137039a7b85SFlorian Fainelli
138f878fe56SFlorian Fainelli bcm_phy_r_rc_cal_reset(phydev);
139039a7b85SFlorian Fainelli
140039a7b85SFlorian Fainelli return 0;
141039a7b85SFlorian Fainelli }
142039a7b85SFlorian Fainelli
bcm7xxx_28nm_config_init(struct phy_device * phydev)143b560a58cSFlorian Fainelli static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
144b560a58cSFlorian Fainelli {
145d8ebfed3SFlorian Fainelli u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
146d8ebfed3SFlorian Fainelli u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
147db88816bSFlorian Fainelli u8 count;
148d8ebfed3SFlorian Fainelli int ret = 0;
149b560a58cSFlorian Fainelli
150039a7b85SFlorian Fainelli /* Newer devices have moved the revision information back into a
151039a7b85SFlorian Fainelli * standard location in MII_PHYS_ID[23]
152039a7b85SFlorian Fainelli */
153039a7b85SFlorian Fainelli if (rev == 0)
154039a7b85SFlorian Fainelli rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
155039a7b85SFlorian Fainelli
1566ec259c1SFlorian Fainelli pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
15784eff6d1SAndrew Lunn phydev_name(phydev), phydev->drv->name, rev, patch);
158d8ebfed3SFlorian Fainelli
1598e346e15SFlorian Fainelli /* Dummy read to a register to workaround an issue upon reset where the
1608e346e15SFlorian Fainelli * internal inverter may not allow the first MDIO transaction to pass
1618e346e15SFlorian Fainelli * the MDIO management controller and make us return 0xffff for such
1628e346e15SFlorian Fainelli * reads.
1638e346e15SFlorian Fainelli */
1648e346e15SFlorian Fainelli phy_read(phydev, MII_BMSR);
1658e346e15SFlorian Fainelli
166d8ebfed3SFlorian Fainelli switch (rev) {
1676fdecfe3SArun Parameswaran case 0xa0:
168d8ebfed3SFlorian Fainelli case 0xb0:
169f878fe56SFlorian Fainelli ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
170d8ebfed3SFlorian Fainelli break;
171a490631fSFlorian Fainelli case 0xd0:
172a490631fSFlorian Fainelli ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
173a490631fSFlorian Fainelli break;
1740c2fdc25SFlorian Fainelli case 0xe0:
1750c2fdc25SFlorian Fainelli case 0xf0:
17660efff0cSFlorian Fainelli /* Rev G0 introduces a roll over */
17760efff0cSFlorian Fainelli case 0x10:
1780c2fdc25SFlorian Fainelli ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
1790c2fdc25SFlorian Fainelli break;
180039a7b85SFlorian Fainelli case 0x01:
181039a7b85SFlorian Fainelli ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
182039a7b85SFlorian Fainelli break;
183d8ebfed3SFlorian Fainelli default:
184d8ebfed3SFlorian Fainelli break;
185d8ebfed3SFlorian Fainelli }
186d8ebfed3SFlorian Fainelli
1879df54ddaSFlorian Fainelli if (ret)
1889df54ddaSFlorian Fainelli return ret;
1899df54ddaSFlorian Fainelli
190ab41ca34SMurali Krishna Policharla ret = bcm_phy_enable_jumbo(phydev);
191ab41ca34SMurali Krishna Policharla if (ret)
192ab41ca34SMurali Krishna Policharla return ret;
193ab41ca34SMurali Krishna Policharla
194db88816bSFlorian Fainelli ret = bcm_phy_downshift_get(phydev, &count);
195db88816bSFlorian Fainelli if (ret)
196db88816bSFlorian Fainelli return ret;
197db88816bSFlorian Fainelli
198db88816bSFlorian Fainelli /* Only enable EEE if Wirespeed/downshift is disabled */
199db88816bSFlorian Fainelli ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
200b8f9a029SFlorian Fainelli if (ret)
201b8f9a029SFlorian Fainelli return ret;
202b8f9a029SFlorian Fainelli
203a1cba561SArun Parameswaran return bcm_phy_enable_apd(phydev, true);
204b560a58cSFlorian Fainelli }
205b560a58cSFlorian Fainelli
bcm7xxx_28nm_resume(struct phy_device * phydev)2064fd14e0bSFlorian Fainelli static int bcm7xxx_28nm_resume(struct phy_device *phydev)
2074fd14e0bSFlorian Fainelli {
2084fd14e0bSFlorian Fainelli int ret;
2094fd14e0bSFlorian Fainelli
2104fd14e0bSFlorian Fainelli /* Re-apply workarounds coming out suspend/resume */
2114fd14e0bSFlorian Fainelli ret = bcm7xxx_28nm_config_init(phydev);
2124fd14e0bSFlorian Fainelli if (ret)
2134fd14e0bSFlorian Fainelli return ret;
2144fd14e0bSFlorian Fainelli
2154fd14e0bSFlorian Fainelli /* 28nm Gigabit PHYs come out of reset without any half-duplex
2164fd14e0bSFlorian Fainelli * or "hub" compliant advertised mode, fix that. This does not
2174fd14e0bSFlorian Fainelli * cause any problems with the PHY library since genphy_config_aneg()
2184fd14e0bSFlorian Fainelli * gracefully handles auto-negotiated and forced modes.
2194fd14e0bSFlorian Fainelli */
2204fd14e0bSFlorian Fainelli return genphy_config_aneg(phydev);
2214fd14e0bSFlorian Fainelli }
2224fd14e0bSFlorian Fainelli
__phy_set_clr_bits(struct phy_device * dev,int location,int set_mask,int clr_mask)223d88fd1b5SFlorian Fainelli static int __phy_set_clr_bits(struct phy_device *dev, int location,
224b560a58cSFlorian Fainelli int set_mask, int clr_mask)
225b560a58cSFlorian Fainelli {
226b560a58cSFlorian Fainelli int v, ret;
227b560a58cSFlorian Fainelli
228d88fd1b5SFlorian Fainelli v = __phy_read(dev, location);
229b560a58cSFlorian Fainelli if (v < 0)
230b560a58cSFlorian Fainelli return v;
231b560a58cSFlorian Fainelli
232b560a58cSFlorian Fainelli v &= ~clr_mask;
233b560a58cSFlorian Fainelli v |= set_mask;
234b560a58cSFlorian Fainelli
235d88fd1b5SFlorian Fainelli ret = __phy_write(dev, location, v);
236b560a58cSFlorian Fainelli if (ret < 0)
237b560a58cSFlorian Fainelli return ret;
238b560a58cSFlorian Fainelli
239b560a58cSFlorian Fainelli return v;
240b560a58cSFlorian Fainelli }
241b560a58cSFlorian Fainelli
phy_set_clr_bits(struct phy_device * dev,int location,int set_mask,int clr_mask)242d88fd1b5SFlorian Fainelli static int phy_set_clr_bits(struct phy_device *dev, int location,
243d88fd1b5SFlorian Fainelli int set_mask, int clr_mask)
244d88fd1b5SFlorian Fainelli {
245d88fd1b5SFlorian Fainelli int ret;
246d88fd1b5SFlorian Fainelli
247d88fd1b5SFlorian Fainelli mutex_lock(&dev->mdio.bus->mdio_lock);
248d88fd1b5SFlorian Fainelli ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask);
249d88fd1b5SFlorian Fainelli mutex_unlock(&dev->mdio.bus->mdio_lock);
250d88fd1b5SFlorian Fainelli
251d88fd1b5SFlorian Fainelli return ret;
252d88fd1b5SFlorian Fainelli }
253d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device * phydev)25483ee102aSDoug Berger static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
25583ee102aSDoug Berger {
25683ee102aSDoug Berger int ret;
25783ee102aSDoug Berger
25883ee102aSDoug Berger /* set shadow mode 2 */
25983ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
26083ee102aSDoug Berger MII_BCM7XXX_SHD_MODE_2, 0);
26183ee102aSDoug Berger if (ret < 0)
26283ee102aSDoug Berger return ret;
26383ee102aSDoug Berger
26483ee102aSDoug Berger /* Set current trim values INT_trim = -1, Ext_trim =0 */
26583ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
26683ee102aSDoug Berger if (ret < 0)
26783ee102aSDoug Berger goto reset_shadow_mode;
26883ee102aSDoug Berger
26983ee102aSDoug Berger /* Cal reset */
27083ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
27183ee102aSDoug Berger MII_BCM7XXX_SHD_3_TL4);
27283ee102aSDoug Berger if (ret < 0)
27383ee102aSDoug Berger goto reset_shadow_mode;
27483ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
27583ee102aSDoug Berger MII_BCM7XXX_TL4_RST_MSK, 0);
27683ee102aSDoug Berger if (ret < 0)
27783ee102aSDoug Berger goto reset_shadow_mode;
27883ee102aSDoug Berger
27983ee102aSDoug Berger /* Cal reset disable */
28083ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
28183ee102aSDoug Berger MII_BCM7XXX_SHD_3_TL4);
28283ee102aSDoug Berger if (ret < 0)
28383ee102aSDoug Berger goto reset_shadow_mode;
28483ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
28583ee102aSDoug Berger 0, MII_BCM7XXX_TL4_RST_MSK);
28683ee102aSDoug Berger if (ret < 0)
28783ee102aSDoug Berger goto reset_shadow_mode;
28883ee102aSDoug Berger
28983ee102aSDoug Berger reset_shadow_mode:
29083ee102aSDoug Berger /* reset shadow mode 2 */
29183ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
29283ee102aSDoug Berger MII_BCM7XXX_SHD_MODE_2);
29383ee102aSDoug Berger if (ret < 0)
29483ee102aSDoug Berger return ret;
29583ee102aSDoug Berger
29683ee102aSDoug Berger return 0;
29783ee102aSDoug Berger }
29883ee102aSDoug Berger
29983ee102aSDoug Berger /* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
bcm7xxx_28nm_ephy_apd_enable(struct phy_device * phydev)30083ee102aSDoug Berger static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
30183ee102aSDoug Berger {
30283ee102aSDoug Berger int ret;
30383ee102aSDoug Berger
30483ee102aSDoug Berger /* set shadow mode 1 */
30583ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
30683ee102aSDoug Berger MII_BRCM_FET_BT_SRE, 0);
30783ee102aSDoug Berger if (ret < 0)
30883ee102aSDoug Berger return ret;
30983ee102aSDoug Berger
31083ee102aSDoug Berger /* Enable auto-power down */
31183ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
31283ee102aSDoug Berger MII_BRCM_FET_SHDW_AS2_APDE, 0);
31383ee102aSDoug Berger if (ret < 0)
31483ee102aSDoug Berger return ret;
31583ee102aSDoug Berger
31683ee102aSDoug Berger /* reset shadow mode 1 */
31783ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
31883ee102aSDoug Berger MII_BRCM_FET_BT_SRE);
31983ee102aSDoug Berger if (ret < 0)
32083ee102aSDoug Berger return ret;
32183ee102aSDoug Berger
32283ee102aSDoug Berger return 0;
32383ee102aSDoug Berger }
32483ee102aSDoug Berger
bcm7xxx_28nm_ephy_eee_enable(struct phy_device * phydev)32583ee102aSDoug Berger static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
32683ee102aSDoug Berger {
32783ee102aSDoug Berger int ret;
32883ee102aSDoug Berger
32983ee102aSDoug Berger /* set shadow mode 2 */
33083ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
33183ee102aSDoug Berger MII_BCM7XXX_SHD_MODE_2, 0);
33283ee102aSDoug Berger if (ret < 0)
33383ee102aSDoug Berger return ret;
33483ee102aSDoug Berger
33583ee102aSDoug Berger /* Advertise supported modes */
33683ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
33783ee102aSDoug Berger MII_BCM7XXX_SHD_3_AN_EEE_ADV);
33883ee102aSDoug Berger if (ret < 0)
33983ee102aSDoug Berger goto reset_shadow_mode;
34083ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
34183ee102aSDoug Berger MDIO_EEE_100TX);
34283ee102aSDoug Berger if (ret < 0)
34383ee102aSDoug Berger goto reset_shadow_mode;
34483ee102aSDoug Berger
34583ee102aSDoug Berger /* Restore Defaults */
34683ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
34783ee102aSDoug Berger MII_BCM7XXX_SHD_3_PCS_CTRL_2);
34883ee102aSDoug Berger if (ret < 0)
34983ee102aSDoug Berger goto reset_shadow_mode;
35083ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
35183ee102aSDoug Berger MII_BCM7XXX_PCS_CTRL_2_DEF);
35283ee102aSDoug Berger if (ret < 0)
35383ee102aSDoug Berger goto reset_shadow_mode;
35483ee102aSDoug Berger
35583ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
35683ee102aSDoug Berger MII_BCM7XXX_SHD_3_EEE_THRESH);
35783ee102aSDoug Berger if (ret < 0)
35883ee102aSDoug Berger goto reset_shadow_mode;
35983ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
36083ee102aSDoug Berger MII_BCM7XXX_EEE_THRESH_DEF);
36183ee102aSDoug Berger if (ret < 0)
36283ee102aSDoug Berger goto reset_shadow_mode;
36383ee102aSDoug Berger
36483ee102aSDoug Berger /* Enable EEE autonegotiation */
36583ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
36683ee102aSDoug Berger MII_BCM7XXX_SHD_3_AN_STAT);
36783ee102aSDoug Berger if (ret < 0)
36883ee102aSDoug Berger goto reset_shadow_mode;
36983ee102aSDoug Berger ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
37083ee102aSDoug Berger (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
37183ee102aSDoug Berger if (ret < 0)
37283ee102aSDoug Berger goto reset_shadow_mode;
37383ee102aSDoug Berger
37483ee102aSDoug Berger reset_shadow_mode:
37583ee102aSDoug Berger /* reset shadow mode 2 */
37683ee102aSDoug Berger ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
37783ee102aSDoug Berger MII_BCM7XXX_SHD_MODE_2);
37883ee102aSDoug Berger if (ret < 0)
37983ee102aSDoug Berger return ret;
38083ee102aSDoug Berger
38183ee102aSDoug Berger /* Restart autoneg */
38283ee102aSDoug Berger phy_write(phydev, MII_BMCR,
38383ee102aSDoug Berger (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
38483ee102aSDoug Berger
38583ee102aSDoug Berger return 0;
38683ee102aSDoug Berger }
38783ee102aSDoug Berger
bcm7xxx_28nm_ephy_config_init(struct phy_device * phydev)38883ee102aSDoug Berger static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
38983ee102aSDoug Berger {
39083ee102aSDoug Berger u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
39183ee102aSDoug Berger int ret = 0;
39283ee102aSDoug Berger
39383ee102aSDoug Berger pr_info_once("%s: %s PHY revision: 0x%02x\n",
39483ee102aSDoug Berger phydev_name(phydev), phydev->drv->name, rev);
39583ee102aSDoug Berger
39683ee102aSDoug Berger /* Dummy read to a register to workaround a possible issue upon reset
39783ee102aSDoug Berger * where the internal inverter may not allow the first MDIO transaction
39883ee102aSDoug Berger * to pass the MDIO management controller and make us return 0xffff for
39983ee102aSDoug Berger * such reads.
40083ee102aSDoug Berger */
40183ee102aSDoug Berger phy_read(phydev, MII_BMSR);
40283ee102aSDoug Berger
40383ee102aSDoug Berger /* Apply AFE software work-around if necessary */
40483ee102aSDoug Berger if (rev == 0x01) {
40583ee102aSDoug Berger ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
40683ee102aSDoug Berger if (ret)
40783ee102aSDoug Berger return ret;
40883ee102aSDoug Berger }
40983ee102aSDoug Berger
41083ee102aSDoug Berger ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
41183ee102aSDoug Berger if (ret)
41283ee102aSDoug Berger return ret;
41383ee102aSDoug Berger
41483ee102aSDoug Berger return bcm7xxx_28nm_ephy_apd_enable(phydev);
41583ee102aSDoug Berger }
41683ee102aSDoug Berger
bcm7xxx_16nm_ephy_afe_config(struct phy_device * phydev)417f68d08c4SFlorian Fainelli static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev)
418f68d08c4SFlorian Fainelli {
419f68d08c4SFlorian Fainelli int tmp, rcalcode, rcalnewcodelp, rcalnewcode11, rcalnewcode11d2;
420f68d08c4SFlorian Fainelli
421f68d08c4SFlorian Fainelli /* Reset PHY */
422f68d08c4SFlorian Fainelli tmp = genphy_soft_reset(phydev);
423f68d08c4SFlorian Fainelli if (tmp)
424f68d08c4SFlorian Fainelli return tmp;
425f68d08c4SFlorian Fainelli
426f68d08c4SFlorian Fainelli /* Reset AFE and PLL */
427f68d08c4SFlorian Fainelli bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006);
428f68d08c4SFlorian Fainelli /* Clear reset */
429f68d08c4SFlorian Fainelli bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000);
430f68d08c4SFlorian Fainelli
431f68d08c4SFlorian Fainelli /* Write PLL/AFE control register to select 54MHz crystal */
432f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000);
433f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a);
434f68d08c4SFlorian Fainelli
435f68d08c4SFlorian Fainelli /* Change Ka,Kp,Ki to pdiv=1 */
436f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1);
437f68d08c4SFlorian Fainelli /* Configuration override */
438f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000);
439f68d08c4SFlorian Fainelli
440f68d08c4SFlorian Fainelli /* Change PLL_NDIV and PLL_NUDGE */
441f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68);
442f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000);
443f68d08c4SFlorian Fainelli
444f68d08c4SFlorian Fainelli /* Reference frequency is 54Mhz, config_mode[15:14] = 3 (low
445f68d08c4SFlorian Fainelli * phase)
446f68d08c4SFlorian Fainelli */
447f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036);
448f68d08c4SFlorian Fainelli
449f68d08c4SFlorian Fainelli /* Initialize bypass mode */
450f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000);
451f68d08c4SFlorian Fainelli /* Bypass code, default: VCOCLK enabled */
452f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002);
453f68d08c4SFlorian Fainelli /* LDOs at default setting */
454f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0);
455f68d08c4SFlorian Fainelli /* Release PLL reset */
456f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001);
457f68d08c4SFlorian Fainelli
458f68d08c4SFlorian Fainelli /* Bandgap curvature correction to correct default */
459f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010);
460f68d08c4SFlorian Fainelli
461f68d08c4SFlorian Fainelli /* Run RCAL */
462f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038);
463f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b);
464f68d08c4SFlorian Fainelli udelay(2);
465f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f);
466f68d08c4SFlorian Fainelli mdelay(5);
467f68d08c4SFlorian Fainelli
468f68d08c4SFlorian Fainelli /* AFE_CAL_CONFIG_0, Vref=1000, Target=10, averaging enabled */
469f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82);
470f68d08c4SFlorian Fainelli /* AFE_CAL_CONFIG_0, no reset and analog powerup */
471f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82);
472f68d08c4SFlorian Fainelli udelay(2);
473f68d08c4SFlorian Fainelli /* AFE_CAL_CONFIG_0, start calibration */
474f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82);
475f68d08c4SFlorian Fainelli udelay(100);
476f68d08c4SFlorian Fainelli /* AFE_CAL_CONFIG_0, clear start calibration, set HiBW */
477f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86);
478f68d08c4SFlorian Fainelli udelay(2);
479f68d08c4SFlorian Fainelli /* AFE_CAL_CONFIG_0, start calibration with hi BW mode set */
480f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86);
481f68d08c4SFlorian Fainelli udelay(100);
482f68d08c4SFlorian Fainelli
483f68d08c4SFlorian Fainelli /* Adjust 10BT amplitude additional +7% and 100BT +2% */
484f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea);
485f68d08c4SFlorian Fainelli /* Adjust 1G mode amplitude and 1G testmode1 */
486f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0);
487f68d08c4SFlorian Fainelli
488f68d08c4SFlorian Fainelli /* Read CORE_EXPA9 */
489582dbb2cSFlorian Fainelli tmp = bcm_phy_read_exp_sel(phydev, 0x00a9);
490f68d08c4SFlorian Fainelli /* CORE_EXPA9[6:1] is rcalcode[5:0] */
491f68d08c4SFlorian Fainelli rcalcode = (tmp & 0x7e) / 2;
492f68d08c4SFlorian Fainelli /* Correct RCAL code + 1 is -1% rprogr, LP: +16 */
493f68d08c4SFlorian Fainelli rcalnewcodelp = rcalcode + 16;
494f68d08c4SFlorian Fainelli /* Correct RCAL code + 1 is -15 rprogr, 11: +10 */
495f68d08c4SFlorian Fainelli rcalnewcode11 = rcalcode + 10;
496f68d08c4SFlorian Fainelli /* Saturate if necessary */
497f68d08c4SFlorian Fainelli if (rcalnewcodelp > 0x3f)
498f68d08c4SFlorian Fainelli rcalnewcodelp = 0x3f;
499f68d08c4SFlorian Fainelli if (rcalnewcode11 > 0x3f)
500f68d08c4SFlorian Fainelli rcalnewcode11 = 0x3f;
501f68d08c4SFlorian Fainelli /* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */
502f68d08c4SFlorian Fainelli tmp = 0x00f8 + rcalnewcodelp * 256;
503f68d08c4SFlorian Fainelli /* Program into AFE_CAL_CONFIG_2 */
504f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp);
505f68d08c4SFlorian Fainelli /* AFE_BIAS_CONFIG_0 10BT bias code (Bias: E4) */
506f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4);
507f68d08c4SFlorian Fainelli /* invert adc clock output and 'adc refp ldo current To correct
508f68d08c4SFlorian Fainelli * default
509f68d08c4SFlorian Fainelli */
510f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002);
511f68d08c4SFlorian Fainelli /* 100BT stair case, high BW, 1G stair case, alternate encode */
512f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882);
513f68d08c4SFlorian Fainelli /* 1000BT DAC transition method per Erol, bits[32], DAC Shuffle
514f68d08c4SFlorian Fainelli * sequence 1 + 10BT imp adjust bits
515f68d08c4SFlorian Fainelli */
516f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201);
517f68d08c4SFlorian Fainelli /* Non-overlap fix */
518f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00);
519f68d08c4SFlorian Fainelli
520f68d08c4SFlorian Fainelli /* pwdb override (rxconfig<5>) to turn on RX LDO indpendent of
521f68d08c4SFlorian Fainelli * pwdb controls from DSP_TAP10
522f68d08c4SFlorian Fainelli */
523f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020);
524f68d08c4SFlorian Fainelli
525f68d08c4SFlorian Fainelli /* Remove references to channel 2 and 3 */
526f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000);
527f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000);
528f68d08c4SFlorian Fainelli
529f68d08c4SFlorian Fainelli /* Set cal_bypassb bit rxconfig<43> */
530f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800);
531f68d08c4SFlorian Fainelli udelay(2);
532f68d08c4SFlorian Fainelli
533f68d08c4SFlorian Fainelli /* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr
534f68d08c4SFlorian Fainelli * is controlled by DSP.
535f68d08c4SFlorian Fainelli */
536f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000);
537f68d08c4SFlorian Fainelli
538f68d08c4SFlorian Fainelli /* Drop LSB */
539f68d08c4SFlorian Fainelli rcalnewcode11d2 = (rcalnewcode11 & 0xfffe) / 2;
540f68d08c4SFlorian Fainelli tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001);
541f68d08c4SFlorian Fainelli /* Clear bits [11:5] */
542f68d08c4SFlorian Fainelli tmp &= ~0xfe0;
543f68d08c4SFlorian Fainelli /* set txcfg_ch0<5>=1 (enable + set local rcal) */
544f68d08c4SFlorian Fainelli tmp |= 0x0020 | (rcalnewcode11d2 * 64);
545f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp);
546f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp);
547f68d08c4SFlorian Fainelli
548f68d08c4SFlorian Fainelli tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000);
549f68d08c4SFlorian Fainelli /* set txcfg<45:44>=11 (enable Rextra + invert fullscaledetect)
550f68d08c4SFlorian Fainelli */
551f68d08c4SFlorian Fainelli tmp &= ~0x3000;
552f68d08c4SFlorian Fainelli tmp |= 0x3000;
553f68d08c4SFlorian Fainelli bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp);
554f68d08c4SFlorian Fainelli
555f68d08c4SFlorian Fainelli return 0;
556f68d08c4SFlorian Fainelli }
557f68d08c4SFlorian Fainelli
bcm7xxx_16nm_ephy_config_init(struct phy_device * phydev)558f68d08c4SFlorian Fainelli static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev)
559f68d08c4SFlorian Fainelli {
560f68d08c4SFlorian Fainelli int ret, val;
561f68d08c4SFlorian Fainelli
562f68d08c4SFlorian Fainelli ret = bcm7xxx_16nm_ephy_afe_config(phydev);
563f68d08c4SFlorian Fainelli if (ret)
564f68d08c4SFlorian Fainelli return ret;
565f68d08c4SFlorian Fainelli
566f68d08c4SFlorian Fainelli ret = bcm_phy_set_eee(phydev, true);
567f68d08c4SFlorian Fainelli if (ret)
568f68d08c4SFlorian Fainelli return ret;
569f68d08c4SFlorian Fainelli
570f68d08c4SFlorian Fainelli ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
571f68d08c4SFlorian Fainelli if (ret < 0)
572f68d08c4SFlorian Fainelli return ret;
573f68d08c4SFlorian Fainelli
574f68d08c4SFlorian Fainelli val = ret;
575f68d08c4SFlorian Fainelli
576f68d08c4SFlorian Fainelli /* Auto power down of DLL enabled,
577f68d08c4SFlorian Fainelli * TXC/RXC disabled during auto power down.
578f68d08c4SFlorian Fainelli */
579f68d08c4SFlorian Fainelli val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
580f68d08c4SFlorian Fainelli val |= BIT(8);
581f68d08c4SFlorian Fainelli
582f68d08c4SFlorian Fainelli ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
583f68d08c4SFlorian Fainelli if (ret < 0)
584f68d08c4SFlorian Fainelli return ret;
585f68d08c4SFlorian Fainelli
586f68d08c4SFlorian Fainelli return bcm_phy_enable_apd(phydev, true);
587f68d08c4SFlorian Fainelli }
588f68d08c4SFlorian Fainelli
bcm7xxx_16nm_ephy_resume(struct phy_device * phydev)589f68d08c4SFlorian Fainelli static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev)
590f68d08c4SFlorian Fainelli {
591f68d08c4SFlorian Fainelli int ret;
592f68d08c4SFlorian Fainelli
593f68d08c4SFlorian Fainelli /* Re-apply workarounds coming out suspend/resume */
594f68d08c4SFlorian Fainelli ret = bcm7xxx_16nm_ephy_config_init(phydev);
595f68d08c4SFlorian Fainelli if (ret)
596f68d08c4SFlorian Fainelli return ret;
597f68d08c4SFlorian Fainelli
598f68d08c4SFlorian Fainelli return genphy_config_aneg(phydev);
599f68d08c4SFlorian Fainelli }
600f68d08c4SFlorian Fainelli
601d88fd1b5SFlorian Fainelli #define MII_BCM7XXX_REG_INVALID 0xff
602d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)603d88fd1b5SFlorian Fainelli static u8 bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)
604d88fd1b5SFlorian Fainelli {
605d88fd1b5SFlorian Fainelli switch (regnum) {
606d88fd1b5SFlorian Fainelli case MDIO_CTRL1:
607d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_PCS_CTRL;
608d88fd1b5SFlorian Fainelli case MDIO_STAT1:
609d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_PCS_STATUS;
610d88fd1b5SFlorian Fainelli case MDIO_PCS_EEE_ABLE:
611d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_EEE_CAP;
612d88fd1b5SFlorian Fainelli case MDIO_AN_EEE_ADV:
613d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_AN_EEE_ADV;
614d88fd1b5SFlorian Fainelli case MDIO_AN_EEE_LPABLE:
615d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_EEE_LP;
616d88fd1b5SFlorian Fainelli case MDIO_PCS_EEE_WK_ERR:
617d88fd1b5SFlorian Fainelli return MII_BCM7XXX_SHD_3_EEE_WK_ERR;
618d88fd1b5SFlorian Fainelli default:
619d88fd1b5SFlorian Fainelli return MII_BCM7XXX_REG_INVALID;
620d88fd1b5SFlorian Fainelli }
621d88fd1b5SFlorian Fainelli }
622d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_dev_valid(int devnum)623d88fd1b5SFlorian Fainelli static bool bcm7xxx_28nm_ephy_dev_valid(int devnum)
624d88fd1b5SFlorian Fainelli {
625d88fd1b5SFlorian Fainelli return devnum == MDIO_MMD_AN || devnum == MDIO_MMD_PCS;
626d88fd1b5SFlorian Fainelli }
627d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)628d88fd1b5SFlorian Fainelli static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
629d88fd1b5SFlorian Fainelli int devnum, u16 regnum)
630d88fd1b5SFlorian Fainelli {
631d88fd1b5SFlorian Fainelli u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
632d88fd1b5SFlorian Fainelli int ret;
633d88fd1b5SFlorian Fainelli
634d88fd1b5SFlorian Fainelli if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
635d88fd1b5SFlorian Fainelli shd == MII_BCM7XXX_REG_INVALID)
636d88fd1b5SFlorian Fainelli return -EOPNOTSUPP;
637d88fd1b5SFlorian Fainelli
638d88fd1b5SFlorian Fainelli /* set shadow mode 2 */
639d88fd1b5SFlorian Fainelli ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
640d88fd1b5SFlorian Fainelli MII_BCM7XXX_SHD_MODE_2, 0);
641d88fd1b5SFlorian Fainelli if (ret < 0)
642d88fd1b5SFlorian Fainelli return ret;
643d88fd1b5SFlorian Fainelli
644d88fd1b5SFlorian Fainelli /* Access the desired shadow register address */
645d88fd1b5SFlorian Fainelli ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
646d88fd1b5SFlorian Fainelli if (ret < 0)
647d88fd1b5SFlorian Fainelli goto reset_shadow_mode;
648d88fd1b5SFlorian Fainelli
649d88fd1b5SFlorian Fainelli ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT);
650d88fd1b5SFlorian Fainelli
651d88fd1b5SFlorian Fainelli reset_shadow_mode:
652d88fd1b5SFlorian Fainelli /* reset shadow mode 2 */
653d88fd1b5SFlorian Fainelli __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
654d88fd1b5SFlorian Fainelli MII_BCM7XXX_SHD_MODE_2);
655d88fd1b5SFlorian Fainelli return ret;
656d88fd1b5SFlorian Fainelli }
657d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)658d88fd1b5SFlorian Fainelli static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
659d88fd1b5SFlorian Fainelli int devnum, u16 regnum, u16 val)
660d88fd1b5SFlorian Fainelli {
661d88fd1b5SFlorian Fainelli u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
662d88fd1b5SFlorian Fainelli int ret;
663d88fd1b5SFlorian Fainelli
664d88fd1b5SFlorian Fainelli if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
665d88fd1b5SFlorian Fainelli shd == MII_BCM7XXX_REG_INVALID)
666d88fd1b5SFlorian Fainelli return -EOPNOTSUPP;
667d88fd1b5SFlorian Fainelli
668d88fd1b5SFlorian Fainelli /* set shadow mode 2 */
669d88fd1b5SFlorian Fainelli ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
670d88fd1b5SFlorian Fainelli MII_BCM7XXX_SHD_MODE_2, 0);
671d88fd1b5SFlorian Fainelli if (ret < 0)
672d88fd1b5SFlorian Fainelli return ret;
673d88fd1b5SFlorian Fainelli
674d88fd1b5SFlorian Fainelli /* Access the desired shadow register address */
675d88fd1b5SFlorian Fainelli ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
676d88fd1b5SFlorian Fainelli if (ret < 0)
677d88fd1b5SFlorian Fainelli goto reset_shadow_mode;
678d88fd1b5SFlorian Fainelli
679d88fd1b5SFlorian Fainelli /* Write the desired value in the shadow register */
680d88fd1b5SFlorian Fainelli __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val);
681d88fd1b5SFlorian Fainelli
682d88fd1b5SFlorian Fainelli reset_shadow_mode:
683d88fd1b5SFlorian Fainelli /* reset shadow mode 2 */
684d88fd1b5SFlorian Fainelli return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
685d88fd1b5SFlorian Fainelli MII_BCM7XXX_SHD_MODE_2);
686d88fd1b5SFlorian Fainelli }
687d88fd1b5SFlorian Fainelli
bcm7xxx_28nm_ephy_resume(struct phy_device * phydev)68883ee102aSDoug Berger static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
68983ee102aSDoug Berger {
69083ee102aSDoug Berger int ret;
69183ee102aSDoug Berger
69283ee102aSDoug Berger /* Re-apply workarounds coming out suspend/resume */
69383ee102aSDoug Berger ret = bcm7xxx_28nm_ephy_config_init(phydev);
69483ee102aSDoug Berger if (ret)
69583ee102aSDoug Berger return ret;
69683ee102aSDoug Berger
69783ee102aSDoug Berger return genphy_config_aneg(phydev);
69883ee102aSDoug Berger }
69983ee102aSDoug Berger
bcm7xxx_config_init(struct phy_device * phydev)700b560a58cSFlorian Fainelli static int bcm7xxx_config_init(struct phy_device *phydev)
701b560a58cSFlorian Fainelli {
702b560a58cSFlorian Fainelli int ret;
703b560a58cSFlorian Fainelli
704b560a58cSFlorian Fainelli /* Enable 64 clock MDIO */
7053ccc3055SFlorian Fainelli phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
706b560a58cSFlorian Fainelli phy_read(phydev, MII_BCM7XXX_AUX_MODE);
707b560a58cSFlorian Fainelli
708b560a58cSFlorian Fainelli /* set shadow mode 2 */
709b560a58cSFlorian Fainelli ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
710b560a58cSFlorian Fainelli MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
711b560a58cSFlorian Fainelli if (ret < 0)
712b560a58cSFlorian Fainelli return ret;
713b560a58cSFlorian Fainelli
714b560a58cSFlorian Fainelli /* set iddq_clkbias */
715b560a58cSFlorian Fainelli phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
716b560a58cSFlorian Fainelli udelay(10);
717b560a58cSFlorian Fainelli
718b560a58cSFlorian Fainelli /* reset iddq_clkbias */
719b560a58cSFlorian Fainelli phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
720b560a58cSFlorian Fainelli
721b560a58cSFlorian Fainelli phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
722b560a58cSFlorian Fainelli
723b560a58cSFlorian Fainelli /* reset shadow mode 2 */
72450d89980SFlorian Fainelli ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
725b560a58cSFlorian Fainelli if (ret < 0)
726b560a58cSFlorian Fainelli return ret;
727b560a58cSFlorian Fainelli
728b560a58cSFlorian Fainelli return 0;
729b560a58cSFlorian Fainelli }
730b560a58cSFlorian Fainelli
731b560a58cSFlorian Fainelli /* Workaround for putting the PHY in IDDQ mode, required
73282c084f5SFlorian Fainelli * for all BCM7XXX 40nm and 65nm PHYs
733b560a58cSFlorian Fainelli */
bcm7xxx_suspend(struct phy_device * phydev)734b560a58cSFlorian Fainelli static int bcm7xxx_suspend(struct phy_device *phydev)
735b560a58cSFlorian Fainelli {
736b560a58cSFlorian Fainelli int ret;
73733c81821SColin Ian King static const struct bcm7xxx_regs {
738b560a58cSFlorian Fainelli int reg;
739b560a58cSFlorian Fainelli u16 value;
740b560a58cSFlorian Fainelli } bcm7xxx_suspend_cfg[] = {
741b560a58cSFlorian Fainelli { MII_BCM7XXX_TEST, 0x008b },
742b560a58cSFlorian Fainelli { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
743b560a58cSFlorian Fainelli { MII_BCM7XXX_100TX_DISC, 0x7000 },
744b560a58cSFlorian Fainelli { MII_BCM7XXX_TEST, 0x000f },
745b560a58cSFlorian Fainelli { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
746b560a58cSFlorian Fainelli { MII_BCM7XXX_TEST, 0x000b },
747b560a58cSFlorian Fainelli };
748b560a58cSFlorian Fainelli unsigned int i;
749b560a58cSFlorian Fainelli
750b560a58cSFlorian Fainelli for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
751b560a58cSFlorian Fainelli ret = phy_write(phydev,
752b560a58cSFlorian Fainelli bcm7xxx_suspend_cfg[i].reg,
753b560a58cSFlorian Fainelli bcm7xxx_suspend_cfg[i].value);
754b560a58cSFlorian Fainelli if (ret)
755b560a58cSFlorian Fainelli return ret;
756b560a58cSFlorian Fainelli }
757b560a58cSFlorian Fainelli
758b560a58cSFlorian Fainelli return 0;
759b560a58cSFlorian Fainelli }
760b560a58cSFlorian Fainelli
bcm7xxx_28nm_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)761db88816bSFlorian Fainelli static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
762db88816bSFlorian Fainelli struct ethtool_tunable *tuna,
763db88816bSFlorian Fainelli void *data)
764db88816bSFlorian Fainelli {
765db88816bSFlorian Fainelli switch (tuna->id) {
766db88816bSFlorian Fainelli case ETHTOOL_PHY_DOWNSHIFT:
767db88816bSFlorian Fainelli return bcm_phy_downshift_get(phydev, (u8 *)data);
768db88816bSFlorian Fainelli default:
769db88816bSFlorian Fainelli return -EOPNOTSUPP;
770db88816bSFlorian Fainelli }
771db88816bSFlorian Fainelli }
772db88816bSFlorian Fainelli
bcm7xxx_28nm_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)773db88816bSFlorian Fainelli static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
774db88816bSFlorian Fainelli struct ethtool_tunable *tuna,
775db88816bSFlorian Fainelli const void *data)
776db88816bSFlorian Fainelli {
777db88816bSFlorian Fainelli u8 count = *(u8 *)data;
778db88816bSFlorian Fainelli int ret;
779db88816bSFlorian Fainelli
780db88816bSFlorian Fainelli switch (tuna->id) {
781db88816bSFlorian Fainelli case ETHTOOL_PHY_DOWNSHIFT:
782db88816bSFlorian Fainelli ret = bcm_phy_downshift_set(phydev, count);
783db88816bSFlorian Fainelli break;
784db88816bSFlorian Fainelli default:
785db88816bSFlorian Fainelli return -EOPNOTSUPP;
786db88816bSFlorian Fainelli }
787db88816bSFlorian Fainelli
788db88816bSFlorian Fainelli if (ret)
789db88816bSFlorian Fainelli return ret;
790db88816bSFlorian Fainelli
791cc1122b0SColin Ian King /* Disable EEE advertisement since this prevents the PHY
792db88816bSFlorian Fainelli * from successfully linking up, trigger auto-negotiation restart
793db88816bSFlorian Fainelli * to let the MAC decide what to do.
794db88816bSFlorian Fainelli */
795db88816bSFlorian Fainelli ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
796db88816bSFlorian Fainelli if (ret)
797db88816bSFlorian Fainelli return ret;
798db88816bSFlorian Fainelli
799db88816bSFlorian Fainelli return genphy_restart_aneg(phydev);
800db88816bSFlorian Fainelli }
801db88816bSFlorian Fainelli
bcm7xxx_28nm_get_phy_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)802b23ce9e8SFlorian Fainelli static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
803b23ce9e8SFlorian Fainelli struct ethtool_stats *stats, u64 *data)
804b23ce9e8SFlorian Fainelli {
805b23ce9e8SFlorian Fainelli struct bcm7xxx_phy_priv *priv = phydev->priv;
806b23ce9e8SFlorian Fainelli
807b23ce9e8SFlorian Fainelli bcm_phy_get_stats(phydev, priv->stats, stats, data);
808b23ce9e8SFlorian Fainelli }
809b23ce9e8SFlorian Fainelli
bcm7xxx_28nm_probe(struct phy_device * phydev)810b23ce9e8SFlorian Fainelli static int bcm7xxx_28nm_probe(struct phy_device *phydev)
811b23ce9e8SFlorian Fainelli {
812b23ce9e8SFlorian Fainelli struct bcm7xxx_phy_priv *priv;
8134228c3a2SHeiner Kallweit struct clk *clk;
814ba4ee3c0SFlorian Fainelli int ret = 0;
815b23ce9e8SFlorian Fainelli
816b23ce9e8SFlorian Fainelli priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
817b23ce9e8SFlorian Fainelli if (!priv)
818b23ce9e8SFlorian Fainelli return -ENOMEM;
819b23ce9e8SFlorian Fainelli
820b23ce9e8SFlorian Fainelli phydev->priv = priv;
821b23ce9e8SFlorian Fainelli
822b23ce9e8SFlorian Fainelli priv->stats = devm_kcalloc(&phydev->mdio.dev,
823b23ce9e8SFlorian Fainelli bcm_phy_get_sset_count(phydev), sizeof(u64),
824b23ce9e8SFlorian Fainelli GFP_KERNEL);
825b23ce9e8SFlorian Fainelli if (!priv->stats)
826b23ce9e8SFlorian Fainelli return -ENOMEM;
827b23ce9e8SFlorian Fainelli
8284228c3a2SHeiner Kallweit clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
8294228c3a2SHeiner Kallweit if (IS_ERR(clk))
8304228c3a2SHeiner Kallweit return PTR_ERR(clk);
831ba4ee3c0SFlorian Fainelli
832ba4ee3c0SFlorian Fainelli /* Dummy read to a register to workaround an issue upon reset where the
833ba4ee3c0SFlorian Fainelli * internal inverter may not allow the first MDIO transaction to pass
834ba4ee3c0SFlorian Fainelli * the MDIO management controller and make us return 0xffff for such
835ba4ee3c0SFlorian Fainelli * reads. This is needed to ensure that any subsequent reads to the
836ba4ee3c0SFlorian Fainelli * PHY will succeed.
837ba4ee3c0SFlorian Fainelli */
838ba4ee3c0SFlorian Fainelli phy_read(phydev, MII_BMSR);
839ba4ee3c0SFlorian Fainelli
840ba4ee3c0SFlorian Fainelli return ret;
841ba4ee3c0SFlorian Fainelli }
842ba4ee3c0SFlorian Fainelli
843153df3c7SFlorian Fainelli #define BCM7XXX_28NM_GPHY(_oui, _name) \
844153df3c7SFlorian Fainelli { \
845153df3c7SFlorian Fainelli .phy_id = (_oui), \
846153df3c7SFlorian Fainelli .phy_id_mask = 0xfffffff0, \
847153df3c7SFlorian Fainelli .name = _name, \
848dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ \
849153df3c7SFlorian Fainelli .flags = PHY_IS_INTERNAL, \
8502a9df742SFlorian Fainelli .config_init = bcm7xxx_28nm_config_init, \
851153df3c7SFlorian Fainelli .resume = bcm7xxx_28nm_resume, \
852db88816bSFlorian Fainelli .get_tunable = bcm7xxx_28nm_get_tunable, \
853db88816bSFlorian Fainelli .set_tunable = bcm7xxx_28nm_set_tunable, \
854b23ce9e8SFlorian Fainelli .get_sset_count = bcm_phy_get_sset_count, \
855b23ce9e8SFlorian Fainelli .get_strings = bcm_phy_get_strings, \
856b23ce9e8SFlorian Fainelli .get_stats = bcm7xxx_28nm_get_phy_stats, \
857b23ce9e8SFlorian Fainelli .probe = bcm7xxx_28nm_probe, \
858153df3c7SFlorian Fainelli }
859153df3c7SFlorian Fainelli
86083ee102aSDoug Berger #define BCM7XXX_28NM_EPHY(_oui, _name) \
86183ee102aSDoug Berger { \
86283ee102aSDoug Berger .phy_id = (_oui), \
86383ee102aSDoug Berger .phy_id_mask = 0xfffffff0, \
86483ee102aSDoug Berger .name = _name, \
865dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ \
86683ee102aSDoug Berger .flags = PHY_IS_INTERNAL, \
86783ee102aSDoug Berger .config_init = bcm7xxx_28nm_ephy_config_init, \
86883ee102aSDoug Berger .resume = bcm7xxx_28nm_ephy_resume, \
86983ee102aSDoug Berger .get_sset_count = bcm_phy_get_sset_count, \
87083ee102aSDoug Berger .get_strings = bcm_phy_get_strings, \
87183ee102aSDoug Berger .get_stats = bcm7xxx_28nm_get_phy_stats, \
87283ee102aSDoug Berger .probe = bcm7xxx_28nm_probe, \
873d88fd1b5SFlorian Fainelli .read_mmd = bcm7xxx_28nm_ephy_read_mmd, \
874d88fd1b5SFlorian Fainelli .write_mmd = bcm7xxx_28nm_ephy_write_mmd, \
87583ee102aSDoug Berger }
87683ee102aSDoug Berger
8773125c081SFlorian Fainelli #define BCM7XXX_40NM_EPHY(_oui, _name) \
8783125c081SFlorian Fainelli { \
8793125c081SFlorian Fainelli .phy_id = (_oui), \
8803125c081SFlorian Fainelli .phy_id_mask = 0xfffffff0, \
8813125c081SFlorian Fainelli .name = _name, \
882dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ \
8833125c081SFlorian Fainelli .flags = PHY_IS_INTERNAL, \
884fe586b82SDoug Berger .soft_reset = genphy_soft_reset, \
8853125c081SFlorian Fainelli .config_init = bcm7xxx_config_init, \
8863125c081SFlorian Fainelli .suspend = bcm7xxx_suspend, \
8873125c081SFlorian Fainelli .resume = bcm7xxx_config_init, \
8883125c081SFlorian Fainelli }
8893125c081SFlorian Fainelli
890f68d08c4SFlorian Fainelli #define BCM7XXX_16NM_EPHY(_oui, _name) \
891f68d08c4SFlorian Fainelli { \
892f68d08c4SFlorian Fainelli .phy_id = (_oui), \
893f68d08c4SFlorian Fainelli .phy_id_mask = 0xfffffff0, \
894f68d08c4SFlorian Fainelli .name = _name, \
895f68d08c4SFlorian Fainelli /* PHY_BASIC_FEATURES */ \
896f68d08c4SFlorian Fainelli .flags = PHY_IS_INTERNAL, \
897*6200e00eSFlorian Fainelli .get_sset_count = bcm_phy_get_sset_count, \
898*6200e00eSFlorian Fainelli .get_strings = bcm_phy_get_strings, \
899*6200e00eSFlorian Fainelli .get_stats = bcm7xxx_28nm_get_phy_stats, \
900f68d08c4SFlorian Fainelli .probe = bcm7xxx_28nm_probe, \
901f68d08c4SFlorian Fainelli .config_init = bcm7xxx_16nm_ephy_config_init, \
902f68d08c4SFlorian Fainelli .config_aneg = genphy_config_aneg, \
903f68d08c4SFlorian Fainelli .read_status = genphy_read_status, \
904f68d08c4SFlorian Fainelli .resume = bcm7xxx_16nm_ephy_resume, \
905f68d08c4SFlorian Fainelli }
906f68d08c4SFlorian Fainelli
907b560a58cSFlorian Fainelli static struct phy_driver bcm7xxx_driver[] = {
90892ec804fSFlorian Fainelli BCM7XXX_28NM_EPHY(PHY_ID_BCM72113, "Broadcom BCM72113"),
9098b86850bSFlorian Fainelli BCM7XXX_28NM_EPHY(PHY_ID_BCM72116, "Broadcom BCM72116"),
910f68d08c4SFlorian Fainelli BCM7XXX_16NM_EPHY(PHY_ID_BCM72165, "Broadcom BCM72165"),
911430ad68fSFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
9128572a1b4SJustin Chen BCM7XXX_28NM_EPHY(PHY_ID_BCM7255, "Broadcom BCM7255"),
91383ee102aSDoug Berger BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
91483ee102aSDoug Berger BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
91583ee102aSDoug Berger BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
916582d0ac3SFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
917430ad68fSFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
918153df3c7SFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
9199fa0bba0SFlorian Fainelli BCM7XXX_16NM_EPHY(PHY_ID_BCM74165, "Broadcom BCM74165"),
920b08d46b0SFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
921153df3c7SFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
92259e33c2bSFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
923153df3c7SFlorian Fainelli BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
9244cef191dSJaedon Shin BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
9254cef191dSJaedon Shin BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
9263125c081SFlorian Fainelli BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
9273125c081SFlorian Fainelli BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
9283125c081SFlorian Fainelli BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
929218f23e8SFlorian Fainelli BCM7XXX_16NM_EPHY(PHY_ID_BCM7712, "Broadcom BCM7712"),
930b6333531SDavid S. Miller };
931b560a58cSFlorian Fainelli
932b560a58cSFlorian Fainelli static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
93392ec804fSFlorian Fainelli { PHY_ID_BCM72113, 0xfffffff0 },
9348b86850bSFlorian Fainelli { PHY_ID_BCM72116, 0xfffffff0, },
935f68d08c4SFlorian Fainelli { PHY_ID_BCM72165, 0xfffffff0, },
936430ad68fSFlorian Fainelli { PHY_ID_BCM7250, 0xfffffff0, },
9378572a1b4SJustin Chen { PHY_ID_BCM7255, 0xfffffff0, },
93883ee102aSDoug Berger { PHY_ID_BCM7260, 0xfffffff0, },
93983ee102aSDoug Berger { PHY_ID_BCM7268, 0xfffffff0, },
94083ee102aSDoug Berger { PHY_ID_BCM7271, 0xfffffff0, },
941582d0ac3SFlorian Fainelli { PHY_ID_BCM7278, 0xfffffff0, },
942430ad68fSFlorian Fainelli { PHY_ID_BCM7364, 0xfffffff0, },
943b560a58cSFlorian Fainelli { PHY_ID_BCM7366, 0xfffffff0, },
9444cef191dSJaedon Shin { PHY_ID_BCM7346, 0xfffffff0, },
9454cef191dSJaedon Shin { PHY_ID_BCM7362, 0xfffffff0, },
946d068b02cSPetri Gynther { PHY_ID_BCM7425, 0xfffffff0, },
947d068b02cSPetri Gynther { PHY_ID_BCM7429, 0xfffffff0, },
948b08d46b0SFlorian Fainelli { PHY_ID_BCM74371, 0xfffffff0, },
949b560a58cSFlorian Fainelli { PHY_ID_BCM7439, 0xfffffff0, },
9509458ceabSFlorian Fainelli { PHY_ID_BCM7435, 0xfffffff0, },
951b560a58cSFlorian Fainelli { PHY_ID_BCM7445, 0xfffffff0, },
952218f23e8SFlorian Fainelli { PHY_ID_BCM7712, 0xfffffff0, },
953b560a58cSFlorian Fainelli { }
954b560a58cSFlorian Fainelli };
955b560a58cSFlorian Fainelli
95650fd7150SJohan Hovold module_phy_driver(bcm7xxx_driver);
957b560a58cSFlorian Fainelli
958b560a58cSFlorian Fainelli MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
959b560a58cSFlorian Fainelli
960b560a58cSFlorian Fainelli MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
961b560a58cSFlorian Fainelli MODULE_LICENSE("GPL");
962b560a58cSFlorian Fainelli MODULE_AUTHOR("Broadcom Corporation");
963