1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
29082eeacSAndy Fleming /*
39082eeacSAndy Fleming * Marvell PHY drivers
49082eeacSAndy Fleming *
59082eeacSAndy Fleming * Copyright 2010-2011 Freescale Semiconductor, Inc.
69082eeacSAndy Fleming * author Andy Fleming
79082eeacSAndy Fleming */
89082eeacSAndy Fleming #include <common.h>
9fbfa1abaSSimon Glass #include <errno.h>
109082eeacSAndy Fleming #include <phy.h>
119082eeacSAndy Fleming
129082eeacSAndy Fleming #define PHY_AUTONEGOTIATE_TIMEOUT 5000
139082eeacSAndy Fleming
1468e6ecadSPhil Edworthy #define MII_MARVELL_PHY_PAGE 22
1568e6ecadSPhil Edworthy
169082eeacSAndy Fleming /* 88E1011 PHY Status Register */
179082eeacSAndy Fleming #define MIIM_88E1xxx_PHY_STATUS 0x11
189082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
199082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
209082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_100 0x4000
219082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
229082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
239082eeacSAndy Fleming #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
249082eeacSAndy Fleming
259082eeacSAndy Fleming #define MIIM_88E1xxx_PHY_SCR 0x10
269082eeacSAndy Fleming #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
279082eeacSAndy Fleming
289082eeacSAndy Fleming /* 88E1111 PHY LED Control Register */
299082eeacSAndy Fleming #define MIIM_88E1111_PHY_LED_CONTROL 24
309082eeacSAndy Fleming #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
319082eeacSAndy Fleming #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
329082eeacSAndy Fleming
33fa12a08eSZang Roy-R61911 /* 88E1111 Extended PHY Specific Control Register */
34fa12a08eSZang Roy-R61911 #define MIIM_88E1111_PHY_EXT_CR 0x14
35fa12a08eSZang Roy-R61911 #define MIIM_88E1111_RX_DELAY 0x80
36fa12a08eSZang Roy-R61911 #define MIIM_88E1111_TX_DELAY 0x2
37fa12a08eSZang Roy-R61911
38fa12a08eSZang Roy-R61911 /* 88E1111 Extended PHY Specific Status Register */
39fa12a08eSZang Roy-R61911 #define MIIM_88E1111_PHY_EXT_SR 0x1b
40fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
41fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
42fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
43fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
44fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
45fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
46fa12a08eSZang Roy-R61911 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
47fa12a08eSZang Roy-R61911
48fa12a08eSZang Roy-R61911 #define MIIM_88E1111_COPPER 0
49fa12a08eSZang Roy-R61911 #define MIIM_88E1111_FIBER 1
50fa12a08eSZang Roy-R61911
519082eeacSAndy Fleming /* 88E1118 PHY defines */
529082eeacSAndy Fleming #define MIIM_88E1118_PHY_PAGE 22
539082eeacSAndy Fleming #define MIIM_88E1118_PHY_LED_PAGE 3
549082eeacSAndy Fleming
559082eeacSAndy Fleming /* 88E1121 PHY LED Control Register */
569082eeacSAndy Fleming #define MIIM_88E1121_PHY_LED_CTRL 16
579082eeacSAndy Fleming #define MIIM_88E1121_PHY_LED_PAGE 3
589082eeacSAndy Fleming #define MIIM_88E1121_PHY_LED_DEF 0x0030
599082eeacSAndy Fleming
609082eeacSAndy Fleming /* 88E1121 PHY IRQ Enable/Status Register */
619082eeacSAndy Fleming #define MIIM_88E1121_PHY_IRQ_EN 18
629082eeacSAndy Fleming #define MIIM_88E1121_PHY_IRQ_STATUS 19
639082eeacSAndy Fleming
649082eeacSAndy Fleming #define MIIM_88E1121_PHY_PAGE 22
659082eeacSAndy Fleming
669082eeacSAndy Fleming /* 88E1145 Extended PHY Specific Control Register */
679082eeacSAndy Fleming #define MIIM_88E1145_PHY_EXT_CR 20
689082eeacSAndy Fleming #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
699082eeacSAndy Fleming #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
709082eeacSAndy Fleming
719082eeacSAndy Fleming #define MIIM_88E1145_PHY_LED_CONTROL 24
729082eeacSAndy Fleming #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
739082eeacSAndy Fleming
749082eeacSAndy Fleming #define MIIM_88E1145_PHY_PAGE 29
759082eeacSAndy Fleming #define MIIM_88E1145_PHY_CAL_OV 30
769082eeacSAndy Fleming
779082eeacSAndy Fleming #define MIIM_88E1149_PHY_PAGE 29
789082eeacSAndy Fleming
79aeceec0dSSebastian Hesselbarth /* 88E1310 PHY defines */
80aeceec0dSSebastian Hesselbarth #define MIIM_88E1310_PHY_LED_CTRL 16
81aeceec0dSSebastian Hesselbarth #define MIIM_88E1310_PHY_IRQ_EN 18
82aeceec0dSSebastian Hesselbarth #define MIIM_88E1310_PHY_RGMII_CTRL 21
83aeceec0dSSebastian Hesselbarth #define MIIM_88E1310_PHY_PAGE 22
84aeceec0dSSebastian Hesselbarth
8593cc2959SJoe Hershberger /* 88E151x PHY defines */
8668e6ecadSPhil Edworthy /* Page 2 registers */
8768e6ecadSPhil Edworthy #define MIIM_88E151x_PHY_MSCR 21
8868e6ecadSPhil Edworthy #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
8968e6ecadSPhil Edworthy #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
9068e6ecadSPhil Edworthy #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
9193cc2959SJoe Hershberger /* Page 3 registers */
9293cc2959SJoe Hershberger #define MIIM_88E151x_LED_FUNC_CTRL 16
9393cc2959SJoe Hershberger #define MIIM_88E151x_LED_FLD_SZ 4
9493cc2959SJoe Hershberger #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
9593cc2959SJoe Hershberger #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
9693cc2959SJoe Hershberger #define MIIM_88E151x_LED0_ACT 3
9793cc2959SJoe Hershberger #define MIIM_88E151x_LED1_100_1000_LINK 6
9893cc2959SJoe Hershberger #define MIIM_88E151x_LED_TIMER_CTRL 18
9993cc2959SJoe Hershberger #define MIIM_88E151x_INT_EN_OFFS 7
10093cc2959SJoe Hershberger /* Page 18 registers */
10193cc2959SJoe Hershberger #define MIIM_88E151x_GENERAL_CTRL 20
10293cc2959SJoe Hershberger #define MIIM_88E151x_MODE_SGMII 1
10393cc2959SJoe Hershberger #define MIIM_88E151x_RESET_OFFS 15
10493cc2959SJoe Hershberger
m88e1xxx_phy_extread(struct phy_device * phydev,int addr,int devaddr,int regnum)105ce27eb9bSLukasz Majewski static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
106ce27eb9bSLukasz Majewski int devaddr, int regnum)
107ce27eb9bSLukasz Majewski {
108ce27eb9bSLukasz Majewski int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
109ce27eb9bSLukasz Majewski int val;
110ce27eb9bSLukasz Majewski
111ce27eb9bSLukasz Majewski phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
112ce27eb9bSLukasz Majewski val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
113ce27eb9bSLukasz Majewski phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
114ce27eb9bSLukasz Majewski
115ce27eb9bSLukasz Majewski return val;
116ce27eb9bSLukasz Majewski }
117ce27eb9bSLukasz Majewski
m88e1xxx_phy_extwrite(struct phy_device * phydev,int addr,int devaddr,int regnum,u16 val)118ce27eb9bSLukasz Majewski static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
119ce27eb9bSLukasz Majewski int devaddr, int regnum, u16 val)
120ce27eb9bSLukasz Majewski {
121ce27eb9bSLukasz Majewski int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
122ce27eb9bSLukasz Majewski
123ce27eb9bSLukasz Majewski phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
124ce27eb9bSLukasz Majewski phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
125ce27eb9bSLukasz Majewski phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
126ce27eb9bSLukasz Majewski
127ce27eb9bSLukasz Majewski return 0;
128ce27eb9bSLukasz Majewski }
129ce27eb9bSLukasz Majewski
1309082eeacSAndy Fleming /* Marvell 88E1011S */
m88e1011s_config(struct phy_device * phydev)1319082eeacSAndy Fleming static int m88e1011s_config(struct phy_device *phydev)
1329082eeacSAndy Fleming {
1339082eeacSAndy Fleming /* Reset and configure the PHY */
1349082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
1359082eeacSAndy Fleming
1369082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
1379082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
1389082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
1399082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
1409082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
1419082eeacSAndy Fleming
1429082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
1439082eeacSAndy Fleming
1449082eeacSAndy Fleming genphy_config_aneg(phydev);
1459082eeacSAndy Fleming
1469082eeacSAndy Fleming return 0;
1479082eeacSAndy Fleming }
1489082eeacSAndy Fleming
1499082eeacSAndy Fleming /* Parse the 88E1011's status register for speed and duplex
1509082eeacSAndy Fleming * information
1519082eeacSAndy Fleming */
m88e1xxx_parse_status(struct phy_device * phydev)152ef5e821bSMichal Simek static int m88e1xxx_parse_status(struct phy_device *phydev)
1539082eeacSAndy Fleming {
1549082eeacSAndy Fleming unsigned int speed;
1559082eeacSAndy Fleming unsigned int mii_reg;
1569082eeacSAndy Fleming
1579082eeacSAndy Fleming mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
1589082eeacSAndy Fleming
1599082eeacSAndy Fleming if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
1609082eeacSAndy Fleming !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
1619082eeacSAndy Fleming int i = 0;
1629082eeacSAndy Fleming
1639082eeacSAndy Fleming puts("Waiting for PHY realtime link");
1649082eeacSAndy Fleming while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
1659082eeacSAndy Fleming /* Timeout reached ? */
1669082eeacSAndy Fleming if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1679082eeacSAndy Fleming puts(" TIMEOUT !\n");
1689082eeacSAndy Fleming phydev->link = 0;
169ef5e821bSMichal Simek return -ETIMEDOUT;
1709082eeacSAndy Fleming }
1719082eeacSAndy Fleming
1729082eeacSAndy Fleming if ((i++ % 1000) == 0)
1739082eeacSAndy Fleming putc('.');
1749082eeacSAndy Fleming udelay(1000);
1759082eeacSAndy Fleming mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
1769082eeacSAndy Fleming MIIM_88E1xxx_PHY_STATUS);
1779082eeacSAndy Fleming }
1789082eeacSAndy Fleming puts(" done\n");
17976f11d3aSMario Six mdelay(500); /* another 500 ms (results in faster booting) */
1809082eeacSAndy Fleming } else {
1819082eeacSAndy Fleming if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
1829082eeacSAndy Fleming phydev->link = 1;
1839082eeacSAndy Fleming else
1849082eeacSAndy Fleming phydev->link = 0;
1859082eeacSAndy Fleming }
1869082eeacSAndy Fleming
1879082eeacSAndy Fleming if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
1889082eeacSAndy Fleming phydev->duplex = DUPLEX_FULL;
1899082eeacSAndy Fleming else
1909082eeacSAndy Fleming phydev->duplex = DUPLEX_HALF;
1919082eeacSAndy Fleming
1929082eeacSAndy Fleming speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
1939082eeacSAndy Fleming
1949082eeacSAndy Fleming switch (speed) {
1959082eeacSAndy Fleming case MIIM_88E1xxx_PHYSTAT_GBIT:
1969082eeacSAndy Fleming phydev->speed = SPEED_1000;
1979082eeacSAndy Fleming break;
1989082eeacSAndy Fleming case MIIM_88E1xxx_PHYSTAT_100:
1999082eeacSAndy Fleming phydev->speed = SPEED_100;
2009082eeacSAndy Fleming break;
2019082eeacSAndy Fleming default:
2029082eeacSAndy Fleming phydev->speed = SPEED_10;
2039082eeacSAndy Fleming break;
2049082eeacSAndy Fleming }
2059082eeacSAndy Fleming
2069082eeacSAndy Fleming return 0;
2079082eeacSAndy Fleming }
2089082eeacSAndy Fleming
m88e1011s_startup(struct phy_device * phydev)2099082eeacSAndy Fleming static int m88e1011s_startup(struct phy_device *phydev)
2109082eeacSAndy Fleming {
211b733c278SMichal Simek int ret;
2129082eeacSAndy Fleming
213b733c278SMichal Simek ret = genphy_update_link(phydev);
214b733c278SMichal Simek if (ret)
215b733c278SMichal Simek return ret;
216b733c278SMichal Simek
217b733c278SMichal Simek return m88e1xxx_parse_status(phydev);
2189082eeacSAndy Fleming }
2199082eeacSAndy Fleming
2209082eeacSAndy Fleming /* Marvell 88E1111S */
m88e1111s_config(struct phy_device * phydev)2219082eeacSAndy Fleming static int m88e1111s_config(struct phy_device *phydev)
2229082eeacSAndy Fleming {
2239082eeacSAndy Fleming int reg;
2249082eeacSAndy Fleming
22524d98cb4SPhil Edworthy if (phy_interface_is_rgmii(phydev)) {
226fa12a08eSZang Roy-R61911 reg = phy_read(phydev,
227fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
228fa12a08eSZang Roy-R61911 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
229fa12a08eSZang Roy-R61911 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
230fa12a08eSZang Roy-R61911 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
231fa12a08eSZang Roy-R61911 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
232fa12a08eSZang Roy-R61911 reg &= ~MIIM_88E1111_TX_DELAY;
233fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_RX_DELAY;
234fa12a08eSZang Roy-R61911 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
235fa12a08eSZang Roy-R61911 reg &= ~MIIM_88E1111_RX_DELAY;
236fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_TX_DELAY;
2379082eeacSAndy Fleming }
2389082eeacSAndy Fleming
239fa12a08eSZang Roy-R61911 phy_write(phydev,
240fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
241fa12a08eSZang Roy-R61911
242fa12a08eSZang Roy-R61911 reg = phy_read(phydev,
243fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
244fa12a08eSZang Roy-R61911
245fa12a08eSZang Roy-R61911 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
246fa12a08eSZang Roy-R61911
247fa12a08eSZang Roy-R61911 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
248fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
249fa12a08eSZang Roy-R61911 else
250fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
251fa12a08eSZang Roy-R61911
252fa12a08eSZang Roy-R61911 phy_write(phydev,
253fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
254fa12a08eSZang Roy-R61911 }
255fa12a08eSZang Roy-R61911
256fa12a08eSZang Roy-R61911 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
257fa12a08eSZang Roy-R61911 reg = phy_read(phydev,
258fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
259fa12a08eSZang Roy-R61911
260fa12a08eSZang Roy-R61911 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
261fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
262fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
263fa12a08eSZang Roy-R61911
264fa12a08eSZang Roy-R61911 phy_write(phydev, MDIO_DEVAD_NONE,
265fa12a08eSZang Roy-R61911 MIIM_88E1111_PHY_EXT_SR, reg);
266fa12a08eSZang Roy-R61911 }
267fa12a08eSZang Roy-R61911
268fa12a08eSZang Roy-R61911 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
269fa12a08eSZang Roy-R61911 reg = phy_read(phydev,
270fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
271fa12a08eSZang Roy-R61911 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
272fa12a08eSZang Roy-R61911 phy_write(phydev,
273fa12a08eSZang Roy-R61911 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
274fa12a08eSZang Roy-R61911
275fa12a08eSZang Roy-R61911 reg = phy_read(phydev, MDIO_DEVAD_NONE,
276fa12a08eSZang Roy-R61911 MIIM_88E1111_PHY_EXT_SR);
277fa12a08eSZang Roy-R61911 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
278fa12a08eSZang Roy-R61911 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
279fa12a08eSZang Roy-R61911 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
280fa12a08eSZang Roy-R61911 phy_write(phydev, MDIO_DEVAD_NONE,
281fa12a08eSZang Roy-R61911 MIIM_88E1111_PHY_EXT_SR, reg);
282fa12a08eSZang Roy-R61911
283fa12a08eSZang Roy-R61911 /* soft reset */
2843089c47dSStefan Roese phy_reset(phydev);
285fa12a08eSZang Roy-R61911
286fa12a08eSZang Roy-R61911 reg = phy_read(phydev, MDIO_DEVAD_NONE,
287fa12a08eSZang Roy-R61911 MIIM_88E1111_PHY_EXT_SR);
288fa12a08eSZang Roy-R61911 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
289fa12a08eSZang Roy-R61911 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
290fa12a08eSZang Roy-R61911 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
291fa12a08eSZang Roy-R61911 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
292fa12a08eSZang Roy-R61911 phy_write(phydev, MDIO_DEVAD_NONE,
293fa12a08eSZang Roy-R61911 MIIM_88E1111_PHY_EXT_SR, reg);
294fa12a08eSZang Roy-R61911 }
295fa12a08eSZang Roy-R61911
296fa12a08eSZang Roy-R61911 /* soft reset */
2973089c47dSStefan Roese phy_reset(phydev);
2989082eeacSAndy Fleming
2999082eeacSAndy Fleming genphy_config_aneg(phydev);
300a8c3eca4SStefan Roese genphy_restart_aneg(phydev);
3019082eeacSAndy Fleming
3029082eeacSAndy Fleming return 0;
3039082eeacSAndy Fleming }
3049082eeacSAndy Fleming
30535fa0ddaSHao Zhang /**
30635fa0ddaSHao Zhang * m88e1518_phy_writebits - write bits to a register
30735fa0ddaSHao Zhang */
m88e1518_phy_writebits(struct phy_device * phydev,u8 reg_num,u16 offset,u16 len,u16 data)30835fa0ddaSHao Zhang void m88e1518_phy_writebits(struct phy_device *phydev,
30935fa0ddaSHao Zhang u8 reg_num, u16 offset, u16 len, u16 data)
31035fa0ddaSHao Zhang {
31135fa0ddaSHao Zhang u16 reg, mask;
31235fa0ddaSHao Zhang
31335fa0ddaSHao Zhang if ((len + offset) >= 16)
31435fa0ddaSHao Zhang mask = 0 - (1 << offset);
31535fa0ddaSHao Zhang else
31635fa0ddaSHao Zhang mask = (1 << (len + offset)) - (1 << offset);
31735fa0ddaSHao Zhang
31835fa0ddaSHao Zhang reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
31935fa0ddaSHao Zhang
32035fa0ddaSHao Zhang reg &= ~mask;
32135fa0ddaSHao Zhang reg |= data << offset;
32235fa0ddaSHao Zhang
32335fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
32435fa0ddaSHao Zhang }
32535fa0ddaSHao Zhang
m88e1518_config(struct phy_device * phydev)32635fa0ddaSHao Zhang static int m88e1518_config(struct phy_device *phydev)
32735fa0ddaSHao Zhang {
32868e6ecadSPhil Edworthy u16 reg;
32968e6ecadSPhil Edworthy
33035fa0ddaSHao Zhang /*
33135fa0ddaSHao Zhang * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
33235fa0ddaSHao Zhang * /88E1514 Rev A0, Errata Section 3.1
33335fa0ddaSHao Zhang */
33490a94ef6SClemens Gruber
33590a94ef6SClemens Gruber /* EEE initialization */
33693cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
33735fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
33835fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
33935fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
34035fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
34135fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
34235fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
34335fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
34435fa0ddaSHao Zhang phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
34593cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
34690a94ef6SClemens Gruber
34790a94ef6SClemens Gruber /* SGMII-to-Copper mode initialization */
34890a94ef6SClemens Gruber if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
34990a94ef6SClemens Gruber /* Select page 18 */
35093cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
35190a94ef6SClemens Gruber
35290a94ef6SClemens Gruber /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
35393cc2959SJoe Hershberger m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
35493cc2959SJoe Hershberger 0, 3, MIIM_88E151x_MODE_SGMII);
35535fa0ddaSHao Zhang
35690a94ef6SClemens Gruber /* PHY reset is necessary after changing MODE[2:0] */
35793cc2959SJoe Hershberger m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
35893cc2959SJoe Hershberger MIIM_88E151x_RESET_OFFS, 1, 1);
35990a94ef6SClemens Gruber
36090a94ef6SClemens Gruber /* Reset page selection */
36193cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
36290a94ef6SClemens Gruber
36335fa0ddaSHao Zhang udelay(100);
36435fa0ddaSHao Zhang }
36535fa0ddaSHao Zhang
36668e6ecadSPhil Edworthy if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
36768e6ecadSPhil Edworthy reg = phy_read(phydev, MDIO_DEVAD_NONE,
36868e6ecadSPhil Edworthy MIIM_88E1111_PHY_EXT_SR);
36968e6ecadSPhil Edworthy
37068e6ecadSPhil Edworthy reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
37168e6ecadSPhil Edworthy reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
37268e6ecadSPhil Edworthy reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
37368e6ecadSPhil Edworthy
37468e6ecadSPhil Edworthy phy_write(phydev, MDIO_DEVAD_NONE,
37568e6ecadSPhil Edworthy MIIM_88E1111_PHY_EXT_SR, reg);
37668e6ecadSPhil Edworthy }
37768e6ecadSPhil Edworthy
37868e6ecadSPhil Edworthy if (phy_interface_is_rgmii(phydev)) {
37968e6ecadSPhil Edworthy phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
38068e6ecadSPhil Edworthy
38168e6ecadSPhil Edworthy reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
38268e6ecadSPhil Edworthy reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
383431be621SMario Six if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
384431be621SMario Six phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
38568e6ecadSPhil Edworthy reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
38668e6ecadSPhil Edworthy else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
38768e6ecadSPhil Edworthy reg |= MIIM_88E151x_RGMII_RX_DELAY;
38868e6ecadSPhil Edworthy else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
38968e6ecadSPhil Edworthy reg |= MIIM_88E151x_RGMII_TX_DELAY;
39068e6ecadSPhil Edworthy phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
39168e6ecadSPhil Edworthy
39268e6ecadSPhil Edworthy phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
39368e6ecadSPhil Edworthy }
39468e6ecadSPhil Edworthy
39568e6ecadSPhil Edworthy /* soft reset */
39668e6ecadSPhil Edworthy phy_reset(phydev);
39768e6ecadSPhil Edworthy
39868e6ecadSPhil Edworthy genphy_config_aneg(phydev);
39968e6ecadSPhil Edworthy genphy_restart_aneg(phydev);
40068e6ecadSPhil Edworthy
40168e6ecadSPhil Edworthy return 0;
40235fa0ddaSHao Zhang }
40335fa0ddaSHao Zhang
4048396d0abSClemens Gruber /* Marvell 88E1510 */
m88e1510_config(struct phy_device * phydev)4058396d0abSClemens Gruber static int m88e1510_config(struct phy_device *phydev)
4068396d0abSClemens Gruber {
4078396d0abSClemens Gruber /* Select page 3 */
40893cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
40993cc2959SJoe Hershberger MIIM_88E1118_PHY_LED_PAGE);
4108396d0abSClemens Gruber
4118396d0abSClemens Gruber /* Enable INTn output on LED[2] */
41293cc2959SJoe Hershberger m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
41393cc2959SJoe Hershberger MIIM_88E151x_INT_EN_OFFS, 1, 1);
4148396d0abSClemens Gruber
4158396d0abSClemens Gruber /* Configure LEDs */
41693cc2959SJoe Hershberger /* LED[0]:0011 (ACT) */
41793cc2959SJoe Hershberger m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
41893cc2959SJoe Hershberger MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
41993cc2959SJoe Hershberger MIIM_88E151x_LED0_ACT);
42093cc2959SJoe Hershberger /* LED[1]:0110 (LINK 100/1000 Mbps) */
42193cc2959SJoe Hershberger m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
42293cc2959SJoe Hershberger MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
42393cc2959SJoe Hershberger MIIM_88E151x_LED1_100_1000_LINK);
4248396d0abSClemens Gruber
4258396d0abSClemens Gruber /* Reset page selection */
42693cc2959SJoe Hershberger phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
4278396d0abSClemens Gruber
4288396d0abSClemens Gruber return m88e1518_config(phydev);
4298396d0abSClemens Gruber }
4308396d0abSClemens Gruber
4319082eeacSAndy Fleming /* Marvell 88E1118 */
m88e1118_config(struct phy_device * phydev)4329082eeacSAndy Fleming static int m88e1118_config(struct phy_device *phydev)
4339082eeacSAndy Fleming {
4349082eeacSAndy Fleming /* Change Page Number */
4359082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
4369082eeacSAndy Fleming /* Delay RGMII TX and RX */
4379082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
4389082eeacSAndy Fleming /* Change Page Number */
4399082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
4409082eeacSAndy Fleming /* Adjust LED control */
4419082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
4429082eeacSAndy Fleming /* Change Page Number */
4439082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
4449082eeacSAndy Fleming
4451b008fdbSMichal Simek return genphy_config_aneg(phydev);
4469082eeacSAndy Fleming }
4479082eeacSAndy Fleming
m88e1118_startup(struct phy_device * phydev)4489082eeacSAndy Fleming static int m88e1118_startup(struct phy_device *phydev)
4499082eeacSAndy Fleming {
450b733c278SMichal Simek int ret;
451b733c278SMichal Simek
4529082eeacSAndy Fleming /* Change Page Number */
4539082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
4549082eeacSAndy Fleming
455b733c278SMichal Simek ret = genphy_update_link(phydev);
456b733c278SMichal Simek if (ret)
457b733c278SMichal Simek return ret;
4589082eeacSAndy Fleming
459b733c278SMichal Simek return m88e1xxx_parse_status(phydev);
4609082eeacSAndy Fleming }
4619082eeacSAndy Fleming
4629082eeacSAndy Fleming /* Marvell 88E1121R */
m88e1121_config(struct phy_device * phydev)4639082eeacSAndy Fleming static int m88e1121_config(struct phy_device *phydev)
4649082eeacSAndy Fleming {
4659082eeacSAndy Fleming int pg;
4669082eeacSAndy Fleming
4679082eeacSAndy Fleming /* Configure the PHY */
4689082eeacSAndy Fleming genphy_config_aneg(phydev);
4699082eeacSAndy Fleming
4709082eeacSAndy Fleming /* Switch the page to access the led register */
4719082eeacSAndy Fleming pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
4729082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
4739082eeacSAndy Fleming MIIM_88E1121_PHY_LED_PAGE);
4749082eeacSAndy Fleming /* Configure leds */
4759082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
4769082eeacSAndy Fleming MIIM_88E1121_PHY_LED_DEF);
4779082eeacSAndy Fleming /* Restore the page pointer */
4789082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
4799082eeacSAndy Fleming
4809082eeacSAndy Fleming /* Disable IRQs and de-assert interrupt */
4819082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
4829082eeacSAndy Fleming phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
4839082eeacSAndy Fleming
4849082eeacSAndy Fleming return 0;
4859082eeacSAndy Fleming }
4869082eeacSAndy Fleming
4879082eeacSAndy Fleming /* Marvell 88E1145 */
m88e1145_config(struct phy_device * phydev)4889082eeacSAndy Fleming static int m88e1145_config(struct phy_device *phydev)
4899082eeacSAndy Fleming {
4909082eeacSAndy Fleming int reg;
4919082eeacSAndy Fleming
4929082eeacSAndy Fleming /* Errata E0, E1 */
4939082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
4949082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
4959082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
4969082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
4979082eeacSAndy Fleming
4989082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
4999082eeacSAndy Fleming MIIM_88E1xxx_PHY_MDI_X_AUTO);
5009082eeacSAndy Fleming
5019082eeacSAndy Fleming reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
5029082eeacSAndy Fleming if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
5039082eeacSAndy Fleming reg |= MIIM_M88E1145_RGMII_RX_DELAY |
5049082eeacSAndy Fleming MIIM_M88E1145_RGMII_TX_DELAY;
5059082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
5069082eeacSAndy Fleming
5079082eeacSAndy Fleming genphy_config_aneg(phydev);
5089082eeacSAndy Fleming
509ef621da7SYork Sun /* soft reset */
510ef621da7SYork Sun reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
511ef621da7SYork Sun reg |= BMCR_RESET;
512ef621da7SYork Sun phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
5139082eeacSAndy Fleming
5149082eeacSAndy Fleming return 0;
5159082eeacSAndy Fleming }
5169082eeacSAndy Fleming
m88e1145_startup(struct phy_device * phydev)5179082eeacSAndy Fleming static int m88e1145_startup(struct phy_device *phydev)
5189082eeacSAndy Fleming {
519b733c278SMichal Simek int ret;
520b733c278SMichal Simek
521b733c278SMichal Simek ret = genphy_update_link(phydev);
522b733c278SMichal Simek if (ret)
523b733c278SMichal Simek return ret;
524b733c278SMichal Simek
5259082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
5269082eeacSAndy Fleming MIIM_88E1145_PHY_LED_DIRECT);
527b733c278SMichal Simek return m88e1xxx_parse_status(phydev);
5289082eeacSAndy Fleming }
5299082eeacSAndy Fleming
5309082eeacSAndy Fleming /* Marvell 88E1149S */
m88e1149_config(struct phy_device * phydev)5319082eeacSAndy Fleming static int m88e1149_config(struct phy_device *phydev)
5329082eeacSAndy Fleming {
5339082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
5349082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
5359082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
5369082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
5379082eeacSAndy Fleming phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
5389082eeacSAndy Fleming
5399082eeacSAndy Fleming genphy_config_aneg(phydev);
5409082eeacSAndy Fleming
5419082eeacSAndy Fleming phy_reset(phydev);
5429082eeacSAndy Fleming
5439082eeacSAndy Fleming return 0;
5449082eeacSAndy Fleming }
5459082eeacSAndy Fleming
546aeceec0dSSebastian Hesselbarth /* Marvell 88E1310 */
m88e1310_config(struct phy_device * phydev)547aeceec0dSSebastian Hesselbarth static int m88e1310_config(struct phy_device *phydev)
548aeceec0dSSebastian Hesselbarth {
549aeceec0dSSebastian Hesselbarth u16 reg;
550aeceec0dSSebastian Hesselbarth
551aeceec0dSSebastian Hesselbarth /* LED link and activity */
552aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
553aeceec0dSSebastian Hesselbarth reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
554aeceec0dSSebastian Hesselbarth reg = (reg & ~0xf) | 0x1;
555aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
556aeceec0dSSebastian Hesselbarth
557aeceec0dSSebastian Hesselbarth /* Set LED2/INT to INT mode, low active */
558aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
559aeceec0dSSebastian Hesselbarth reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
560aeceec0dSSebastian Hesselbarth reg = (reg & 0x77ff) | 0x0880;
561aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
562aeceec0dSSebastian Hesselbarth
563aeceec0dSSebastian Hesselbarth /* Set RGMII delay */
564aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
565aeceec0dSSebastian Hesselbarth reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
566aeceec0dSSebastian Hesselbarth reg |= 0x0030;
567aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
568aeceec0dSSebastian Hesselbarth
569aeceec0dSSebastian Hesselbarth /* Ensure to return to page 0 */
570aeceec0dSSebastian Hesselbarth phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
571aeceec0dSSebastian Hesselbarth
57208e64cecSNathan Rossi return genphy_config_aneg(phydev);
573aeceec0dSSebastian Hesselbarth }
5749082eeacSAndy Fleming
m88e1680_config(struct phy_device * phydev)575c52d428dSDirk Eibach static int m88e1680_config(struct phy_device *phydev)
576c52d428dSDirk Eibach {
577c52d428dSDirk Eibach /*
578c52d428dSDirk Eibach * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
579c52d428dSDirk Eibach * Errata Section 4.1
580c52d428dSDirk Eibach */
581c52d428dSDirk Eibach u16 reg;
582c52d428dSDirk Eibach int res;
583c52d428dSDirk Eibach
584c52d428dSDirk Eibach /* Matrix LED mode (not neede if single LED mode is used */
585c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
586c52d428dSDirk Eibach reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
587c52d428dSDirk Eibach reg |= (1 << 5);
588c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
589c52d428dSDirk Eibach
590c52d428dSDirk Eibach /* QSGMII TX amplitude change */
591c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
592c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
593c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
594c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
595c52d428dSDirk Eibach
596c52d428dSDirk Eibach /* EEE initialization */
597c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
598c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
599c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
600c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
601c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
602c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
603c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
604c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
605c52d428dSDirk Eibach
606c52d428dSDirk Eibach res = genphy_config_aneg(phydev);
607c52d428dSDirk Eibach if (res < 0)
608c52d428dSDirk Eibach return res;
609c52d428dSDirk Eibach
610c52d428dSDirk Eibach /* soft reset */
611c52d428dSDirk Eibach reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
612c52d428dSDirk Eibach reg |= BMCR_RESET;
613c52d428dSDirk Eibach phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
614c52d428dSDirk Eibach
615c52d428dSDirk Eibach return 0;
616c52d428dSDirk Eibach }
617c52d428dSDirk Eibach
6189082eeacSAndy Fleming static struct phy_driver M88E1011S_driver = {
6199082eeacSAndy Fleming .name = "Marvell 88E1011S",
6209082eeacSAndy Fleming .uid = 0x1410c60,
6219082eeacSAndy Fleming .mask = 0xffffff0,
6229082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6239082eeacSAndy Fleming .config = &m88e1011s_config,
6249082eeacSAndy Fleming .startup = &m88e1011s_startup,
6259082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6269082eeacSAndy Fleming };
6279082eeacSAndy Fleming
6289082eeacSAndy Fleming static struct phy_driver M88E1111S_driver = {
6299082eeacSAndy Fleming .name = "Marvell 88E1111S",
6309082eeacSAndy Fleming .uid = 0x1410cc0,
6319082eeacSAndy Fleming .mask = 0xffffff0,
6329082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6339082eeacSAndy Fleming .config = &m88e1111s_config,
6349082eeacSAndy Fleming .startup = &m88e1011s_startup,
6359082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6369082eeacSAndy Fleming };
6379082eeacSAndy Fleming
6389082eeacSAndy Fleming static struct phy_driver M88E1118_driver = {
6399082eeacSAndy Fleming .name = "Marvell 88E1118",
6409082eeacSAndy Fleming .uid = 0x1410e10,
6419082eeacSAndy Fleming .mask = 0xffffff0,
6429082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6439082eeacSAndy Fleming .config = &m88e1118_config,
6449082eeacSAndy Fleming .startup = &m88e1118_startup,
6459082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6469082eeacSAndy Fleming };
6479082eeacSAndy Fleming
648b4b81e83SMichal Simek static struct phy_driver M88E1118R_driver = {
649b4b81e83SMichal Simek .name = "Marvell 88E1118R",
650b4b81e83SMichal Simek .uid = 0x1410e40,
651b4b81e83SMichal Simek .mask = 0xffffff0,
652b4b81e83SMichal Simek .features = PHY_GBIT_FEATURES,
653b4b81e83SMichal Simek .config = &m88e1118_config,
654b4b81e83SMichal Simek .startup = &m88e1118_startup,
655b4b81e83SMichal Simek .shutdown = &genphy_shutdown,
656b4b81e83SMichal Simek };
657b4b81e83SMichal Simek
6589082eeacSAndy Fleming static struct phy_driver M88E1121R_driver = {
6599082eeacSAndy Fleming .name = "Marvell 88E1121R",
6609082eeacSAndy Fleming .uid = 0x1410cb0,
6619082eeacSAndy Fleming .mask = 0xffffff0,
6629082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6639082eeacSAndy Fleming .config = &m88e1121_config,
6649082eeacSAndy Fleming .startup = &genphy_startup,
6659082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6669082eeacSAndy Fleming };
6679082eeacSAndy Fleming
6689082eeacSAndy Fleming static struct phy_driver M88E1145_driver = {
6699082eeacSAndy Fleming .name = "Marvell 88E1145",
6709082eeacSAndy Fleming .uid = 0x1410cd0,
6719082eeacSAndy Fleming .mask = 0xffffff0,
6729082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6739082eeacSAndy Fleming .config = &m88e1145_config,
6749082eeacSAndy Fleming .startup = &m88e1145_startup,
6759082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6769082eeacSAndy Fleming };
6779082eeacSAndy Fleming
6789082eeacSAndy Fleming static struct phy_driver M88E1149S_driver = {
6799082eeacSAndy Fleming .name = "Marvell 88E1149S",
6809082eeacSAndy Fleming .uid = 0x1410ca0,
6819082eeacSAndy Fleming .mask = 0xffffff0,
6829082eeacSAndy Fleming .features = PHY_GBIT_FEATURES,
6839082eeacSAndy Fleming .config = &m88e1149_config,
6849082eeacSAndy Fleming .startup = &m88e1011s_startup,
6859082eeacSAndy Fleming .shutdown = &genphy_shutdown,
6869082eeacSAndy Fleming };
6879082eeacSAndy Fleming
6888396d0abSClemens Gruber static struct phy_driver M88E1510_driver = {
6898396d0abSClemens Gruber .name = "Marvell 88E1510",
6908396d0abSClemens Gruber .uid = 0x1410dd0,
69183cfbeb0SPhil Edworthy .mask = 0xfffffff,
6928396d0abSClemens Gruber .features = PHY_GBIT_FEATURES,
6938396d0abSClemens Gruber .config = &m88e1510_config,
6948396d0abSClemens Gruber .startup = &m88e1011s_startup,
6958396d0abSClemens Gruber .shutdown = &genphy_shutdown,
696ce27eb9bSLukasz Majewski .readext = &m88e1xxx_phy_extread,
697ce27eb9bSLukasz Majewski .writeext = &m88e1xxx_phy_extwrite,
6988396d0abSClemens Gruber };
6998396d0abSClemens Gruber
700998640b4SPhil Edworthy /*
701998640b4SPhil Edworthy * This supports:
702998640b4SPhil Edworthy * 88E1518, uid 0x1410dd1
703998640b4SPhil Edworthy * 88E1512, uid 0x1410dd4
704998640b4SPhil Edworthy */
7051415107eSMichal Simek static struct phy_driver M88E1518_driver = {
7061415107eSMichal Simek .name = "Marvell 88E1518",
707998640b4SPhil Edworthy .uid = 0x1410dd0,
708998640b4SPhil Edworthy .mask = 0xffffffa,
7091415107eSMichal Simek .features = PHY_GBIT_FEATURES,
71035fa0ddaSHao Zhang .config = &m88e1518_config,
7111415107eSMichal Simek .startup = &m88e1011s_startup,
7121415107eSMichal Simek .shutdown = &genphy_shutdown,
713ce27eb9bSLukasz Majewski .readext = &m88e1xxx_phy_extread,
714ce27eb9bSLukasz Majewski .writeext = &m88e1xxx_phy_extwrite,
7151415107eSMichal Simek };
7161415107eSMichal Simek
717aeceec0dSSebastian Hesselbarth static struct phy_driver M88E1310_driver = {
718aeceec0dSSebastian Hesselbarth .name = "Marvell 88E1310",
719aeceec0dSSebastian Hesselbarth .uid = 0x01410e90,
720aeceec0dSSebastian Hesselbarth .mask = 0xffffff0,
721aeceec0dSSebastian Hesselbarth .features = PHY_GBIT_FEATURES,
722aeceec0dSSebastian Hesselbarth .config = &m88e1310_config,
723aeceec0dSSebastian Hesselbarth .startup = &m88e1011s_startup,
724aeceec0dSSebastian Hesselbarth .shutdown = &genphy_shutdown,
725aeceec0dSSebastian Hesselbarth };
726aeceec0dSSebastian Hesselbarth
727c52d428dSDirk Eibach static struct phy_driver M88E1680_driver = {
728c52d428dSDirk Eibach .name = "Marvell 88E1680",
729c52d428dSDirk Eibach .uid = 0x1410ed0,
730c52d428dSDirk Eibach .mask = 0xffffff0,
731c52d428dSDirk Eibach .features = PHY_GBIT_FEATURES,
732c52d428dSDirk Eibach .config = &m88e1680_config,
733c52d428dSDirk Eibach .startup = &genphy_startup,
734c52d428dSDirk Eibach .shutdown = &genphy_shutdown,
735c52d428dSDirk Eibach };
736c52d428dSDirk Eibach
phy_marvell_init(void)7379082eeacSAndy Fleming int phy_marvell_init(void)
7389082eeacSAndy Fleming {
739aeceec0dSSebastian Hesselbarth phy_register(&M88E1310_driver);
7409082eeacSAndy Fleming phy_register(&M88E1149S_driver);
7419082eeacSAndy Fleming phy_register(&M88E1145_driver);
7429082eeacSAndy Fleming phy_register(&M88E1121R_driver);
7439082eeacSAndy Fleming phy_register(&M88E1118_driver);
744b4b81e83SMichal Simek phy_register(&M88E1118R_driver);
7459082eeacSAndy Fleming phy_register(&M88E1111S_driver);
7469082eeacSAndy Fleming phy_register(&M88E1011S_driver);
7478396d0abSClemens Gruber phy_register(&M88E1510_driver);
7481415107eSMichal Simek phy_register(&M88E1518_driver);
749c52d428dSDirk Eibach phy_register(&M88E1680_driver);
7509082eeacSAndy Fleming
7519082eeacSAndy Fleming return 0;
7529082eeacSAndy Fleming }
753