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Searched refs:phy_set_bits (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c286 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168bb_hw_phy_config()
307 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168cp_2_hw_phy_config()
308 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168cp_2_hw_phy_config()
337 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_1_hw_phy_config()
338 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_1_hw_phy_config()
364 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_2_hw_phy_config()
365 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_2_hw_phy_config()
366 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_2_hw_phy_config()
386 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_3_hw_phy_config()
387 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_3_hw_phy_config()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dnxp-tja11xx.c130 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); in tja11xx_enable_reg_write()
135 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_enable_link_control()
155 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup()
331 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_config_init()
734 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST); in tja11xx_cable_test_start()
795 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_get_status()
H A Dnxp-cbtx.c89 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
105 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
H A Dmediatek-ge.c61 phy_set_bits(phydev, 0x17, BIT(4)); in mt7531_phy_config_init()
H A Dadin.c367 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, in adin_set_downshift()
521 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG, in adin_phy_config_intr()
659 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); in adin_config_aneg()
H A Dsmsc.c94 return phy_set_bits(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_edpd()
194 int rc = phy_set_bits(phydev, PHY_EDPD_CONFIG, in lan95xx_config_aneg_ext()
H A Dbroadcom.c155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
748 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, in brcm_fet_config_init()
755 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in brcm_fet_config_init()
H A Drealtek.c341 return phy_set_bits(phydev, MII_CTRL1000, in rtl8211c_config_init()
531 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, in rtl8366rb_config_init()
H A Dicplus.c281 ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON); in ip101a_config_init()
H A Dat803x.c1629 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); in qca83xx_config_init()
1665 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); in qca83xx_resume()
H A Dmxl-gpy.c755 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); in gpy_set_wol()
H A Ddp83867.c989 phy_set_bits(phydev, DP83867_CFG2, in dp83867_link_change_notify()
H A Dbcm-phy-lib.c637 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE); in bcm_phy_enable_jumbo()
H A Dmarvell.c1252 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1496 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
H A Dphy_device.c2699 return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_suspend()
H A Dmicrel.c1277 return phy_set_bits(phydev, 0x1e, BIT(9)); in ksz9131_led_errata()
/openbmc/linux/include/linux/
H A Dphy.h1424 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_set_bits() function