Home
last modified time | relevance | path

Searched refs:gpu (Results 1 – 25 of 606) sorted by relevance

12345678910>>...25

/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c403 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
485 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
487 gpu->base_rate_shader >> gpu->freq_scale); in etnaviv_gpu_update_clock()
502 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), in etnaviv_gpu_update_clock()
1135 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1354 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1427 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1435 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_recover_hang() local
1558 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1769 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
[all …]
H A Detnaviv_sched.c37 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
59 (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
61 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
62 gpu->hangcheck_fence = gpu->completed_fence; in etnaviv_sched_timedout_job()
75 drm_sched_start(&gpu->sched, true); in etnaviv_sched_timedout_job()
80 drm_sched_start(&gpu->sched, true); in etnaviv_sched_timedout_job()
101 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_push_job() local
109 mutex_lock(&gpu->sched_lock); in etnaviv_sched_push_job()
128 mutex_unlock(&gpu->sched_lock); in etnaviv_sched_push_job()
140 dev_name(gpu->dev), gpu->dev); in etnaviv_sched_init()
[all …]
H A Detnaviv_buffer.c95 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
103 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
167 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_init()
184 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_config_mmuv2()
219 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_config_pta()
241 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_end()
243 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_buffer_end()
307 lockdep_assert_held(&gpu->lock); in etnaviv_sync_point_queue()
355 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_queue()
438 gpu->flush_seq = new_flush_seq; in etnaviv_buffer_queue()
[all …]
H A Detnaviv_gpu.h168 writel(data, gpu->mmio + reg); in gpu_write()
173 return readl(gpu->mmio + reg); in gpu_read()
179 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
180 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
188 writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg)); in gpu_write_power()
193 return readl(gpu->mmio + gpu_fix_power_address(gpu, reg)); in gpu_read_power()
198 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
206 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
209 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
213 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
[all …]
H A Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
66 pipe_select(gpu, clock, i); in pipe_perf_reg_read()
71 pipe_select(gpu, clock, 0); in pipe_perf_reg_read()
85 pipe_select(gpu, clock, i); in pipe_reg_read()
86 value += gpu_read(gpu, signal->data); in pipe_reg_read()
90 pipe_select(gpu, clock, 0); in pipe_reg_read()
106 return gpu_read(gpu, reg); in hi_total_cycle_read()
120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
508 dom = pm_domain(gpu, domain->iter); in etnaviv_pm_query_dom()
533 dom = pm_domain(gpu, signal->domain); in etnaviv_pm_query_sig()
[all …]
H A Detnaviv_drv.c74 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
77 if (gpu) { in etnaviv_open()
101 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
103 if (gpu) in etnaviv_postclose()
223 gpu = priv->gpu[i]; in show_each_gpu()
265 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_get_param()
266 if (!gpu) in etnaviv_ioctl_get_param()
361 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_wait_fence()
412 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_gem_wait()
440 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_pm_query_dom()
[all …]
H A Detnaviv_iommu_v2.c175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
199 if (gpu->mmu_context) in etnaviv_iommuv2_restore_sec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
224 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_sec()
226 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_sec()
247 switch (gpu->sec_mode) { in etnaviv_iommuv2_restore()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.c60 if (gpu->core_clk && gpu->fast_rate) in enable_clk()
169 ret = gpu->funcs->hw_init(gpu); in msm_gpu_hw_init()
207 gpu->funcs->show(gpu, state, &p); in msm_gpu_devcoredump_read()
270 state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_crashstate_capture()
425 gpu->funcs->recover(gpu); in recover_worker()
437 gpu->funcs->submit(gpu, submit); in recover_worker()
502 if (!gpu->funcs->progress(gpu, ring)) in made_progress()
781 gpu->funcs->submit(gpu, submit); in msm_gpu_submit()
795 return gpu->funcs->irq(gpu); in irq_handler()
936 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev); in msm_gpu_init()
[all …]
H A Dmsm_gpu_devfreq.c48 gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); in msm_devfreq_target()
72 return gpu->funcs->gpu_get_freq(gpu); in get_freq()
99 busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); in msm_devfreq_get_dev_status()
190 gpu->cooling = NULL; in msm_devfreq_init()
215 if (!has_devfreq(gpu)) in msm_devfreq_cleanup()
227 if (!has_devfreq(gpu)) in msm_devfreq_resume()
231 df->busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); in msm_devfreq_resume()
243 if (!has_devfreq(gpu)) in msm_devfreq_suspend()
269 if (!has_devfreq(gpu)) in msm_devfreq_boost()
272 freq = get_freq(gpu); in msm_devfreq_boost()
[all …]
H A Dmsm_gpu.h84 (struct msm_gpu *gpu);
470 if (rn >= gpu->nr_rings) in msm_gpu_convert_priority()
678 mutex_lock(&gpu->lock); in msm_gpu_crashstate_get()
680 if (gpu->crashstate) { in msm_gpu_crashstate_get()
682 state = gpu->crashstate; in msm_gpu_crashstate_get()
685 mutex_unlock(&gpu->lock); in msm_gpu_crashstate_get()
692 mutex_lock(&gpu->lock); in msm_gpu_crashstate_put()
694 if (gpu->crashstate) { in msm_gpu_crashstate_put()
695 if (gpu->funcs->gpu_state_put(gpu->crashstate)) in msm_gpu_crashstate_put()
696 gpu->crashstate = NULL; in msm_gpu_crashstate_put()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c180 return a4xx_idle(gpu); in a4xx_me_init()
325 gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a4xx_hw_init()
363 a4xx_dump(gpu); in a4xx_recover()
368 adreno_recover(gpu); in a4xx_recover()
376 DBG("%s", gpu->name); in a4xx_destroy()
388 if (!adreno_idle(gpu, gpu->rb[0])) in a4xx_idle()
418 msm_gpu_retire(gpu); in a4xx_irq()
569 adreno_dump(gpu); in a4xx_dump()
658 struct msm_gpu *gpu; in a4xx_gpu_init() local
696 if (!gpu->aspace) { in a4xx_gpu_init()
[all …]
H A Da3xx_gpu.c109 return a3xx_idle(gpu); in a3xx_me_init()
119 DBG("%s", gpu->name); in a3xx_hw_init()
276 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a3xx_hw_init()
364 a3xx_dump(gpu); in a3xx_recover()
369 adreno_recover(gpu); in a3xx_recover()
389 if (!adreno_idle(gpu, gpu->rb[0])) in a3xx_idle()
415 msm_gpu_retire(gpu); in a3xx_irq()
463 adreno_dump(gpu); in a3xx_dump()
530 struct msm_gpu *gpu; in a3xx_gpu_init() local
569 if (!gpu->aspace) { in a3xx_gpu_init()
[all …]
H A Da5xx_gpu.c922 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
962 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
963 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
980 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
981 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
1015 a5xx_dump(gpu); in a5xx_recover()
1224 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a5xx_fault_detect_irq()
1248 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_fault_detect_irq()
1371 gpu->name, in a5xx_pm_resume()
1382 gpu->name); in a5xx_pm_resume()
[all …]
H A Dadreno_gpu.h209 return gpu->chip_id & 0xff; in adreno_patchid()
214 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_revn()
221 return gpu->gmu_is_wrapper; in adreno_has_gmu_wrapper()
226 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_a2xx()
233 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_a20x()
266 return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0); in adreno_is_a330v2()
336 return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); in adreno_is_a619_holi()
377 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_a630_family()
384 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_a660_family()
392 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_a650_family()
[all …]
H A Da5xx_power.c164 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a530_lm_setup()
165 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a530_lm_setup()
199 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a540_lm_setup()
200 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a540_lm_setup()
247 gpu->name); in a5xx_gpmu_init()
264 gpu->name); in a5xx_gpmu_init()
271 gpu->name, val); in a5xx_gpmu_init()
306 a530_lm_setup(gpu); in a5xx_power_init()
308 a540_lm_setup(gpu); in a5xx_power_init()
311 a5xx_pc_init(gpu); in a5xx_power_init()
[all …]
H A Da2xx_gpu.c105 return a2xx_idle(gpu); in a2xx_me_init()
118 DBG("%s", gpu->name); in a2xx_hw_init()
219 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a2xx_hw_init()
279 a2xx_dump(gpu); in a2xx_recover()
284 adreno_recover(gpu); in a2xx_recover()
302 if (!adreno_idle(gpu, gpu->rb[0])) in a2xx_idle()
351 msm_gpu_retire(gpu); in a2xx_irq()
452 adreno_dump(gpu); in a2xx_dump()
520 struct msm_gpu *gpu; in a2xx_gpu_init() local
554 if (!gpu->aspace) { in a2xx_gpu_init()
[all …]
H A Da6xx_gpu.c1393 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1435 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1436 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1504 a6xx_dump(gpu); in a6xx_recover()
1671 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a6xx_fault_detect_irq()
1703 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_fault_detect_irq()
1956 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_resume()
2025 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_suspend()
2377 if (gpu->aspace) in a6xx_gpu_init()
2378 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, in a6xx_gpu_init()
[all …]
H A Da5xx_preempt.c66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
86 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_timer()
97 if (gpu->nr_rings == 1) in a5xx_preempt_trigger()
108 ring = get_next_ring(gpu); in a5xx_preempt_trigger()
180 gpu->name); in a5xx_preempt_irq()
181 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_irq()
203 if (gpu->nr_rings == 1) in a5xx_preempt_hw_init()
285 if (gpu->nr_rings <= 1) in a5xx_preempt_init()
294 a5xx_preempt_fini(gpu); in a5xx_preempt_init()
[all …]
H A Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
79 show(priv->gpu, &p); in show()
97 struct msm_gpu *gpu = priv->gpu; in reset_set() local
110 mutex_lock(&gpu->lock); in reset_set()
130 gpu->needs_hw_init = true; in reset_set()
132 pm_runtime_get_sync(&gpu->pdev->dev); in reset_set()
133 gpu->funcs->recover(gpu); in reset_set()
135 pm_runtime_put_sync(&gpu->pdev->dev); in reset_set()
[all …]
H A Dadreno_gpu.c265 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); in adreno_fault_handler()
303 kthread_queue_work(gpu->worker, &gpu->fault_work); in adreno_fault_handler()
559 VERB("%s", gpu->name); in adreno_hw_init()
589 return gpu->funcs->get_rptr(gpu, ring); in get_rptr()
594 return gpu->rb[0]; in adreno_active_ring()
605 gpu->funcs->pm_suspend(gpu); in adreno_recover()
606 gpu->funcs->pm_resume(gpu); in adreno_recover()
970 struct msm_gpu *gpu) in adreno_get_pwrlevels() argument
977 gpu->fast_rate = 0; in adreno_get_pwrlevels()
1003 gpu->fast_rate = freq; in adreno_get_pwrlevels()
[all …]
H A Da6xx_gpu_state.c124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
216 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
219 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
265 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
271 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
280 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
398 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
421 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
905 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
910 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
[all …]
H A Dadreno_device.c550 if (!gpu) { in adreno_load_gpu()
568 ret = gpu->funcs->ucode_load(gpu); in adreno_load_gpu()
598 gpu->funcs->debugfs_init(gpu, dev->primary); in adreno_load_gpu()
599 gpu->funcs->debugfs_init(gpu, dev->render); in adreno_load_gpu()
603 return gpu; in adreno_load_gpu()
690 if (IS_ERR(gpu)) { in adreno_bind()
711 gpu->funcs->destroy(gpu); in adreno_unbind()
779 return gpu->funcs->pm_resume(gpu); in adreno_runtime_resume()
793 return gpu->funcs->pm_suspend(gpu); in adreno_runtime_suspend()
832 if (!gpu) in adreno_system_suspend()
[all …]
H A Da5xx_gpu.h135 int a5xx_power_init(struct msm_gpu *gpu);
136 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
138 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
143 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
154 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
155 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
157 void a5xx_preempt_init(struct msm_gpu *gpu);
158 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
159 void a5xx_preempt_trigger(struct msm_gpu *gpu);
160 void a5xx_preempt_irq(struct msm_gpu *gpu);
[all …]
/openbmc/linux/Documentation/gpu/
H A Ddrm-kms-helpers.rst154 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
160 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
166 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
172 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
188 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
215 .. kernel-doc:: drivers/gpu/drm/drm_panel.c
221 .. kernel-doc:: drivers/gpu/drm/drm_panel.c
363 .. kernel-doc:: drivers/gpu/drm/drm_edid.c
401 .. kernel-doc:: drivers/gpu/drm/drm_rect.c
428 .. kernel-doc:: drivers/gpu/drm/drm_of.c
[all …]
H A Di915.rst19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
[all …]

12345678910>>...25