Lines Matching refs:gpu

165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu,  in etnaviv_iommuv2_restore_nonsec()  argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
199 if (gpu->mmu_context) in etnaviv_iommuv2_restore_sec()
200 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_sec()
201 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_sec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
223 prefetch = etnaviv_buffer_config_pta(gpu, v2_context->id); in etnaviv_iommuv2_restore_sec()
224 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_sec()
226 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
244 static void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore() argument
247 switch (gpu->sec_mode) { in etnaviv_iommuv2_restore()
249 etnaviv_iommuv2_restore_nonsec(gpu, context); in etnaviv_iommuv2_restore()
252 etnaviv_iommuv2_restore_sec(gpu, context); in etnaviv_iommuv2_restore()