10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)  in a2xx_submit()  argument
25 			if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)  in a2xx_submit()
51 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu)  in a2xx_me_init()  argument
56 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_me_init()
58 	struct msm_ringbuffer *ring = gpu->rb[0];  in a2xx_me_init()
104 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a2xx_me_init()
105 	return a2xx_idle(gpu);  in a2xx_me_init()
108 static int a2xx_hw_init(struct msm_gpu *gpu)  in a2xx_hw_init()  argument
110 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_hw_init()
116 	msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);  in a2xx_hw_init()
118 	DBG("%s", gpu->name);  in a2xx_hw_init()
121 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);  in a2xx_hw_init()
123 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);  in a2xx_hw_init()
124 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);  in a2xx_hw_init()
127 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);  in a2xx_hw_init()
129 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);  in a2xx_hw_init()
132 		gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);  in a2xx_hw_init()
135 	gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);  in a2xx_hw_init()
138 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);  in a2xx_hw_init()
139 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);  in a2xx_hw_init()
141 	gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |  in a2xx_hw_init()
155 	gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |  in a2xx_hw_init()
158 	gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);  in a2xx_hw_init()
159 	gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);  in a2xx_hw_init()
161 	gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,  in a2xx_hw_init()
165 	gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,  in a2xx_hw_init()
180 		gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);  in a2xx_hw_init()
182 	gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);  in a2xx_hw_init()
183 	gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);  in a2xx_hw_init()
185 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */  in a2xx_hw_init()
186 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */  in a2xx_hw_init()
189 	gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);  in a2xx_hw_init()
191 	gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,  in a2xx_hw_init()
193 	gpu_write(gpu, REG_AXXX_CP_INT_CNTL,  in a2xx_hw_init()
201 	gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);  in a2xx_hw_init()
202 	gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,  in a2xx_hw_init()
210 	gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);  in a2xx_hw_init()
212 	ret = adreno_hw_init(gpu);  in a2xx_hw_init()
216 	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,  in a2xx_hw_init()
219 	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a2xx_hw_init()
238 		dev_warn(gpu->dev->dev,  in a2xx_hw_init()
243 	gpu_write(gpu, REG_AXXX_CP_DEBUG,  in a2xx_hw_init()
245 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a2xx_hw_init()
247 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);  in a2xx_hw_init()
254 	gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);  in a2xx_hw_init()
256 		gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);  in a2xx_hw_init()
258 	gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);  in a2xx_hw_init()
261 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a2xx_hw_init()
263 	return a2xx_me_init(gpu) ? 0 : -EINVAL;  in a2xx_hw_init()
266 static void a2xx_recover(struct msm_gpu *gpu)  in a2xx_recover()  argument
270 	adreno_dump_info(gpu);  in a2xx_recover()
274 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));  in a2xx_recover()
279 		a2xx_dump(gpu);  in a2xx_recover()
281 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);  in a2xx_recover()
282 	gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET);  in a2xx_recover()
283 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);  in a2xx_recover()
284 	adreno_recover(gpu);  in a2xx_recover()
287 static void a2xx_destroy(struct msm_gpu *gpu)  in a2xx_destroy()  argument
289 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_destroy()
292 	DBG("%s", gpu->name);  in a2xx_destroy()
299 static bool a2xx_idle(struct msm_gpu *gpu)  in a2xx_idle()  argument
302 	if (!adreno_idle(gpu, gpu->rb[0]))  in a2xx_idle()
306 	if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) &  in a2xx_idle()
308 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);  in a2xx_idle()
317 static irqreturn_t a2xx_irq(struct msm_gpu *gpu)  in a2xx_irq()  argument
321 	mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL);  in a2xx_irq()
324 		status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS);  in a2xx_irq()
326 		dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status);  in a2xx_irq()
327 		dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n",  in a2xx_irq()
328 			gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT));  in a2xx_irq()
330 		gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);  in a2xx_irq()
334 		status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS);  in a2xx_irq()
338 			dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status);  in a2xx_irq()
340 		gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);  in a2xx_irq()
344 		status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS);  in a2xx_irq()
346 		dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status);  in a2xx_irq()
348 		gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);  in a2xx_irq()
351 	msm_gpu_retire(gpu);  in a2xx_irq()
448 static void a2xx_dump(struct msm_gpu *gpu)  in a2xx_dump()  argument
451 			gpu_read(gpu, REG_A2XX_RBBM_STATUS));  in a2xx_dump()
452 	adreno_dump(gpu);  in a2xx_dump()
455 static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)  in a2xx_gpu_state_get()  argument
462 	adreno_gpu_state_get(gpu, state);  in a2xx_gpu_state_get()
464 	state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS);  in a2xx_gpu_state_get()
470 a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)  in a2xx_create_address_space()  argument
472 	struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);  in a2xx_create_address_space()
484 static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in a2xx_get_rptr()  argument
486 	ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);  in a2xx_get_rptr()
520 	struct msm_gpu *gpu;  in a2xx_gpu_init()  local
538 	gpu = &adreno_gpu->base;  in a2xx_gpu_init()
540 	gpu->perfcntrs = perfcntrs;  in a2xx_gpu_init()
541 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);  in a2xx_gpu_init()
554 	if (!gpu->aspace) {  in a2xx_gpu_init()
562 	return gpu;  in a2xx_gpu_init()