1f6ffbd4fSLucas Stach /* SPDX-License-Identifier: GPL-2.0 */
2a8c21a54SThe etnaviv authors /*
3f6ffbd4fSLucas Stach * Copyright (C) 2015-2018 Etnaviv Project
4a8c21a54SThe etnaviv authors */
5a8c21a54SThe etnaviv authors
6a8c21a54SThe etnaviv authors #ifndef __ETNAVIV_GPU_H__
7a8c21a54SThe etnaviv authors #define __ETNAVIV_GPU_H__
8a8c21a54SThe etnaviv authors
92f9225dbSLucas Stach #include "etnaviv_cmdbuf.h"
10db82a043SLucas Stach #include "etnaviv_gem.h"
1127b67278SLucas Stach #include "etnaviv_mmu.h"
12a8c21a54SThe etnaviv authors #include "etnaviv_drv.h"
1361a6920bSDoug Brown #include "common.xml.h"
14a8c21a54SThe etnaviv authors
15a8c21a54SThe etnaviv authors struct etnaviv_gem_submit;
16b6325f40SRussell King struct etnaviv_vram_mapping;
17a8c21a54SThe etnaviv authors
18a8c21a54SThe etnaviv authors struct etnaviv_chip_identity {
19a8c21a54SThe etnaviv authors u32 model;
20a8c21a54SThe etnaviv authors u32 revision;
21815e45bbSChristian Gmeiner u32 product_id;
22815e45bbSChristian Gmeiner u32 customer_id;
23815e45bbSChristian Gmeiner u32 eco_id;
24a8c21a54SThe etnaviv authors
25a8c21a54SThe etnaviv authors /* Supported feature fields. */
26a8c21a54SThe etnaviv authors u32 features;
27a8c21a54SThe etnaviv authors
28a8c21a54SThe etnaviv authors /* Supported minor feature fields. */
29a8c21a54SThe etnaviv authors u32 minor_features0;
30a8c21a54SThe etnaviv authors u32 minor_features1;
31a8c21a54SThe etnaviv authors u32 minor_features2;
32a8c21a54SThe etnaviv authors u32 minor_features3;
33602eb489SRussell King u32 minor_features4;
34602eb489SRussell King u32 minor_features5;
350538aaf9SLucas Stach u32 minor_features6;
360538aaf9SLucas Stach u32 minor_features7;
370538aaf9SLucas Stach u32 minor_features8;
380538aaf9SLucas Stach u32 minor_features9;
390538aaf9SLucas Stach u32 minor_features10;
400538aaf9SLucas Stach u32 minor_features11;
41602eb489SRussell King
42a8c21a54SThe etnaviv authors /* Number of streams supported. */
43a8c21a54SThe etnaviv authors u32 stream_count;
44a8c21a54SThe etnaviv authors
45a8c21a54SThe etnaviv authors /* Total number of temporary registers per thread. */
46a8c21a54SThe etnaviv authors u32 register_max;
47a8c21a54SThe etnaviv authors
48a8c21a54SThe etnaviv authors /* Maximum number of threads. */
49a8c21a54SThe etnaviv authors u32 thread_count;
50a8c21a54SThe etnaviv authors
51a8c21a54SThe etnaviv authors /* Number of shader cores. */
52a8c21a54SThe etnaviv authors u32 shader_core_count;
53a8c21a54SThe etnaviv authors
54ab3d7b6dSTomeu Vizoso /* Number of Neural Network cores. */
55ab3d7b6dSTomeu Vizoso u32 nn_core_count;
56ab3d7b6dSTomeu Vizoso
57a8c21a54SThe etnaviv authors /* Size of the vertex cache. */
58a8c21a54SThe etnaviv authors u32 vertex_cache_size;
59a8c21a54SThe etnaviv authors
60a8c21a54SThe etnaviv authors /* Number of entries in the vertex output buffer. */
61a8c21a54SThe etnaviv authors u32 vertex_output_buffer_size;
62a8c21a54SThe etnaviv authors
63a8c21a54SThe etnaviv authors /* Number of pixel pipes. */
64a8c21a54SThe etnaviv authors u32 pixel_pipes;
65a8c21a54SThe etnaviv authors
66a8c21a54SThe etnaviv authors /* Number of instructions. */
67a8c21a54SThe etnaviv authors u32 instruction_count;
68a8c21a54SThe etnaviv authors
69a8c21a54SThe etnaviv authors /* Number of constants. */
70a8c21a54SThe etnaviv authors u32 num_constants;
71a8c21a54SThe etnaviv authors
72a8c21a54SThe etnaviv authors /* Buffer size */
73a8c21a54SThe etnaviv authors u32 buffer_size;
74602eb489SRussell King
75602eb489SRussell King /* Number of varyings */
76602eb489SRussell King u8 varyings_count;
77a8c21a54SThe etnaviv authors };
78a8c21a54SThe etnaviv authors
79007ad58dSLucas Stach enum etnaviv_sec_mode {
80007ad58dSLucas Stach ETNA_SEC_NONE = 0,
81007ad58dSLucas Stach ETNA_SEC_KERNEL,
82007ad58dSLucas Stach ETNA_SEC_TZ
83007ad58dSLucas Stach };
84007ad58dSLucas Stach
85a8c21a54SThe etnaviv authors struct etnaviv_event {
86f54d1867SChris Wilson struct dma_fence *fence;
87ef146c00SLucas Stach struct etnaviv_gem_submit *submit;
88357713ceSChristian Gmeiner
89357713ceSChristian Gmeiner void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
90a8c21a54SThe etnaviv authors };
91a8c21a54SThe etnaviv authors
92e66774ddSLucas Stach struct etnaviv_cmdbuf_suballoc;
93f9d255f4SLucas Stach struct regulator;
94f9d255f4SLucas Stach struct clk;
95a8c21a54SThe etnaviv authors
96355502e0SChristian Gmeiner #define ETNA_NR_EVENTS 30
97355502e0SChristian Gmeiner
98647d817dSLucas Stach enum etnaviv_gpu_state {
99647d817dSLucas Stach ETNA_GPU_STATE_UNKNOWN = 0,
100647d817dSLucas Stach ETNA_GPU_STATE_IDENTIFIED,
101647d817dSLucas Stach ETNA_GPU_STATE_RESET,
102647d817dSLucas Stach ETNA_GPU_STATE_INITIALIZED,
103647d817dSLucas Stach ETNA_GPU_STATE_RUNNING,
104*9ec2afdeSLucas Stach ETNA_GPU_STATE_FAULT,
105647d817dSLucas Stach };
106647d817dSLucas Stach
107a8c21a54SThe etnaviv authors struct etnaviv_gpu {
108a8c21a54SThe etnaviv authors struct drm_device *drm;
109bcdfb5e5SRussell King struct thermal_cooling_device *cooling;
110a8c21a54SThe etnaviv authors struct device *dev;
111a8c21a54SThe etnaviv authors struct mutex lock;
112a8c21a54SThe etnaviv authors struct etnaviv_chip_identity identity;
113007ad58dSLucas Stach enum etnaviv_sec_mode sec_mode;
114a7790d78SLucas Stach struct workqueue_struct *wq;
1152cd5bd98SLucas Stach struct mutex sched_lock;
116e93b6deeSLucas Stach struct drm_gpu_scheduler sched;
117647d817dSLucas Stach enum etnaviv_gpu_state state;
118a8c21a54SThe etnaviv authors
119a8c21a54SThe etnaviv authors /* 'ring'-buffer: */
1202f9225dbSLucas Stach struct etnaviv_cmdbuf buffer;
121f6086311SRussell King int exec_state;
122a8c21a54SThe etnaviv authors
123a8c21a54SThe etnaviv authors /* event management: */
124355502e0SChristian Gmeiner DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
125355502e0SChristian Gmeiner struct etnaviv_event event[ETNA_NR_EVENTS];
126a8c21a54SThe etnaviv authors struct completion event_free;
127a8c21a54SThe etnaviv authors spinlock_t event_spinlock;
128a8c21a54SThe etnaviv authors
129a8c21a54SThe etnaviv authors u32 idle_mask;
130a8c21a54SThe etnaviv authors
131a8c21a54SThe etnaviv authors /* Fencing support */
132764be123SLucas Stach struct xarray user_fences;
133764be123SLucas Stach u32 next_user_fence;
134a8c21a54SThe etnaviv authors u32 next_fence;
135a8c21a54SThe etnaviv authors u32 completed_fence;
136a8c21a54SThe etnaviv authors wait_queue_head_t fence_event;
13776bf0db5SChristian König u64 fence_context;
138a8c21a54SThe etnaviv authors spinlock_t fence_spinlock;
139a8c21a54SThe etnaviv authors
140357713ceSChristian Gmeiner /* worker for handling 'sync' points: */
141357713ceSChristian Gmeiner struct work_struct sync_point_work;
142357713ceSChristian Gmeiner int sync_point_event;
143357713ceSChristian Gmeiner
1442c83a726SLucas Stach /* hang detection */
1452c83a726SLucas Stach u32 hangcheck_dma_addr;
146cdd15695SLucas Stach u32 hangcheck_fence;
1472c83a726SLucas Stach
148a8c21a54SThe etnaviv authors void __iomem *mmio;
149a8c21a54SThe etnaviv authors int irq;
150a8c21a54SThe etnaviv authors
15127b67278SLucas Stach struct etnaviv_iommu_context *mmu_context;
1524900dda9SLucas Stach unsigned int flush_seq;
153a8c21a54SThe etnaviv authors
154a8c21a54SThe etnaviv authors /* Power Control: */
155a8c21a54SThe etnaviv authors struct clk *clk_bus;
15665f037e8SLucas Stach struct clk *clk_reg;
157a8c21a54SThe etnaviv authors struct clk *clk_core;
158a8c21a54SThe etnaviv authors struct clk *clk_shader;
159a8c21a54SThe etnaviv authors
160bcdfb5e5SRussell King unsigned int freq_scale;
161295b6c02SLucas Stach unsigned int fe_waitcycles;
162d79fd1ccSLucas Stach unsigned long base_rate_core;
163d79fd1ccSLucas Stach unsigned long base_rate_shader;
164a8c21a54SThe etnaviv authors };
165a8c21a54SThe etnaviv authors
gpu_write(struct etnaviv_gpu * gpu,u32 reg,u32 data)166a8c21a54SThe etnaviv authors static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
167a8c21a54SThe etnaviv authors {
168a98b1e78SLucas Stach writel(data, gpu->mmio + reg);
169a8c21a54SThe etnaviv authors }
170a8c21a54SThe etnaviv authors
gpu_read(struct etnaviv_gpu * gpu,u32 reg)171a8c21a54SThe etnaviv authors static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
172a8c21a54SThe etnaviv authors {
173a98b1e78SLucas Stach return readl(gpu->mmio + reg);
174a8c21a54SThe etnaviv authors }
175a8c21a54SThe etnaviv authors
gpu_fix_power_address(struct etnaviv_gpu * gpu,u32 reg)17661a6920bSDoug Brown static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg)
17761a6920bSDoug Brown {
17861a6920bSDoug Brown /* Power registers in GC300 < 2.0 are offset by 0x100 */
17961a6920bSDoug Brown if (gpu->identity.model == chipModel_GC300 &&
18061a6920bSDoug Brown gpu->identity.revision < 0x2000)
18161a6920bSDoug Brown reg += 0x100;
18261a6920bSDoug Brown
18361a6920bSDoug Brown return reg;
18461a6920bSDoug Brown }
18561a6920bSDoug Brown
gpu_write_power(struct etnaviv_gpu * gpu,u32 reg,u32 data)18661a6920bSDoug Brown static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data)
18761a6920bSDoug Brown {
18861a6920bSDoug Brown writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
18961a6920bSDoug Brown }
19061a6920bSDoug Brown
gpu_read_power(struct etnaviv_gpu * gpu,u32 reg)19161a6920bSDoug Brown static inline u32 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg)
19261a6920bSDoug Brown {
19361a6920bSDoug Brown return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
19461a6920bSDoug Brown }
19561a6920bSDoug Brown
196a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
197a8c21a54SThe etnaviv authors
198a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
199681c19c8SLucas Stach bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
200a8c21a54SThe etnaviv authors
201a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS
202a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
203a8c21a54SThe etnaviv authors #endif
204a8c21a54SThe etnaviv authors
205f51d753fSChristian Gmeiner void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit);
206a8c21a54SThe etnaviv authors void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
207a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
20838c4a4cfSArnd Bergmann u32 fence, struct drm_etnaviv_timespec *timeout);
209a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
21038c4a4cfSArnd Bergmann struct etnaviv_gem_object *etnaviv_obj,
21138c4a4cfSArnd Bergmann struct drm_etnaviv_timespec *timeout);
212e93b6deeSLucas Stach struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
213a8c21a54SThe etnaviv authors int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
214a8c21a54SThe etnaviv authors void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
215b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
216229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
217a8c21a54SThe etnaviv authors
218a8c21a54SThe etnaviv authors extern struct platform_driver etnaviv_gpu_driver;
219a8c21a54SThe etnaviv authors
220a8c21a54SThe etnaviv authors #endif /* __ETNAVIV_GPU_H__ */
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