Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43 |
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90b593ce |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Switch to chip-id for identifying GPU
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. Th
drm/msm/adreno: Switch to chip-id for identifying GPU
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549782/
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47bd37f9 |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move adreno info to config
Let's just stash it in adreno_platform_config rather than looking it up in N different places.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-
drm/msm/adreno: Move adreno info to config
Let's just stash it in adreno_platform_config rather than looking it up in N different places.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549777/
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8825f596 |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add helper for formating chip-id
This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better.
Signed-off-by: Rob Clark <robd
drm/msm/adreno: Add helper for formating chip-id
This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549774/
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67133dc0 |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add adreno family
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id.
drm/msm/adreno: Add adreno family
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id.
v2: Fix is_a2xx() typo
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549773/
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75a5227c |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Bring the a630 family together
All of these are derivatives of a630.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwor
drm/msm/adreno: Bring the a630 family together
All of these are derivatives of a630.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549770/
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c928a05e |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move speedbin mapping to device table
This simplifies the code.
v2: Use a table of structs instead of flat uint32_t[]
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by:
drm/msm/adreno: Move speedbin mapping to device table
This simplifies the code.
v2: Use a table of structs instead of flat uint32_t[]
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549769/
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f30a648d |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Allow SoC specific gpu device table entries
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to spe
drm/msm/adreno: Allow SoC specific gpu device table entries
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549767/
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155668ef |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk to identify cached-coherent support
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like g
drm/msm/adreno: Use quirk to identify cached-coherent support
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549765/
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459f9e26 |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk identify hw_apriv
Rather than just open coding a list of gpu-id matches.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro
drm/msm/adreno: Use quirk identify hw_apriv
Rather than just open coding a list of gpu-id matches.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549764/
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f4f1c707 |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove redundant revn param
This just duplicates what is in adreno_info, and can cause confusion if used before it is set.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed
drm/msm/adreno: Remove redundant revn param
This just duplicates what is in adreno_info, and can cause confusion if used before it is set.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549761/
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6391030d |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove redundant gmem size param
Even in the ocmem case, the allocated ocmem buffer size should match the requested size.
v2: Move stray hunk to previous patch, make OCMEM size mism
drm/msm/adreno: Remove redundant gmem size param
Even in the ocmem case, the allocated ocmem buffer size should match the requested size.
v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549759/
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832ee64d |
| 27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove GPU name
No real need to have marketing names in the kernel.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-
drm/msm/adreno: Remove GPU name
No real need to have marketing names in the kernel.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549757/
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Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38 |
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317ab1b9 |
| 04-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a690: Remove revn and name
These fields are deprecated. But any userspace new enough to support a690 also knows how to identify the GPU based on chip-id.
Signed-off-by: Rob Clark <robdclar
drm/msm/a690: Remove revn and name
These fields are deprecated. But any userspace new enough to support a690 also knows how to identify the GPU based on chip-id.
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545552/
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71643600 |
| 04-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Fix warn splat for devices without revn
Recently, a WARN_ON() was introduced to ensure that revn is filled before adreno_is_aXYZ is called. This however doesn't work very well when r
drm/msm/adreno: Fix warn splat for devices without revn
Recently, a WARN_ON() was introduced to ensure that revn is filled before adreno_is_aXYZ is called. This however doesn't work very well when revn is 0 by design (such as for A635).
Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before being set") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Patchwork: https://patchwork.freedesktop.org/patch/545554/
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Revision tags: v6.1.37, v6.1.36, v6.4, v6.1.35 |
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b3bcd583 |
| 15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching
Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improveme
drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching
Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542777/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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e7fc9398 |
| 15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A610 support
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that i
drm/msm/a6xx: Add A610 support
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again.
This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever.
Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542779/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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8296ff0a |
| 15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add support for A619_holi
A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Ad
drm/msm/a6xx: Add support for A619_holi
A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542775/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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5a903a44 |
| 15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Introduce GMU wrapper support
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directl
drm/msm/a6xx: Introduce GMU wrapper support
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels).
This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542766/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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87cc0d0a |
| 15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Use adreno_is_revn for A690
The adreno_is_revn rework came at the same time as A690 introduction and that resulted in it not covering all cases. Fix it.
Signed-off-by: Konrad Dybcio
drm/msm/adreno: Use adreno_is_revn for A690
The adreno_is_revn rework came at the same time as A690 introduction and that resulted in it not covering all cases. Fix it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542754/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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Revision tags: v6.1.34 |
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b263325b |
| 12-Jun-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: make adreno_is_a690()'s argument const
Change adreno_is_a690() prototype to accept the const struct adreno_gpu pointer instead of a non-const one. This fixes the following warning:
drm/msm/adreno: make adreno_is_a690()'s argument const
Change adreno_is_a690() prototype to accept the const struct adreno_gpu pointer instead of a non-const one. This fixes the following warning:
In file included from drivers/gpu/drm/msm/msm_drv.c:33: drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’: drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
Fixes: 1b90e8f8879c ("drm/msm/adreno: change adreno_is_* functions to accept const argument") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/542138/ Link: https://lore.kernel.org/r/20230612182527.3345786-1-dmitry.baryshkov@linaro.org
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Revision tags: v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24 |
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1b90e8f8 |
| 11-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: change adreno_is_* functions to accept const argument
All adreno_is_*() functions do not modify their argument in any way, so they can be changed to accept const struct adreno_gpu po
drm/msm/adreno: change adreno_is_* functions to accept const argument
All adreno_is_*() functions do not modify their argument in any way, so they can be changed to accept const struct adreno_gpu pointer.
Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/531706/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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cc943f43 |
| 11-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: warn if chip revn is verified before being set
The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno 510") tried to check GPU's revn before revn being set. Add WAR
drm/msm/adreno: warn if chip revn is verified before being set
The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE to prevent such bugs from happening again. A separate helper is necessary so that the warning is displayed really just once instead of being displayed for each of comparisons.
Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/531705/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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5e7665b5 |
| 30-May-2023 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
drm/msm/adreno: Add Adreno A690 support
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@l
drm/msm/adreno: Add Adreno A690 support
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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Revision tags: v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12 |
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f62ad0f6 |
| 14-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: split a6xx fault handler into generic and a6xx parts
Split the a6xx_fault_handler() into the generic adreno_fault_handler() and platform-specific parts. The adreno_fault_handler() ca
drm/msm/adreno: split a6xx fault handler into generic and a6xx parts
Split the a6xx_fault_handler() into the generic adreno_fault_handler() and platform-specific parts. The adreno_fault_handler() can further be used by a5xx and hopefully by a4xx (at some point).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522722/ Link: https://lore.kernel.org/r/20230214123504.3729522-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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Revision tags: v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17 |
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13ef096e |
| 02-Jan-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Make adreno quirks not overwrite each other
So far the adreno quirks have all been assigned with an OR operator, which is problematic, because they were assigned consecutive integer
drm/msm/adreno: Make adreno quirks not overwrite each other
So far the adreno quirks have all been assigned with an OR operator, which is problematic, because they were assigned consecutive integer values, which makes checking them with an AND operator kind of no bueno..
Switch to using BIT(n) so that only the quirks that the programmer chose are taken into account when evaluating info->quirks & ADRENO_QUIRK_...
Fixes: 370063ee427a ("drm/msm/adreno: Add A540 support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/516456/ Link: https://lore.kernel.org/r/20230102100201.77286-1-konrad.dybcio@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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