47 	int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 	int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 	int (*hw_init)(struct msm_gpu *gpu);
56 	int (*ucode_load)(struct msm_gpu *gpu);
58 	int (*pm_suspend)(struct msm_gpu *gpu);
59 	int (*pm_resume)(struct msm_gpu *gpu);
60 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
61 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
63 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 	void (*recover)(struct msm_gpu *gpu);
65 	void (*destroy)(struct msm_gpu *gpu);
68 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
71 	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
74 	u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
75 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
77 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
79 	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
82 		(struct msm_gpu *gpu, struct platform_device *pdev);
84 		(struct msm_gpu *gpu);
85 	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
94 	bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
318 static inline bool msm_gpu_active(struct msm_gpu *gpu)  in msm_gpu_active()  argument
322 	for (i = 0; i < gpu->nr_rings; i++) {  in msm_gpu_active()
323 		struct msm_ringbuffer *ring = gpu->rb[i];  in msm_gpu_active()
458 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,  in msm_gpu_convert_priority()  argument
470 	if (rn >= gpu->nr_rings)  in msm_gpu_convert_priority()
556 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)  in gpu_write()  argument
558 	msm_writel(data, gpu->mmio + (reg << 2));  in gpu_write()
561 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)  in gpu_read()  argument
563 	return msm_readl(gpu->mmio + (reg << 2));  in gpu_read()
566 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)  in gpu_rmw()  argument
568 	msm_rmw(gpu->mmio + (reg << 2), mask, or);  in gpu_rmw()
571 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)  in gpu_read64()  argument
589 	val = (u64) msm_readl(gpu->mmio + (reg << 2));  in gpu_read64()
590 	val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);  in gpu_read64()
595 static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)  in gpu_write64()  argument
598 	msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));  in gpu_write64()
599 	msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));  in gpu_write64()
602 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
603 int msm_gpu_pm_resume(struct msm_gpu *gpu);
605 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
622 				 struct msm_gpu *gpu, int sysprof);
637 void msm_devfreq_init(struct msm_gpu *gpu);
638 void msm_devfreq_cleanup(struct msm_gpu *gpu);
639 void msm_devfreq_resume(struct msm_gpu *gpu);
640 void msm_devfreq_suspend(struct msm_gpu *gpu);
641 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
642 void msm_devfreq_active(struct msm_gpu *gpu);
643 void msm_devfreq_idle(struct msm_gpu *gpu);
645 int msm_gpu_hw_init(struct msm_gpu *gpu);
647 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
648 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
649 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
652 void msm_gpu_retire(struct msm_gpu *gpu);
653 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
656 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
660 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
662 void msm_gpu_cleanup(struct msm_gpu *gpu);
674 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)  in msm_gpu_crashstate_get()  argument
678 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_get()
680 	if (gpu->crashstate) {  in msm_gpu_crashstate_get()
681 		kref_get(&gpu->crashstate->ref);  in msm_gpu_crashstate_get()
682 		state = gpu->crashstate;  in msm_gpu_crashstate_get()
685 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_get()
690 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)  in msm_gpu_crashstate_put()  argument
692 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_put()
694 	if (gpu->crashstate) {  in msm_gpu_crashstate_put()
695 		if (gpu->funcs->gpu_state_put(gpu->crashstate))  in msm_gpu_crashstate_put()
696 			gpu->crashstate = NULL;  in msm_gpu_crashstate_put()
699 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_put()
706 #define check_apriv(gpu, flags) \  argument
707 	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))