Home
last modified time | relevance | path

Searched +full:zynq +full:- +full:can +full:- +full:1 (Results 1 – 25 of 84) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx Axi CAN/Zynq CANPS controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
[all …]
H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
[all …]
/openbmc/u-boot/doc/
H A DREADME.zynq1 # SPDX-License-Identifier: GPL-2.0+
3 # Xilinx ZYNQ U-Boot
7 1. About this
9 This document describes the information about Xilinx Zynq U-Boot -
12 2. Zynq boards
14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
18 * zc702 (single qspi, gem0, mmc) [1]
23 - zc770-xm010 (single qspi, gem0, mmc)
24 - zc770-xm011 (8 or 16 bit nand)
25 - zc770-xm012 (nor)
[all …]
/openbmc/u-boot/board/xilinx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 string "Zynq/ZynqMP PS init file(s) location"
10 On Zynq and ZynqMP U-Boot SPL (or U-Boot proper if
14 psu_init_gpl.c on ZynqMP, ps7_init_gpl.c for Zynq-7000)
17 U-Boot contains PS init files for some boards, but each of
19 different board, or needing a different configuration, can
22 There are three ways to give a PS init file to U-Boot:
24 1. Set this variable to the path, either relative to the
26 ps7_init_gpl.c file is located. U-Boot will build this
29 2. If you leave an empty string here, U-Boot will use
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
16 communication. Xilinx provides a standard IP core that can be used to access the
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynq-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
21 parameters, such as pull-up, slew rate, etc.
[all …]
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c2 * Xilinx Zynq Baseboard System emulation.
9 * This program is free software; you can redistribute it and/or
28 #include "hw/adc/zynq-xadc.h"
31 #include "qemu/error-report.h"
36 #include "hw/qdev-clock.h"
41 #include "target/arm/cpu-qom.h"
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup()
125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init()
141 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; in zynq_init_spi_flashes()
[all …]
/openbmc/linux/arch/arm/mach-zynq/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk/zynq.h>
24 #include <linux/irqchip/arm-gic.h>
32 #include <asm/mach-types.h>
36 #include <asm/hardware/cache-l2x0.h>
47 * zynq_memory_init - Initialize special memory
49 * We need to stop things allocating the low memory as DMA can't work in
50 * the 1st 512K of memory.
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
[all …]
H A Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
13 #include <linux/clk/zynq.h>
34 * zynq_slcr_write - Write to a register in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
72 * zynq_slcr_get_device_id - Read device code id
88 * zynq_slcr_system_restart - Restart the entire system.
104 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
109 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); in zynq_slcr_system_restart()
[all …]
/openbmc/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
31 Enable the Altera SPI driver. This driver can be used to
40 Enable the Aspeed AST2500 FMC/SPI driver. This driver can be
54 Enable the Andestech ATCSPI200 SPI driver. This driver can be
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
72 many AT91 (ARM) chips. This driver can be used to access
79 Enable the BCM6328 HSSPI driver. This driver can be used to
87 Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
94 Enable the Broadcom set-top box SPI driver. This driver can
[all …]
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq PS SPI controller driver (master mode only)
17 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
23 #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
39 /* zynq spi register set */
53 /* zynq spi platform data */
62 /* zynq spi priv */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
[all …]
H A Dzynq_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
17 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
26 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
34 /* zynq qspi Transmit Data Register */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
40 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Darm-xilinx-zynq-a9-machine.c6 * This library is free software; you can redistribute it and/or
22 #include "libqos-malloc.h"
42 return &machine->alloc; in xilinx_zynq_a9_get_driver()
45 fprintf(stderr, "%s not present in arm/xilinx-zynq-a9\n", interface); in xilinx_zynq_a9_get_driver()
52 if (!g_strcmp0(device, "generic-sdhci")) { in xilinx_zynq_a9_get_device()
53 return &machine->sdhci.obj; in xilinx_zynq_a9_get_device()
56 fprintf(stderr, "%s not present in arm/xilinx-zynq-a9\n", device); in xilinx_zynq_a9_get_device()
63 alloc_destroy(&machine->alloc); in xilinx_zynq_a9_destructor()
68 QXilinxZynqA9Machine *machine = g_new0(QXilinxZynqA9Machine, 1); in qos_create_machine_arm_xilinx_zynq_a9()
70 alloc_init(&machine->alloc, 0, in qos_create_machine_arm_xilinx_zynq_a9()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/openbmc/u-boot/drivers/net/
H A DKconfig11 This is currently implemented in net/eth-uclass.c
43 bool "Altera Triple-Speed Ethernet MAC support"
47 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
48 Please find details on the "Triple-Speed Ethernet MegaCore Function
133 used on devices with SPI support you can reprogram the EEPROM from
134 U-Boot.
152 in U-Boot to the RAW AF_PACKET API in Linux. This allows real
162 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
209 Ethernet controller that can be found on Aspeed SoCs (which
217 and integrates a link list DMA engine with direct M-Bus
[all …]
/openbmc/linux/Documentation/networking/device_drivers/can/ctu/
H A Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 CTU CAN FD Driver
9 About CTU CAN FD IP Core
10 ------------------------
12 `CTU CAN FD <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
18 The SocketCAN driver for Xilinx Zynq SoC based MicroZed board
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
[all …]
/openbmc/qemu/hw/adc/
H A Dzynq-xadc.c2 * ADC registers for Xilinx Zynq Platform
7 * This program is free software; you can redistribute it and/or
18 #include "hw/adc/zynq-xadc.h"
44 #define CFG_TCKRATE_DIV(x) (0x1 << (x - 1))
54 #define INT_ALM_MASK (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
82 s->regs[INT_STS] |= INT_CFIFO_LTH; in zynq_xadc_update_ints()
84 if (s->xadc_dfifo_entries > in zynq_xadc_update_ints()
85 extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) { in zynq_xadc_update_ints()
86 s->regs[INT_STS] |= INT_DFIFO_GTH; in zynq_xadc_update_ints()
89 qemu_set_irq(s->irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK])); in zynq_xadc_update_ints()
[all …]
/openbmc/u-boot/tools/
H A Dzynqimage.c1 // SPDX-License-Identifier: GPL-2.0+
7 * * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3)
8 * * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8)
11 * Forced as 'little' endian, 32-bit words
13 * 0x 0 - Interrupt Table (8 words)
15 * 0x 1f
16 * 0x 20 - Width Detection
18 * 0x 24 - Image Identifier
20 * 0x 28 - Encryption
21 * * 0x00000000 - None
[all …]
/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER 1
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
[all …]
/openbmc/u-boot/board/xilinx/zynq/
H A Dcmds.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <u-boot/md5.h>
12 #include <u-boot/rsa.h>
13 #include <u-boot/rsa-mod-exp.h>
14 #include <u-boot/sha256.h>
37 #define ZYNQ_RSA_PART_OWNER_UBOOT 1
47 u32 n0inv; /* -1 / modulus[0] mod 2^32 */
72 ppkptr += (ZYNQ_RSA_ALIGN_PPK_START - padsize); in zynq_extract_ppk()
85 * Calculate the inverse(-1 / modulus[0] mod 2^32 ) for the PPK
90 u32 tmp = BIT(1); in zynq_calc_inv()
[all …]
/openbmc/linux/drivers/clk/zynq/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
35 #define PLLCTRL_BPQUAL_MASK (1 << 3)
37 #define PLLCTRL_PWRDWN_SHIFT 1
38 #define PLLCTRL_RESET_MASK 1
45 * zynq_pll_round_rate() - Round a clock frequency
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig9 This option, if enabled, provides more flexible and linux-like
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
51 Sector size, in bytes, can be 512 or 1024.
101 GPMC controller is used for parallel NAND flash devices, and can
120 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
153 bool "24-error correction (45 ECC bytes)"
156 bool "32-error correction (60 ECC bytes)"
178 ---help---
245 bool "Support for Zynq Nand controller"
250 found on Zynq SoC.
[all …]
/openbmc/u-boot/drivers/gpio/
H A DKconfig15 is defined in include/asm-generic/gpio.h.
24 is a mechanism providing automatic GPIO request and config-
25 uration as part of the gpio-controller's driver probe function.
34 is a mechanism providing automatic GPIO request and config-
35 uration as part of the gpio-controller's driver probe function.
64 lines. Each I/O line may be dedicated as a general-purpose
68 responsible for the general-purpose I/O.
98 95 GPIOs which can be configured from the device tree.
149 - APQ8016
150 - MSM8916
[all …]

1234