clk/zynq/pll.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Zynq PLL driver
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15  * struct zynq_pll - pll clock
16  * @hw:		Handle between common and hardware-specific interfaces
35 #define PLLCTRL_BPQUAL_MASK	(1 << 3)
37 #define PLLCTRL_PWRDWN_SHIFT	1
38 #define PLLCTRL_RESET_MASK	1
45  * zynq_pll_round_rate() - Round a clock frequency
46  * @hw:		Handle between common and hardware-specific interfaces
49  * Return:	frequency closest to @rate the hardware can generate.
66  * zynq_pll_recalc_rate() - Recalculate clock frequency
67  * @hw:			Handle between common and hardware-specific interfaces
81 	fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>  in zynq_pll_recalc_rate()
88  * zynq_pll_is_enabled - Check if a clock is enabled
89  * @hw:		Handle between common and hardware-specific interfaces
90  * Return:	1 if the clock is enabled, 0 otherwise.
101 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_is_enabled()
103 	reg = readl(clk->pll_ctrl);  in zynq_pll_is_enabled()
105 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_is_enabled()
111  * zynq_pll_enable - Enable clock
112  * @hw:		Handle between common and hardware-specific interfaces
127 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_enable()
129 	reg = readl(clk->pll_ctrl);  in zynq_pll_enable()
131 	writel(reg, clk->pll_ctrl);  in zynq_pll_enable()
132 	while (!(readl(clk->pll_status) & (1 << clk->lockbit)))  in zynq_pll_enable()
135 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_enable()
141  * zynq_pll_disable - Disable clock
142  * @hw:		Handle between common and hardware-specific interfaces
157 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_disable()
159 	reg = readl(clk->pll_ctrl);  in zynq_pll_disable()
161 	writel(reg, clk->pll_ctrl);  in zynq_pll_disable()
163 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_disable()
175  * clk_register_zynq_pll() - Register PLL with the clock framework
191 	const char *parent_arr[1] = {parent};  in clk_register_zynq_pll()
197 		.num_parents = 1,  in clk_register_zynq_pll()
203 		return ERR_PTR(-ENOMEM);  in clk_register_zynq_pll()
206 	pll->hw.init = &initd;  in clk_register_zynq_pll()
207 	pll->pll_ctrl = pll_ctrl;  in clk_register_zynq_pll()
208 	pll->pll_status = pll_status;  in clk_register_zynq_pll()
209 	pll->lockbit = lock_index;  in clk_register_zynq_pll()
210 	pll->lock = lock;  in clk_register_zynq_pll()
212 	spin_lock_irqsave(pll->lock, flags);  in clk_register_zynq_pll()
214 	reg = readl(pll->pll_ctrl);  in clk_register_zynq_pll()
216 	writel(reg, pll->pll_ctrl);  in clk_register_zynq_pll()
218 	spin_unlock_irqrestore(pll->lock, flags);  in clk_register_zynq_pll()
220 	clk = clk_register(NULL, &pll->hw);  in clk_register_zynq_pll()