1 // SPDX-License-Identifier: GPL-2.0+
7  *   * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3)
8  *   * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8)
11  * Forced as 'little' endian, 32-bit words
13  *  0x  0 - Interrupt Table (8 words)
15  *  0x 1f
16  *  0x 20 - Width Detection
18  *  0x 24 - Image Identifier
20  *  0x 28 - Encryption
21  *         * 0x00000000 - None
22  *         * 0xa5c3c5a3 - eFuse
23  *         * 0x3a5c3c5a - bbRam
24  *  0x 2C - User Field
25  *  0x 30 - Image Offset
26  *  0x 34 - Image Size
27  *  0x 38 - Reserved (0x00000000) (according to spec)
29  *  0x 3C - Image Load
30  *  0x 40 - Image Stored Size
31  *  0x 44 - Reserved (0x00000000) (according to spec)
33  *  0x 48 - Checksum
34  *  0x 4c - Unused (21 words)
37  *  0x a0 - Register Initialization, 256 Address and Data word pairs
41  *  0x8a0 - Unused (8 words)
44  *  0x8c0 - Data/Image starts here or above
97 	checksum += le32_to_cpu(ptr->width_detection);  in zynqimage_checksum()
98 	checksum += le32_to_cpu(ptr->image_identifier);  in zynqimage_checksum()
99 	checksum += le32_to_cpu(ptr->encryption);  in zynqimage_checksum()
100 	checksum += le32_to_cpu(ptr->user_field);  in zynqimage_checksum()
101 	checksum += le32_to_cpu(ptr->image_offset);  in zynqimage_checksum()
102 	checksum += le32_to_cpu(ptr->image_size);  in zynqimage_checksum()
103 	checksum += le32_to_cpu(ptr->__reserved1);  in zynqimage_checksum()
104 	checksum += le32_to_cpu(ptr->image_load);  in zynqimage_checksum()
105 	checksum += le32_to_cpu(ptr->image_stored_size);  in zynqimage_checksum()
106 	checksum += le32_to_cpu(ptr->__reserved2);  in zynqimage_checksum()
119 	ptr->width_detection = HEADER_WIDTHDETECTION;  in zynqimage_default_header()
120 	ptr->image_identifier = HEADER_IMAGEIDENTIFIER;  in zynqimage_default_header()
121 	ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);  in zynqimage_default_header()
123 	/* Setup not-supported/constant/reserved fields */  in zynqimage_default_header()
125 		ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;  in zynqimage_default_header()
128 		ptr->register_init[i].address = HEADER_REGINIT_NULL;  in zynqimage_default_header()
129 		ptr->register_init[i].data = HEADER_REGINIT_NULL;  in zynqimage_default_header()
136 	ptr->__reserved1 = 0x0;  in zynqimage_default_header()
137 	ptr->__reserved2 = 0x0;  in zynqimage_default_header()
147 		return -1;  in zynqimage_verify_header()
149 	if (zynqhdr->__reserved1 != 0)  in zynqimage_verify_header()
150 		return -1;  in zynqimage_verify_header()
152 	if (zynqhdr->__reserved2 != 0)  in zynqimage_verify_header()
153 		return -1;  in zynqimage_verify_header()
155 	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)  in zynqimage_verify_header()
156 		return -1;  in zynqimage_verify_header()
157 	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)  in zynqimage_verify_header()
158 		return -1;  in zynqimage_verify_header()
160 	if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum)  in zynqimage_verify_header()
161 		return -1;  in zynqimage_verify_header()
171 	printf("Image Type   : Xilinx Zynq Boot Image support\n");  in zynqimage_print_header()
172 	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));  in zynqimage_print_header()
174 	       (unsigned long)le32_to_cpu(zynqhdr->image_size),  in zynqimage_print_header()
175 	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));  in zynqimage_print_header()
176 	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));  in zynqimage_print_header()
177 	printf("User Field   : 0x%08x\n", le32_to_cpu(zynqhdr->user_field));  in zynqimage_print_header()
178 	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));  in zynqimage_print_header()
181 		if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)  in zynqimage_print_header()
185 		       le32_to_cpu(zynqhdr->interrupt_vectors[i]));  in zynqimage_print_header()
189 		if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)  in zynqimage_print_header()
195 		printf("    @ 0x%08x -> 0x%08x\n",  in zynqimage_print_header()
196 		       le32_to_cpu(zynqhdr->register_init[i].address),  in zynqimage_print_header()
197 		       le32_to_cpu(zynqhdr->register_init[i].data));  in zynqimage_print_header()
206 	if (params->addr != 0x0) {  in zynqimage_check_params()
208 		return -1;  in zynqimage_check_params()
214 	if (params->eflag && (params->ep % 64 != 0)) {  in zynqimage_check_params()
216 			"Error: Entry Point must be aligned to a 64-byte boundary.\n");  in zynqimage_check_params()
217 		return -1;  in zynqimage_check_params()
220 	return !(params->lflag || params->dflag);  in zynqimage_check_params()
239 	/* Expect a table of register-value pairs, e.g. "0x12345678 0x4321" */  in zynqimage_parse_initparams()
243 		exit(1);  in zynqimage_parse_initparams()
260 			zynqhdr->register_init[reg_count] = reginit;  in zynqimage_parse_initparams()
275 	zynqhdr->image_offset =  in zynqimage_set_header()
277 	zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size);  in zynqimage_set_header()
278 	zynqhdr->image_stored_size = zynqhdr->image_size;  in zynqimage_set_header()
279 	zynqhdr->image_load = 0x0;  in zynqimage_set_header()
280 	if (params->eflag)  in zynqimage_set_header()
281 		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);  in zynqimage_set_header()
283 	/* User can pass in text file with init list */  in zynqimage_set_header()
284 	if (strlen(params->imagename2))  in zynqimage_set_header()
285 		zynqimage_parse_initparams(zynqhdr, params->imagename2);  in zynqimage_set_header()
287 	zynqhdr->checksum = zynqimage_checksum(zynqhdr);  in zynqimage_set_header()
292 	"Xilinx Zynq Boot Image support",