2  * ADC registers for Xilinx Zynq Platform
7  * This program is free software; you can redistribute it and/or
18 #include "hw/adc/zynq-xadc.h"
44 #define CFG_TCKRATE_DIV(x)      (0x1 << (x - 1))
54 #define INT_ALM_MASK            (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
82     s->regs[INT_STS] |= INT_CFIFO_LTH;  in zynq_xadc_update_ints()
84     if (s->xadc_dfifo_entries >  in zynq_xadc_update_ints()
85         extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) {  in zynq_xadc_update_ints()
86         s->regs[INT_STS] |= INT_DFIFO_GTH;  in zynq_xadc_update_ints()
89     qemu_set_irq(s->irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));  in zynq_xadc_update_ints()
96     s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT |  in zynq_xadc_reset()
98     s->regs[INT_STS] = INT_CFIFO_LTH;  in zynq_xadc_reset()
99     s->regs[INT_MASK] = 0xffffffff;  in zynq_xadc_reset()
100     s->regs[CMDFIFO] = 0;  in zynq_xadc_reset()
101     s->regs[RDFIFO] = 0;  in zynq_xadc_reset()
102     s->regs[MCTL] = MCTL_RESET;  in zynq_xadc_reset()
104     memset(s->xadc_regs, 0, sizeof(s->xadc_regs));  in zynq_xadc_reset()
105     memset(s->xadc_dfifo, 0, sizeof(s->xadc_dfifo));  in zynq_xadc_reset()
106     s->xadc_dfifo_entries = 0;  in zynq_xadc_reset()
113     uint16_t rv = s->xadc_dfifo[0];  in xadc_pop_dfifo()
116     if (s->xadc_dfifo_entries > 0) {  in xadc_pop_dfifo()
117         s->xadc_dfifo_entries--;  in xadc_pop_dfifo()
119     for (i = 0; i < s->xadc_dfifo_entries; i++) {  in xadc_pop_dfifo()
120         s->xadc_dfifo[i] = s->xadc_dfifo[i + 1];  in xadc_pop_dfifo()
122     s->xadc_dfifo[s->xadc_dfifo_entries] = 0;  in xadc_pop_dfifo()
129     if (s->xadc_dfifo_entries < ZYNQ_XADC_FIFO_DEPTH) {  in xadc_push_dfifo()
130         s->xadc_dfifo[s->xadc_dfifo_entries++] = s->xadc_read_reg_previous;  in xadc_push_dfifo()
132     s->xadc_read_reg_previous = regval;  in xadc_push_dfifo()
171         rv = s->regs[reg];  in zynq_xadc_read()
175         rv |= s->xadc_dfifo_entries << MSTS_DFIFO_LVL_SHIFT;  in zynq_xadc_read()
176         if (!s->xadc_dfifo_entries) {  in zynq_xadc_read()
178         } else if (s->xadc_dfifo_entries == ZYNQ_XADC_FIFO_DEPTH) {  in zynq_xadc_read()
206         s->regs[CFG] = val;  in zynq_xadc_write()
209         s->regs[INT_STS] &= ~val;  in zynq_xadc_write()
212         s->regs[INT_MASK] = val & INT_ALL;  in zynq_xadc_write()
219         if (s->regs[MCTL] & MCTL_RESET) {  in zynq_xadc_write()
234             xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);  in zynq_xadc_write()
237             s->xadc_regs[xadc_reg] = xadc_data;  in zynq_xadc_write()
245         s->regs[MCTL] = val & 0x00fffeff;  in zynq_xadc_write()
262     memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",  in zynq_xadc_init()
264     sysbus_init_mmio(sbd, &s->iomem);  in zynq_xadc_init()
265     sysbus_init_irq(sbd, &s->irq);  in zynq_xadc_init()
269     .name = "zynq-xadc",
270     .version_id = 1,
271     .minimum_version_id = 1,
288     dc->vmsd = &vmstate_zynq_xadc;  in zynq_xadc_class_init()