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/openbmc/u-boot/drivers/mtd/spi/
H A DKconfig1 menu "SPI Flash Support"
4 bool "Enable Driver Model for SPI flash"
7 Enable driver model for SPI flash. This SPI flash interface
9 implemented by the SPI flash uclass. There is one standard
10 SPI flash driver which knows how to probe most chips
11 supported by U-Boot. The uclass interface is defined in
14 during the transition parent. SPI and SPI flash must be
19 bool "Support sandbox SPI flash device"
23 provided instead. Drivers can be connected up to the sandbox SPI
24 bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
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H A Dsf_probe.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SPI flash probing
14 #include <spi.h>
20 * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
22 * @flashp: Pointer to place to put flash info, which may be NULL if the
25 static int spi_flash_probe_slave(struct spi_flash *flash) in spi_flash_probe_slave() argument
27 struct spi_slave *spi = flash->spi; in spi_flash_probe_slave() local
31 if (!spi) { in spi_flash_probe_slave()
33 return -ENODEV; in spi_flash_probe_slave()
36 /* Claim spi bus */ in spi_flash_probe_slave()
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/openbmc/u-boot/drivers/spi/
H A DKconfig1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
16 typically use driver-private data instead of extending the
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
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/openbmc/u-boot/arch/x86/include/asm/
H A Dmrccache.h1 /* SPDX-License-Identifier: GPL-2.0+ */
33 * mrccache_find_current() - find the latest MRC cache record
38 * @entry: Position and size of MRC cache in SPI flash
44 * mrccache_update() - update the MRC cache with a new record
49 * @sf: SPI flash to write to
50 * @entry: Position and size of MRC cache in SPI flash
52 * @return 0 if updated, -EEXIST if the record is the same as the latest
53 * record, -EINVAL if the record is not valid, other error if SPI write failed
59 * mrccache_reserve() - reserve MRC data on the stack
61 * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
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/openbmc/u-boot/doc/SPI/
H A Dstatus.txt1 Status on SPI subsystem:
4 SPI COMMAND (common/cmd_sf, cmd_spi):
5 -
7 SPI FLASH (drivers/mtd/spi):
8 - sf_probe.c: SPI flash probing code.
9 - sf_ops.c: SPI flash operations code.
10 - sf.c: SPI flash interface, which interacts controller driver.
11 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
12 - Added memory_mapped support for read operations.
13 - Common probe support for all supported flash vendors except, ramtron.
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H A DREADME.ti_qspi_flash1 QSPI U-Boot support
2 ------------------
4 Host processor is connected to serial flash device via qpsi
5 interface. QSPI is a kind of spi module that allows single,
6 dual and quad read access to external spi devices. The module
8 for accessing data form external spi devices.
11 from Quad SPI flash devices.
14 -------
16 MLO/u-boot.img will be flashed from SD/MMC to the flash device
17 using serial flash erase and write commands. Then, switch settings
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H A DREADME.sandbox-spi1 Sandbox SPI/SPI Flash Implementation
4 U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled
5 using the --spi_sf paramter when starting U-Boot.
11 $ ./sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin
15 SPI bus number (typically 0)
16 SPI chip select number (typically 0)
17 SPI chip to emulate
21 U-Boot it started you can use 'sf' commands as normal. For example:
23 $ ./b/sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin \
24 -c "sf probe; sf test 0 100000; sf read 0 1000 1000; \
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600-gb200nvl-bmc-nvidia.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
66 pinctrl-names = "default";
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H A Dast2600-bletchley.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
35 clock-frequency = <800000000>;
38 clock-frequency = <800000000>;
44 u-boot,dm-pre-reloc;
49 clock-frequency = <400000000>;
66 pinctrl-names = "default";
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H A Dfsl-ls2080a-qds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 /dts-v1/;
10 #include "fsl-ls2080a.dtsi"
14 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
23 bus-num = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "spi-flash";
30 spi-max-frequency = <3000000>;
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H A Dfsl-ls1046a-qds.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /include/ "fsl-ls1046a.dtsi"
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "spi-flash";
28 spi-max-frequency = <1000000>; /* input clock */
29 spi-cpol;
30 spi-cpha;
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H A Dast2600-slt.dts1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
12 stdout-path = &uart5;
30 clock-frequency = <800000000>;
33 clock-frequency = <800000000>;
39 u-boot,dm-pre-reloc;
44 clock-frequency = <400000000>;
48 u-boot,dm-pre-reloc;
53 u-boot,dm-pre-reloc;
58 u-boot,dm-pre-reloc;
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H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
8 /dts-v1/;
10 #include "fsl-ls1088a.dtsi"
14 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
22 #address-cells = <2>;
23 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "cfi-flash";
35 bank-width = <2>;
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H A Dast2400-evb.dts1 /dts-v1/;
3 #include "ast2400-u-boot.dtsi"
7 compatible = "aspeed,ast2400-evb", "aspeed,ast2400";
15 stdout-path = &uart5;
27 u-boot,dm-pre-reloc;
32 clock-frequency = <200000000>;
36 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
47 phy-mode = "rgmii";
49 pinctrl-names = "default";
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H A Dast2600-pfr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
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H A Dast2600-intel.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <1200000000>;
37 clock-frequency = <1200000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
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/openbmc/u-boot/include/
H A Dspi_flash.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Common SPI flash Interface
14 #include <linux/mtd/spi-nor.h>
38 * get_sw_write_prot() - Check state of software write-protect feature
40 * SPI flash chips can lock a region of the flash defined by a
44 * @dev: SPI flash device
45 * @return 0 if no region is write-protected, 1 if a region is
46 * write-protected, -ENOSYS if the driver does not implement this,
47 * other -ve value on error
55 #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
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/openbmc/u-boot/test/py/tests/
H A Dtest_sf.py1 # SPDX-License-Identifier: GPL-2.0
12 which SPI Flash areas are available for testing. Without this, this test will
16 # A list of sections of Flash memory to be tested.
19 # Where in SPI Flash should the test operate.
26 # If set as a number, specifies the speed of the SPI Flash.
32 # If missing, the SPI Flash page size is used as a default (based on
36 # If present, specifies if the test can write to Flash offset
40 # If present, specifies the expected CRC32 value of the flash area.
48 """Check global state of the SPI Flash before running any test.
51 u_boot_console: A U-Boot console connection.
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/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/flash/phosphor-software-manager/
H A Dbios-update3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
5 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
6 source /usr/libexec/phosphor-state-manager/power-cmd
10 # SPI Get Link name
11 SPI_DEV=$(find /sys/bus/spi/devices/ -type l -exec sh -c 'readlink "$1" | grep -q "1e631000.spi" &&…
12 SPI_PATH="/sys/bus/spi/drivers/spi-nor"
17 # bmc-spi-mux-select-0: 1:BMC / 0:CPU
18 set_gpio bmc-spi-mux-select-0 1
25 # bmc-spi-mux-select-0: 1:BMC / 0:CPU
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/openbmc/u-boot/doc/
H A DREADME.at914 - I. Board mapping & boot media
5 - II. NAND partition table
6 - III. watchdog support
9 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
14 0x20000000 - 23FFFFFF SDRAM (64 MB)
15 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
16 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
20 U-Boot environment variables can be stored at different places:
21 - Dataflash on SPI chip select 1 (default)
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/openbmc/u-boot/common/spl/
H A Dspl_spi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <spi.h>
25 struct spi_flash *flash, in spi_load_image_os() argument
31 spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), in spi_load_image_os()
35 return -1; in spi_load_image_os()
41 spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, in spi_load_image_os()
42 spl_image->size, (void *)spl_image->load_addr); in spi_load_image_os()
45 spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, in spi_load_image_os()
56 struct spi_flash *flash = load->dev; in spl_spi_fit_read() local
59 ret = spi_flash_read(flash, sector, count, buf); in spl_spi_fit_read()
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/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
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/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
7 2. Physical base address & size of mapped NOR Flash.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
11 Connected flash properties
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
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/openbmc/u-boot/env/
H A DKconfig20 while U-Boot is running, but once U-Boot exits it will not be
21 stored. U-Boot will therefore always start up with a default
31 - CONFIG_ENV_OFFSET:
32 - CONFIG_ENV_SIZE:
41 - CONFIG_ENV_EEPROM_IS_ON_I2C
42 define this, if you have I2C and SPI activated, and your
45 - CONFIG_I2C_ENV_EEPROM_BUS
74 bool "Environment in flash memory"
84 Define this if you have a flash device which you want to use for the
87 a) The environment occupies one whole flash sector, which is
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/openbmc/u-boot/drivers/mtd/
H A DKconfig11 flash, RAM and similar chips, often used for solid state file
15 bool "Enable parallel NOR flash support"
17 Enable support for parallel NOR flash.
26 bool "Enable CFI Flash driver"
28 The Common Flash Interface specification was developed by Intel,
29 AMD and other flash manufactures. It provides a universal method
30 for probing the capabilities of flash devices. If you wish to
31 support any device that is CFI-compliant, you need to enable this
36 bool "Enable Driver Model for CFI Flash driver"
39 The Common Flash Interface specification was developed by Intel,
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