| /openbmc/u-boot/drivers/mtd/spi/ |
| H A D | Kconfig | 1 menu "SPI Flash Support"
4 bool "Enable Driver Model for SPI flash"
7 Enable driver model for SPI flash. This SPI flash interface
9 implemented by the SPI flash uclass. There is one standard
10 SPI flash driver which knows how to probe most chips
11 supported by U-Boot. The uclass interface is defined in
14 during the transition parent. SPI and SPI flash must be
19 bool "Support sandbox SPI flash device"
23 provided instead. Drivers can be connected up to the sandbox SPI
24 bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
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| H A D | sf_probe.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * SPI flash probing
14 #include <spi.h>
20 * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
22 * @flashp: Pointer to place to put flash info, which may be NULL if the
25 static int spi_flash_probe_slave(struct spi_flash *flash) in spi_flash_probe_slave() argument
27 struct spi_slave *spi = flash->spi; in spi_flash_probe_slave() local
31 if (!spi) { in spi_flash_probe_slave()
33 return -ENODEV; in spi_flash_probe_slave()
36 /* Claim spi bus */ in spi_flash_probe_slave()
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
16 typically use driver-private data instead of extending the
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
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| H A D | aspeed_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * ASPEED AST2500 FMC/SPI Controller driver
5 * Copyright (c) 2015-2018, IBM Corporation.
13 #include <spi.h>
32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
35 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */
58 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */
59 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */
64 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */
65 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */
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| /openbmc/linux/drivers/mtd/devices/ |
| H A D | mchp48l640.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Microchip 48L640 64 Kb SPI Serial EERAM
23 #include <linux/spi/flash.h>
24 #include <linux/spi/spi.h>
33 struct spi_device *spi; member
60 static int mchp48l640_mkcmd(struct mchp48l640_flash *flash, u8 cmd, loff_t addr, char *buf) in mchp48l640_mkcmd() argument
69 static int mchp48l640_read_status(struct mchp48l640_flash *flash, int *status) in mchp48l640_read_status() argument
76 mutex_lock(&flash->lock); in mchp48l640_read_status()
77 ret = spi_write_then_read(flash->spi, &cmd[0], 1, &cmd[1], 1); in mchp48l640_read_status()
78 mutex_unlock(&flash->lock); in mchp48l640_read_status()
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| H A D | mchp23k256.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Driver for Microchip 23k256 SPI RAM chips
16 #include <linux/spi/flash.h>
17 #include <linux/spi/spi.h>
28 struct spi_device *spi; member
41 static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash, in mchp23k256_addr2cmd() argument
51 for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8) in mchp23k256_addr2cmd()
55 static int mchp23k256_cmdsz(struct mchp23k256_flash *flash) in mchp23k256_cmdsz() argument
57 return 1 + flash->caps->addr_width; in mchp23k256_cmdsz()
63 struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd); in mchp23k256_write() local
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| H A D | sst25l.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Driver for SST25L SPI Flash chips
24 #include <linux/spi/spi.h>
25 #include <linux/spi/flash.h>
47 struct spi_device *spi; member
67 static int sst25l_status(struct sst25l_flash *flash, int *status) in sst25l_status() argument
83 err = spi_sync(flash->spi, &m); in sst25l_status()
91 static int sst25l_write_enable(struct sst25l_flash *flash, int enable) in sst25l_write_enable() argument
97 err = spi_write(flash->spi, command, 1); in sst25l_write_enable()
102 err = spi_write(flash->spi, command, 1); in sst25l_write_enable()
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| /openbmc/linux/drivers/spi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | mrccache.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
33 * mrccache_find_current() - find the latest MRC cache record
38 * @entry: Position and size of MRC cache in SPI flash
44 * mrccache_update() - update the MRC cache with a new record
49 * @sf: SPI flash to write to
50 * @entry: Position and size of MRC cache in SPI flash
52 * @return 0 if updated, -EEXIST if the record is the same as the latest
53 * record, -EINVAL if the record is not valid, other error if SPI write failed
59 * mrccache_reserve() - reserve MRC data on the stack
61 * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-spi-devices-spi-nor | 1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
6 flash device.
8 The attribute is not present if the flash doesn't support
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
18 The attribute is not present if the flash device isn't
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| /openbmc/u-boot/include/ |
| H A D | spi_flash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Common SPI flash Interface
14 #include <linux/mtd/spi-nor.h>
38 * get_sw_write_prot() - Check state of software write-protect feature
40 * SPI flash chips can lock a region of the flash defined by a
44 * @dev: SPI flash device
45 * @return 0 if no region is write-protected, 1 if a region is
46 * write-protected, -ENOSYS if the driver does not implement this,
47 * other -ve value on error
55 #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nxp-spifi.txt | 1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
6 mode. In memory mode the Flash is accessible from the CPU as
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
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| H A D | jedec,spi-nor.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
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| /openbmc/u-boot/test/py/tests/ |
| H A D | test_sf.py | 1 # SPDX-License-Identifier: GPL-2.0
12 which SPI Flash areas are available for testing. Without this, this test will
16 # A list of sections of Flash memory to be tested.
19 # Where in SPI Flash should the test operate.
26 # If set as a number, specifies the speed of the SPI Flash.
32 # If missing, the SPI Flash page size is used as a default (based on
36 # If present, specifies if the test can write to Flash offset
40 # If present, specifies the expected CRC32 value of the flash area.
48 """Check global state of the SPI Flash before running any test.
51 u_boot_console: A U-Boot console connection.
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| /openbmc/u-boot/doc/SPI/ |
| H A D | status.txt | 1 Status on SPI subsystem:
4 SPI COMMAND (common/cmd_sf, cmd_spi):
5 -
7 SPI FLASH (drivers/mtd/spi):
8 - sf_probe.c: SPI flash probing code.
9 - sf_ops.c: SPI flash operations code.
10 - sf.c: SPI flash interface, which interacts controller driver.
11 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
12 - Added memory_mapped support for read operations.
13 - Common probe support for all supported flash vendors except, ramtron.
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| H A D | README.ti_qspi_flash | 1 QSPI U-Boot support
2 ------------------
4 Host processor is connected to serial flash device via qpsi
5 interface. QSPI is a kind of spi module that allows single,
6 dual and quad read access to external spi devices. The module
8 for accessing data form external spi devices.
11 from Quad SPI flash devices.
14 -------
16 MLO/u-boot.img will be flashed from SD/MMC to the flash device
17 using serial flash erase and write commands. Then, switch settings
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| /openbmc/linux/drivers/mtd/spi-nor/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Standard SPI NOR flash operations. */
155 /* Dual SPI */
161 /* Quad SPI */
167 /* Octal SPI */
180 /* Quad SPI */
185 /* Octal SPI */
195 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
201 * @opcode: the SPI command op code to erase the sector/block.
202 * @idx: Erase Type index as sorted in the Basic Flash Parameter
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SPI NOR device support"
8 This is the framework for the SPI NOR which can be used by the SPI
9 device drivers and the SPI NOR device driver.
17 Many flash memories support erasing small (4096 B) sectors. Depending
20 Changing a small part of the flash's contents is usually faster with
34 This option disables the software write protection on any SPI
35 flashes at boot-up.
37 Depending on the flash chip this either clears the block protection
41 of your SPI flash. This is only to keep backwards compatibility.
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | ast2600-bletchley.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
35 clock-frequency = <800000000>;
38 clock-frequency = <800000000>;
44 u-boot,dm-pre-reloc;
49 clock-frequency = <400000000>;
66 pinctrl-names = "default";
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| /openbmc/u-boot/doc/ |
| H A D | README.at91 | 4 - I. Board mapping & boot media
5 - II. NAND partition table
6 - III. watchdog support
9 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
14 0x20000000 - 23FFFFFF SDRAM (64 MB)
15 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
16 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
20 U-Boot environment variables can be stored at different places:
21 - Dataflash on SPI chip select 1 (default)
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| /openbmc/linux/Documentation/driver-api/mtd/ |
| H A D | spi-intel.rst | 2 Upgrading BIOS using spi-intel
5 Many Intel CPUs like Baytrail and Braswell include SPI serial flash host
7 Since contents of the SPI serial flash is crucial for machine to function,
11 Not all manufacturers protect the SPI serial flash, mainly because it
14 The spi-intel driver makes it possible to read and write the SPI serial
15 flash, if certain protection bits are not set and locked. If it finds
16 any of them set, the whole MTD device is made read-only to prevent
17 partial overwrites. By default the driver exposes SPI serial flash
18 contents as read-only but it can be changed from kernel command line,
21 Please keep in mind that overwriting the BIOS image on SPI serial flash
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| /openbmc/u-boot/env/ |
| H A D | Kconfig | 20 while U-Boot is running, but once U-Boot exits it will not be
21 stored. U-Boot will therefore always start up with a default
31 - CONFIG_ENV_OFFSET:
32 - CONFIG_ENV_SIZE:
41 - CONFIG_ENV_EEPROM_IS_ON_I2C
42 define this, if you have I2C and SPI activated, and your
45 - CONFIG_I2C_ENV_EEPROM_BUS
74 bool "Environment in flash memory"
84 Define this if you have a flash device which you want to use for the
87 a) The environment occupies one whole flash sector, which is
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| /openbmc/u-boot/common/spl/ |
| H A D | spl_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <spi.h>
25 struct spi_flash *flash, in spi_load_image_os() argument
31 spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), in spi_load_image_os()
35 return -1; in spi_load_image_os()
41 spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, in spi_load_image_os()
42 spl_image->size, (void *)spl_image->load_addr); in spi_load_image_os()
45 spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, in spi_load_image_os()
56 struct spi_flash *flash = load->dev; in spl_spi_fit_read() local
59 ret = spi_flash_read(flash, sector, count, buf); in spl_spi_fit_read()
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| /openbmc/u-boot/cmd/ |
| H A D | otp_info.h | 7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
37 { 2, 1, 0, "Disable Boot from debug SPI" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
105 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" },
106 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" },
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| /openbmc/u-boot/board/freescale/c29xpcie/ |
| H A D | README | 3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
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