Lines Matching +full:spi +full:- +full:flash
1 // SPDX-License-Identifier: GPL-2.0+
3 * ASPEED AST2500 FMC/SPI Controller driver
5 * Copyright (c) 2015-2018, IBM Corporation.
13 #include <spi.h>
32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
35 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */
58 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */
59 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */
64 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */
65 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */
66 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */
113 /* Auto Soft-Reset Command Control */
118 * and the end address of the AHB window of a SPI flash device.
121 * CE0 0x20000000 - 0x2fffffff 128MB
122 * CE1 0x28000000 - 0x29ffffff 32MB
123 * CE2 0x2a000000 - 0x2bffffff 32MB
126 * covered and CE0 start address and CE2 end addresses are read-only.
136 ((((start) & 0x0ff00000) >> 16) | (((end) - 0x100000) & 0xffff0000))
168 * flash related info
172 /* Initialized when the SPI bus is
183 struct spi_flash *spi; /* Associated SPI Flash device */ member
264 void __iomem *ahb_base; /* AHB Window for all flash devices */
274 u8 cmd_buf[16]; /* SPI command in progress */
278 struct aspeed_spi_flash *flash,
282 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash,
288 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); in aspeed_spi_get_flash()
289 u8 cs = slave_plat->cs; in aspeed_spi_get_flash()
291 if (cs >= priv->flash_count) { in aspeed_spi_get_flash()
296 return &priv->flashes[cs]; in aspeed_spi_get_flash()
301 u32 hclk_rate = priv->hclk_rate; in aspeed_g6_spi_hclk_divisor()
336 u32 hclk_rate = priv->hclk_rate; in aspeed_spi_hclk_divisor()
357 * Use some address/size under the first flash device CE0
360 struct aspeed_spi_flash *flash, in aspeed_spi_fmc_checksum() argument
363 u32 flash_addr = (u32)flash->ahb_base + 0x10000; in aspeed_spi_fmc_checksum()
367 writel(flash_addr, &priv->regs->dma_flash_addr); in aspeed_spi_fmc_checksum()
368 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len); in aspeed_spi_fmc_checksum()
371 * When doing calibration, the SPI clock rate in the CE0 in aspeed_spi_fmc_checksum()
378 writel(dma_ctrl, &priv->regs->dma_ctrl); in aspeed_spi_fmc_checksum()
379 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) in aspeed_spi_fmc_checksum()
382 writel(0x0, &priv->regs->intr_ctrl); in aspeed_spi_fmc_checksum()
384 checksum = readl(&priv->regs->dma_checksum); in aspeed_spi_fmc_checksum()
386 writel(0x0, &priv->regs->dma_ctrl); in aspeed_spi_fmc_checksum()
391 * Use some address/size under the first flash device CE0
394 struct aspeed_spi_flash *flash, in aspeed_g6_spi_fmc_checksum() argument
397 u32 flash_addr = (u32)flash->ahb_base; in aspeed_g6_spi_fmc_checksum()
401 writel(DMA_GET_REQ_MAGIC, &priv->regs->dma_ctrl); in aspeed_g6_spi_fmc_checksum()
402 if (readl(&priv->regs->dma_ctrl) & DAM_CTRL_REQUEST) { in aspeed_g6_spi_fmc_checksum()
403 while (!(readl(&priv->regs->dma_ctrl) & DAM_CTRL_GRANT)) in aspeed_g6_spi_fmc_checksum()
407 writel(flash_addr, &priv->regs->dma_flash_addr); in aspeed_g6_spi_fmc_checksum()
408 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len); in aspeed_g6_spi_fmc_checksum()
411 * When doing calibration, the SPI clock rate in the control in aspeed_g6_spi_fmc_checksum()
418 writel(dma_ctrl, &priv->regs->dma_ctrl); in aspeed_g6_spi_fmc_checksum()
419 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) in aspeed_g6_spi_fmc_checksum()
422 checksum = readl(&priv->regs->dma_checksum); in aspeed_g6_spi_fmc_checksum()
424 writel(0x0, &priv->regs->intr_ctrl); in aspeed_g6_spi_fmc_checksum()
425 writel(0x0, &priv->regs->dma_ctrl); in aspeed_g6_spi_fmc_checksum()
426 writel(DMA_DISCARD_REQ_MAGIC, &priv->regs->dma_ctrl); in aspeed_g6_spi_fmc_checksum()
432 struct aspeed_spi_flash *flash, in aspeed_spi_read_checksum() argument
435 if (priv->new_ver) in aspeed_spi_read_checksum()
436 return aspeed_g6_spi_fmc_checksum(priv, flash, div, delay); in aspeed_spi_read_checksum()
439 if (!priv->is_fmc) { in aspeed_spi_read_checksum()
440 pr_warn("No timing calibration support for SPI controllers"); in aspeed_spi_read_checksum()
444 return aspeed_spi_fmc_checksum(priv, flash, div, delay); in aspeed_spi_read_checksum()
452 * avoid calibriate umount spi-flash.
491 * In order to get a stable SPI read timing, in get_mid_point_of_longest_one()
496 return -1; in get_mid_point_of_longest_one()
502 struct aspeed_spi_flash *flash) in aspeed_spi_timing_calibration() argument
504 u32 cs = flash->cs; in aspeed_spi_timing_calibration()
513 u32 max_freq = flash->max_freq; in aspeed_spi_timing_calibration()
520 if (priv->new_ver) { in aspeed_spi_timing_calibration()
521 timing_reg = readl(&priv->regs->timings + cs); in aspeed_spi_timing_calibration()
529 reg_val = flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK; in aspeed_spi_timing_calibration()
530 writel(reg_val, &priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
533 return -ENOMEM; in aspeed_spi_timing_calibration()
535 memcpy_fromio(tmp_buf, flash->ahb_base, FLASH_CALIBRATION_LEN); in aspeed_spi_timing_calibration()
537 debug("flash data is monotonous, skip calibration.\n"); in aspeed_spi_timing_calibration()
542 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0); in aspeed_spi_timing_calibration()
552 return -ENOMEM; in aspeed_spi_timing_calibration()
556 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { in aspeed_spi_timing_calibration()
557 if (priv->hclk_rate / (i + 2) > max_freq) { in aspeed_spi_timing_calibration()
558 debug("skipping freq %ld\n", priv->hclk_rate / (i + 2)); in aspeed_spi_timing_calibration()
562 max_freq = (u32)priv->hclk_rate / (i + 2); in aspeed_spi_timing_calibration()
569 checksum = aspeed_g6_spi_fmc_checksum(priv, flash, in aspeed_spi_timing_calibration()
570 hclk_masks[3 - i], in aspeed_spi_timing_calibration()
590 writel(final_delay, &priv->regs->timings + cs); in aspeed_spi_timing_calibration()
596 /* configure SPI clock frequency */ in aspeed_spi_timing_calibration()
597 reg_val = readl(&priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
599 writel(reg_val, &priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
602 flash->ce_ctrl_user = in aspeed_spi_timing_calibration()
603 (flash->ce_ctrl_user & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()
604 flash->ce_ctrl_fread = in aspeed_spi_timing_calibration()
605 (flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()
617 timing_reg = readl(&priv->regs->timings); in aspeed_spi_timing_calibration()
622 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0); in aspeed_spi_timing_calibration()
625 u32 hdiv = 5 - i; in aspeed_spi_timing_calibration()
626 u32 hshift = (hdiv - 1) << 2; in aspeed_spi_timing_calibration()
630 if (priv->hclk_rate / hdiv > flash->max_freq) { in aspeed_spi_timing_calibration()
631 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); in aspeed_spi_timing_calibration()
639 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i], in aspeed_spi_timing_calibration()
651 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i], in aspeed_spi_timing_calibration()
669 writel(timing_reg, &priv->regs->timings); in aspeed_spi_timing_calibration()
680 * Enable write on all flash devices as USER command mode in aspeed_spi_controller_init()
683 setbits_le32(&priv->regs->conf, in aspeed_spi_controller_init()
688 * tuned after the SPI flash devices are probed. in aspeed_spi_controller_init()
690 if (priv->new_ver) { in aspeed_spi_controller_init()
691 for (cs = 0; cs < priv->flash_count; cs++) { in aspeed_spi_controller_init()
692 struct aspeed_spi_flash *flash = &priv->flashes[cs]; in aspeed_spi_controller_init() local
696 flash->ahb_base = priv->ahb_base; in aspeed_spi_controller_init()
697 debug("cs0 mem-map : %x\n", (u32)flash->ahb_base); in aspeed_spi_controller_init()
700 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000; /* cs0 + 64MB */ in aspeed_spi_controller_init()
701 debug("cs1 mem-map : %x end %x\n", in aspeed_spi_controller_init()
702 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); in aspeed_spi_controller_init()
705 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000 * 2; /* cs0 + 128MB : use 64MB */ in aspeed_spi_controller_init()
706 debug("cs2 mem-map : %x end %x\n", in aspeed_spi_controller_init()
707 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); in aspeed_spi_controller_init()
711 G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); in aspeed_spi_controller_init()
712 writel(addr_config, &priv->regs->segment_addr[cs]); in aspeed_spi_controller_init()
713 flash->cs = cs; in aspeed_spi_controller_init()
714 flash->ce_ctrl_user = CE_CTRL_USERMODE; in aspeed_spi_controller_init()
715 flash->ce_ctrl_fread = CE_CTRL_READMODE; in aspeed_spi_controller_init()
718 for (cs = 0; cs < priv->flash_count; cs++) { in aspeed_spi_controller_init()
719 struct aspeed_spi_flash *flash = &priv->flashes[cs]; in aspeed_spi_controller_init() local
720 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); in aspeed_spi_controller_init()
723 * read-only and is the same as the address of the in aspeed_spi_controller_init()
724 * overall AHB window of the controller for all flash in aspeed_spi_controller_init()
727 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : in aspeed_spi_controller_init()
728 priv->ahb_base; in aspeed_spi_controller_init()
730 flash->cs = cs; in aspeed_spi_controller_init()
731 flash->ce_ctrl_user = CE_CTRL_USERMODE; in aspeed_spi_controller_init()
732 flash->ce_ctrl_fread = CE_CTRL_READMODE; in aspeed_spi_controller_init()
746 len -= offset; in aspeed_spi_read_from_ahb()
761 len -= offset; in aspeed_spi_write_to_ahb()
769 struct aspeed_spi_flash *flash) in aspeed_spi_start_user() argument
771 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; in aspeed_spi_start_user()
774 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_start_user()
777 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); in aspeed_spi_start_user()
781 struct aspeed_spi_flash *flash) in aspeed_spi_stop_user() argument
784 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); in aspeed_spi_stop_user()
787 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_stop_user()
791 struct aspeed_spi_flash *flash, in aspeed_spi_read_reg() argument
801 if (priv->spi_exec_op_cmd) { in aspeed_spi_read_reg()
802 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_read_reg()
806 aspeed_spi_start_user(priv, flash); in aspeed_spi_read_reg()
807 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); in aspeed_spi_read_reg()
808 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); in aspeed_spi_read_reg()
809 aspeed_spi_stop_user(priv, flash); in aspeed_spi_read_reg()
815 struct aspeed_spi_flash *flash, in aspeed_spi_write_reg() argument
826 if (priv->spi_exec_op_cmd) { in aspeed_spi_write_reg()
838 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_write_reg()
842 aspeed_spi_start_user(priv, flash); in aspeed_spi_write_reg()
843 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); in aspeed_spi_write_reg()
844 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); in aspeed_spi_write_reg()
845 aspeed_spi_stop_user(priv, flash); in aspeed_spi_write_reg()
852 * the scenario where spi controller is at 4B mode in aspeed_spi_write_reg()
853 * and flash site is at 3B mode after 3rd switch. in aspeed_spi_write_reg()
855 if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR)) in aspeed_spi_write_reg()
856 writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN, in aspeed_spi_write_reg()
857 &priv->regs->soft_rst_cmd_ctrl); in aspeed_spi_write_reg()
859 writel(readl(&priv->regs->ctrl) | (0x11 << flash->cs), &priv->regs->ctrl); in aspeed_spi_write_reg()
862 writel(readl(&priv->regs->ctrl) & ~(0x11 << flash->cs), &priv->regs->ctrl); in aspeed_spi_write_reg()
869 struct aspeed_spi_flash *flash, in aspeed_spi_send_cmd_addr() argument
875 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); in aspeed_spi_send_cmd_addr()
877 if(flash->write_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_WRITE_TO_FLASH)) in aspeed_spi_send_cmd_addr()
878 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_send_cmd_addr()
879 else if(flash->read_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_READ_FROM_FLASH)) in aspeed_spi_send_cmd_addr()
880 writel(flash->ce_ctrl_user | flash->read_iomode, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_send_cmd_addr()
884 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); in aspeed_spi_send_cmd_addr()
888 struct aspeed_spi_flash *flash, in aspeed_spi_read_user() argument
895 ASPEED_SPI_OP(flash->read_iomode, in aspeed_spi_read_user()
898 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8), in aspeed_spi_read_user()
901 if (priv->spi_exec_op_cmd) { in aspeed_spi_read_user()
902 op.addr.nbytes = cmdlen - 1 - op.dummy.nbytes; in aspeed_spi_read_user()
903 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1); in aspeed_spi_read_user()
904 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_read_user()
908 aspeed_spi_start_user(priv, flash); in aspeed_spi_read_user()
911 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, in aspeed_spi_read_user()
912 cmdlen - (flash->spi->read_dummy / 8), SPI_READ_FROM_FLASH); in aspeed_spi_read_user()
914 for (i = 0; i < (flash->spi->read_dummy / 8); i++) in aspeed_spi_read_user()
915 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); in aspeed_spi_read_user()
917 if (flash->read_iomode) { in aspeed_spi_read_user()
918 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], in aspeed_spi_read_user()
920 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->read_iomode); in aspeed_spi_read_user()
923 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); in aspeed_spi_read_user()
924 aspeed_spi_stop_user(priv, flash); in aspeed_spi_read_user()
930 struct aspeed_spi_flash *flash, in aspeed_spi_read_sfdp() argument
937 ASPEED_SPI_OP(flash->read_iomode, in aspeed_spi_read_sfdp()
940 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8), in aspeed_spi_read_sfdp()
943 if (priv->spi_exec_op_cmd) { in aspeed_spi_read_sfdp()
944 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1); in aspeed_spi_read_sfdp()
945 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_read_sfdp()
949 /* only 1-1-1 mode is used to read SFDP */ in aspeed_spi_read_sfdp()
950 aspeed_spi_start_user(priv, flash); in aspeed_spi_read_sfdp()
953 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, in aspeed_spi_read_sfdp()
954 cmdlen - (flash->spi->read_dummy / 8), 0); in aspeed_spi_read_sfdp()
956 for (i = 0; i < (flash->spi->read_dummy / 8); i++) in aspeed_spi_read_sfdp()
957 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); in aspeed_spi_read_sfdp()
959 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); in aspeed_spi_read_sfdp()
960 aspeed_spi_stop_user(priv, flash); in aspeed_spi_read_sfdp()
966 struct aspeed_spi_flash *flash, in aspeed_spi_write_user() argument
971 ASPEED_SPI_OP(flash->write_iomode, in aspeed_spi_write_user()
977 if (priv->spi_exec_op_cmd) { in aspeed_spi_write_user()
978 op.addr.nbytes = cmdlen - 1; in aspeed_spi_write_user()
979 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1); in aspeed_spi_write_user()
980 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_write_user()
984 aspeed_spi_start_user(priv, flash); in aspeed_spi_write_user()
987 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen, SPI_WRITE_TO_FLASH); in aspeed_spi_write_user()
990 if(flash->write_iomode == CE_CTRL_IO_QUAD_DATA) in aspeed_spi_write_user()
991 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_write_user()
993 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); in aspeed_spi_write_user()
995 aspeed_spi_stop_user(priv, flash); in aspeed_spi_write_user()
1000 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, in aspeed_spi_flash_to_addr() argument
1003 u8 addrlen = cmdlen - 1; in aspeed_spi_flash_to_addr()
1007 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might in aspeed_spi_flash_to_addr()
1018 struct aspeed_spi_flash *flash, in aspeed_spi_read() argument
1023 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, in aspeed_spi_read()
1024 cmdlen - (flash->spi->read_dummy/8)); in aspeed_spi_read()
1026 ASPEED_SPI_OP(flash->read_iomode, in aspeed_spi_read()
1029 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8), in aspeed_spi_read()
1032 if (priv->spi_exec_op_cmd) { in aspeed_spi_read()
1033 op.addr.nbytes = cmdlen - 1 - op.dummy.nbytes; in aspeed_spi_read()
1034 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1); in aspeed_spi_read()
1035 priv->spi_exec_op_cmd(priv, flash, &op); in aspeed_spi_read()
1041 * - if read SFDP content. in aspeed_spi_read()
1042 * - if the AHB window configured for the device is in aspeed_spi_read()
1044 * - if read offset is smaller than the decoded start address in aspeed_spi_read()
1045 * and the decoded range is not multiple of flash size. in aspeed_spi_read()
1047 if ((offset + len >= flash->ahb_size) || \ in aspeed_spi_read()
1048 (offset < ((int)flash->ahb_base & 0x0FFFFFFF) && \ in aspeed_spi_read()
1049 (((int)flash->ahb_base & 0x0FFFFFFF) % flash->spi->size) != 0)) { in aspeed_spi_read()
1050 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, in aspeed_spi_read()
1054 memcpy_fromio(read_buf, flash->ahb_base + offset, len); in aspeed_spi_read()
1060 struct aspeed_spi_flash *flash, in aspeed_spi_exec_op_cmd_mode() argument
1063 uint32_t cs = flash->cs; in aspeed_spi_exec_op_cmd_mode()
1073 op->io_mode, op->cmd.opcode, op->addr.val, op->dummy.nbytes, in aspeed_spi_exec_op_cmd_mode()
1074 op->data.nbytes, op->data.dir == ASPEED_SPI_DIR_IN ? "in" : "out"); in aspeed_spi_exec_op_cmd_mode()
1076 addr_mode_reg = readl(&priv->regs->ctrl); in aspeed_spi_exec_op_cmd_mode()
1078 addr_data_mask = readl(&priv->regs->cmd_ctrl); in aspeed_spi_exec_op_cmd_mode()
1080 ctrl_val = flash->ce_ctrl_fread & (~0xf0ff40c7); in aspeed_spi_exec_op_cmd_mode()
1081 ctrl_val |= op->io_mode; in aspeed_spi_exec_op_cmd_mode()
1083 ctrl_val |= op->cmd.opcode << 16; in aspeed_spi_exec_op_cmd_mode()
1086 if (op->addr.nbytes != 0) { in aspeed_spi_exec_op_cmd_mode()
1087 if (op->addr.nbytes == 3) in aspeed_spi_exec_op_cmd_mode()
1093 op_addr = flash->ahb_base + op->addr.val; in aspeed_spi_exec_op_cmd_mode()
1096 op_addr = flash->ahb_base; in aspeed_spi_exec_op_cmd_mode()
1099 if (op->dummy.nbytes != 0) { in aspeed_spi_exec_op_cmd_mode()
1100 ctrl_val |= ((op->dummy.nbytes & 0x3) << 6 | in aspeed_spi_exec_op_cmd_mode()
1101 ((op->dummy.nbytes & 0x4) >> 2) << 14); in aspeed_spi_exec_op_cmd_mode()
1105 if (op->data.nbytes != 0) { in aspeed_spi_exec_op_cmd_mode()
1107 if (op->data.nbytes < 4) in aspeed_spi_exec_op_cmd_mode()
1108 addr_data_mask |= ~((1 << op->data.nbytes) - 1); in aspeed_spi_exec_op_cmd_mode()
1110 data_byte = op->data.nbytes; in aspeed_spi_exec_op_cmd_mode()
1111 if (op->data.dir == ASPEED_SPI_DIR_OUT) { in aspeed_spi_exec_op_cmd_mode()
1113 memset(priv->tmp_buf, 0xff, ((data_byte / 4) + 1) * 4); in aspeed_spi_exec_op_cmd_mode()
1114 memcpy(priv->tmp_buf, op->data.buf.out, data_byte); in aspeed_spi_exec_op_cmd_mode()
1115 data_buf = priv->tmp_buf; in aspeed_spi_exec_op_cmd_mode()
1118 data_buf = op->data.buf.out; in aspeed_spi_exec_op_cmd_mode()
1121 data_buf = op->data.buf.in; in aspeed_spi_exec_op_cmd_mode()
1130 if (op->data.dir == ASPEED_SPI_DIR_OUT) in aspeed_spi_exec_op_cmd_mode()
1136 writel(ctrl_val, &priv->regs->ce_ctrl[cs]); in aspeed_spi_exec_op_cmd_mode()
1137 writel(addr_mode_reg, &priv->regs->ctrl); in aspeed_spi_exec_op_cmd_mode()
1138 writel(addr_data_mask, &priv->regs->cmd_ctrl); in aspeed_spi_exec_op_cmd_mode()
1143 /* trigger spi transmission or reception sequence */ in aspeed_spi_exec_op_cmd_mode()
1144 if (op->data.dir == ASPEED_SPI_DIR_OUT) in aspeed_spi_exec_op_cmd_mode()
1150 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[cs]); in aspeed_spi_exec_op_cmd_mode()
1151 writel(addr_mode_reg_backup, &priv->regs->ctrl); in aspeed_spi_exec_op_cmd_mode()
1152 writel(0x0, &priv->regs->cmd_ctrl); in aspeed_spi_exec_op_cmd_mode()
1160 struct udevice *bus = dev->parent; in aspeed_spi_xfer()
1162 struct aspeed_spi_flash *flash; in aspeed_spi_xfer() local
1163 u8 *cmd_buf = priv->cmd_buf; in aspeed_spi_xfer()
1168 flash = aspeed_spi_get_flash(dev); in aspeed_spi_xfer()
1169 if (!flash) in aspeed_spi_xfer()
1170 return -ENXIO; in aspeed_spi_xfer()
1174 priv->cmd_len = bitlen / 8; in aspeed_spi_xfer()
1175 memcpy(cmd_buf, dout, priv->cmd_len); in aspeed_spi_xfer()
1185 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, in aspeed_spi_xfer()
1186 din ? "read" : "write", priv->cmd_len, data_bytes); in aspeed_spi_xfer()
1189 if (priv->cmd_len == 0) { in aspeed_spi_xfer()
1191 return -1; in aspeed_spi_xfer()
1195 if (priv->cmd_len == 1) { in aspeed_spi_xfer()
1196 err = aspeed_spi_read_reg(priv, flash, in aspeed_spi_xfer()
1200 err = aspeed_spi_read_sfdp(priv, flash, in aspeed_spi_xfer()
1201 priv->cmd_len, in aspeed_spi_xfer()
1205 /* only for Cypress flash */ in aspeed_spi_xfer()
1206 iomode = flash->read_iomode; in aspeed_spi_xfer()
1207 flash->read_iomode = 0; in aspeed_spi_xfer()
1208 err = aspeed_spi_read_user(priv, flash, in aspeed_spi_xfer()
1209 priv->cmd_len, in aspeed_spi_xfer()
1212 flash->read_iomode = iomode; in aspeed_spi_xfer()
1214 err = aspeed_spi_read(priv, flash, in aspeed_spi_xfer()
1215 priv->cmd_len, in aspeed_spi_xfer()
1220 if (priv->cmd_len == 1) { in aspeed_spi_xfer()
1221 err = aspeed_spi_write_reg(priv, flash, in aspeed_spi_xfer()
1225 err = aspeed_spi_write_user(priv, flash, in aspeed_spi_xfer()
1226 priv->cmd_len, in aspeed_spi_xfer()
1234 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); in aspeed_spi_xfer()
1235 priv->cmd_len = 0; in aspeed_spi_xfer()
1249 reg_val = readl(&priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1260 reg_val = readl(&priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1265 writel(reg_val, &priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1270 writel(reg_val, &priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1277 reg_val = readl(&priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1281 writel(reg_val, &priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1298 bit_offset = (addr_width - 3) * 8; in aspeed_spi_fill_AQCD()
1301 reg_val = readl(&priv->regs->addr_qualified_cmd[i]); in aspeed_spi_fill_AQCD()
1311 reg_val = readl(&priv->regs->addr_qualified_cmd[i]); in aspeed_spi_fill_AQCD()
1316 writel(reg_val, &priv->regs->addr_qualified_cmd[i]); in aspeed_spi_fill_AQCD()
1324 writel(reg_val, &priv->regs->addr_qualified_cmd[i]); in aspeed_spi_fill_AQCD()
1335 reg_val = readl(&priv->regs->write_cmd_filter_ctrl); in aspeed_spi_cmd_filter_config()
1342 writel(reg_val, &priv->regs->write_cmd_filter_ctrl); in aspeed_spi_cmd_filter_config()
1354 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl); in aspeed_spi_write_addr_ftr_sanity()
1358 reg_val = readl(&priv->regs->write_addr_filter[i]); in aspeed_spi_write_addr_ftr_sanity()
1363 return -1; in aspeed_spi_write_addr_ftr_sanity()
1365 return -1; in aspeed_spi_write_addr_ftr_sanity()
1393 return -1; in aspeed_add_write_addr_ftr()
1396 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl); in aspeed_add_write_addr_ftr()
1400 end = offset + len - 1; in aspeed_add_write_addr_ftr()
1407 writel(reg_val, &priv->regs->write_addr_filter[i]); in aspeed_add_write_addr_ftr()
1409 writel(addr_ftr_ctrl, &priv->regs->write_addr_filter_ctrl); in aspeed_add_write_addr_ftr()
1420 return -1; in aspeed_add_write_addr_ftr()
1438 return -1; in aspeed_remove_write_addr_ftr()
1443 return -1; in aspeed_remove_write_addr_ftr()
1448 return -1; in aspeed_remove_write_addr_ftr()
1451 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl); in aspeed_remove_write_addr_ftr()
1457 reg_val = readl(&priv->regs->write_addr_filter[i]); in aspeed_remove_write_addr_ftr()
1465 writel(addr_ftr_ctrl, &priv->regs->write_addr_filter_ctrl); in aspeed_remove_write_addr_ftr()
1466 writel(0x0, &priv->regs->write_addr_filter[i]); in aspeed_remove_write_addr_ftr()
1474 return -1; in aspeed_remove_write_addr_ftr()
1482 struct udevice *bus = dev->parent; in aspeed_spi_mem_wlock()
1484 struct aspeed_spi_flash *flash; in aspeed_spi_mem_wlock() local
1490 flash = aspeed_spi_get_flash(dev); in aspeed_spi_mem_wlock()
1491 if (!flash) in aspeed_spi_mem_wlock()
1492 return -ENXIO; in aspeed_spi_mem_wlock()
1494 nor = flash->spi; in aspeed_spi_mem_wlock()
1497 nor->name, nor->read_opcode, nor->erase_opcode, nor->program_opcode); in aspeed_spi_mem_wlock()
1500 aspeed_spi_fill_FQCD(priv, nor->read_opcode); in aspeed_spi_mem_wlock()
1501 aspeed_spi_fill_AQCD(priv, nor->erase_opcode, nor->addr_width); in aspeed_spi_mem_wlock()
1502 aspeed_spi_fill_AQCD(priv, nor->program_opcode, nor->addr_width); in aspeed_spi_mem_wlock()
1503 aspeed_spi_cmd_filter_config(priv, flash->cs, true); in aspeed_spi_mem_wlock()
1513 return -1; in aspeed_spi_mem_wlock()
1520 struct udevice *bus = dev->parent; in aspeed_spi_mem_wunlock()
1526 return -1; in aspeed_spi_mem_wunlock()
1537 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); in aspeed_spi_child_pre_probe()
1540 return -ENXIO; in aspeed_spi_child_pre_probe()
1546 * AST2600 SPI memory controllers support multiple chip selects.
1548 * of its related flash size. Namely, the total decoded size
1549 * from flash 0 to flash N should be multiple of (N + 1) flash size.
1556 for (cs = len - 1; cs >= 0; cs--) { in aspeed_g6_adjust_decode_sz()
1570 * which should work fine for a single flash device.
1576 struct aspeed_spi_flash *flash) in aspeed_spi_flash_set_segment() argument
1586 flash->ahb_size = flash->spi->size; in aspeed_spi_flash_set_segment()
1588 if (priv->new_ver) { in aspeed_spi_flash_set_segment()
1590 reg_val = readl(&priv->regs->segment_addr[cs]); in aspeed_spi_flash_set_segment()
1594 G6_SEGMENT_ADDR_END(reg_val) - G6_SEGMENT_ADDR_START(reg_val); in aspeed_spi_flash_set_segment()
1600 decode_sz_arr[flash->cs] = flash->ahb_size; in aspeed_spi_flash_set_segment()
1601 aspeed_g6_adjust_decode_sz(decode_sz_arr, flash->cs + 1); in aspeed_spi_flash_set_segment()
1606 if (total_decode_sz > priv->ahb_size) { in aspeed_spi_flash_set_segment()
1608 return -ENOMEM; in aspeed_spi_flash_set_segment()
1612 struct aspeed_spi_flash *flash = &priv->flashes[cs]; in aspeed_spi_flash_set_segment() local
1614 flash->ahb_base = (void __iomem *)((u32)priv->ahb_base + cur_offset); in aspeed_spi_flash_set_segment()
1617 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, in aspeed_spi_flash_set_segment()
1618 (u32)flash->ahb_base + decode_sz_arr[cs]); in aspeed_spi_flash_set_segment()
1623 writel(seg_addr, &priv->regs->segment_addr[cs]); in aspeed_spi_flash_set_segment()
1624 flash->ahb_size = decode_sz_arr[cs]; in aspeed_spi_flash_set_segment()
1628 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, in aspeed_spi_flash_set_segment()
1629 (u32)flash->ahb_base + flash->ahb_size); in aspeed_spi_flash_set_segment()
1630 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); in aspeed_spi_flash_set_segment()
1637 struct aspeed_spi_flash *flash, in aspeed_spi_flash_init() argument
1643 struct udevice *bus = dev->parent; in aspeed_spi_flash_init()
1646 flash->spi = spi_flash; in aspeed_spi_flash_init()
1649 * The flash device has not been probed yet. Initial transfers in aspeed_spi_flash_init()
1653 if (!spi_flash->name) in aspeed_spi_flash_init()
1657 * The SPI flash device slave should not change, so initialize in aspeed_spi_flash_init()
1660 if (flash->init) in aspeed_spi_flash_init()
1664 flash->cs, in aspeed_spi_flash_init()
1665 spi_flash->name, spi_flash->flags, spi_flash->size, in aspeed_spi_flash_init()
1666 spi_flash->page_size, spi_flash->sector_size, in aspeed_spi_flash_init()
1667 spi_flash->erase_size); in aspeed_spi_flash_init()
1669 spi_flash->erase_opcode, in aspeed_spi_flash_init()
1670 spi_flash->read_opcode, spi_flash->program_opcode, in aspeed_spi_flash_init()
1671 spi_flash->read_dummy, slave->speed); in aspeed_spi_flash_init()
1673 flash->ce_ctrl_user = CE_CTRL_USERMODE; in aspeed_spi_flash_init()
1674 flash->max_freq = slave->speed; in aspeed_spi_flash_init()
1676 if(priv->new_ver) in aspeed_spi_flash_init()
1677 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); in aspeed_spi_flash_init()
1679 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); in aspeed_spi_flash_init()
1681 switch(flash->spi->read_opcode) { in aspeed_spi_flash_init()
1684 flash->read_iomode = CE_CTRL_IO_SINGLE; in aspeed_spi_flash_init()
1688 flash->read_iomode = CE_CTRL_IO_DUAL_DATA; in aspeed_spi_flash_init()
1692 flash->read_iomode = CE_CTRL_IO_QUAD_DATA; in aspeed_spi_flash_init()
1696 flash->read_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; in aspeed_spi_flash_init()
1701 switch(flash->spi->program_opcode) { in aspeed_spi_flash_init()
1704 flash->write_iomode = CE_CTRL_IO_SINGLE; in aspeed_spi_flash_init()
1708 flash->write_iomode = CE_CTRL_IO_QUAD_DATA; in aspeed_spi_flash_init()
1712 flash->write_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; in aspeed_spi_flash_init()
1717 if(priv->new_ver) { in aspeed_spi_flash_init()
1718 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | in aspeed_spi_flash_init()
1719 flash->read_iomode | in aspeed_spi_flash_init()
1720 CE_CTRL_CMD(flash->spi->read_opcode) | in aspeed_spi_flash_init()
1721 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | in aspeed_spi_flash_init()
1723 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk); in aspeed_spi_flash_init()
1725 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | in aspeed_spi_flash_init()
1726 flash->read_iomode | in aspeed_spi_flash_init()
1727 CE_CTRL_CMD(flash->spi->read_opcode) | in aspeed_spi_flash_init()
1728 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | in aspeed_spi_flash_init()
1732 if (flash->spi->addr_width == 4) in aspeed_spi_flash_init()
1733 writel(readl(&priv->regs->ctrl) | 0x11 << flash->cs, &priv->regs->ctrl); in aspeed_spi_flash_init()
1735 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, in aspeed_spi_flash_init()
1736 flash->ce_ctrl_user, flash->ce_ctrl_fread); in aspeed_spi_flash_init()
1739 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); in aspeed_spi_flash_init()
1742 ret = aspeed_spi_flash_set_segment(priv, flash); in aspeed_spi_flash_init()
1750 if (!dev_read_bool(bus, "timing-calibration-disabled")) { in aspeed_spi_flash_init()
1751 ret = aspeed_spi_timing_calibration(priv, flash); in aspeed_spi_flash_init()
1757 flash->init = true; in aspeed_spi_flash_init()
1764 struct udevice *bus = dev->parent; in aspeed_spi_claim_bus()
1767 struct aspeed_spi_flash *flash; in aspeed_spi_claim_bus() local
1771 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); in aspeed_spi_claim_bus()
1773 flash = aspeed_spi_get_flash(dev); in aspeed_spi_claim_bus()
1774 if (!flash) in aspeed_spi_claim_bus()
1775 return -ENODEV; in aspeed_spi_claim_bus()
1777 if (priv->new_ver) { in aspeed_spi_claim_bus()
1778 if (dev_read_bool(bus, "timing-calibration-disabled")) { in aspeed_spi_claim_bus()
1779 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); in aspeed_spi_claim_bus()
1780 flash->ce_ctrl_user &= CE_CTRL_FREQ_MASK; in aspeed_spi_claim_bus()
1781 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk); in aspeed_spi_claim_bus()
1782 flash->ce_ctrl_fread &= CE_CTRL_FREQ_MASK; in aspeed_spi_claim_bus()
1783 flash->ce_ctrl_fread |= CE_G6_CTRL_CLOCK_FREQ(read_hclk); in aspeed_spi_claim_bus()
1787 return aspeed_spi_flash_init(priv, flash, dev); in aspeed_spi_claim_bus()
1792 struct udevice *bus = dev->parent; in aspeed_spi_release_bus()
1795 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); in aspeed_spi_release_bus()
1798 return -ENODEV; in aspeed_spi_release_bus()
1805 debug("%s: setting mode to %x\n", bus->name, mode); in aspeed_spi_set_mode()
1809 pr_err("%s invalid QUAD IO mode\n", bus->name); in aspeed_spi_set_mode()
1810 return -EINVAL; in aspeed_spi_set_mode()
1820 debug("%s: setting speed to %u\n", bus->name, hz); in aspeed_spi_set_speed()
1833 (ofnode_device_is_compatible(node, "spi-flash") || in aspeed_spi_count_flash_devices()
1834 ofnode_device_is_compatible(node, "jedec,spi-nor"))) in aspeed_spi_count_flash_devices()
1843 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, in aspeed_spi_bind()
1844 bus->seq); in aspeed_spi_bind()
1860 priv->regs = (void __iomem *)res_regs.start; in aspeed_spi_probe()
1866 priv->ahb_base = (void __iomem *)res_ahb.start; in aspeed_spi_probe()
1867 priv->ahb_size = res_ahb.end - res_ahb.start + 1; in aspeed_spi_probe()
1871 pr_err("%s could not get clock: %d\n", bus->name, ret); in aspeed_spi_probe()
1875 priv->hclk_rate = clk_get_rate(&hclk); in aspeed_spi_probe()
1878 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); in aspeed_spi_probe()
1880 priv->flash_count = aspeed_spi_count_flash_devices(bus); in aspeed_spi_probe()
1881 if (priv->flash_count > priv->num_cs) { in aspeed_spi_probe()
1882 pr_err("%s has too many flash devices: %d\n", bus->name, in aspeed_spi_probe()
1883 priv->flash_count); in aspeed_spi_probe()
1884 return -EINVAL; in aspeed_spi_probe()
1887 if (!priv->flash_count) { in aspeed_spi_probe()
1888 pr_err("%s has no flash devices ?!\n", bus->name); in aspeed_spi_probe()
1889 return -ENODEV; in aspeed_spi_probe()
1892 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || in aspeed_spi_probe()
1893 device_is_compatible(bus, "aspeed,ast2600-spi")) { in aspeed_spi_probe()
1894 priv->new_ver = 1; in aspeed_spi_probe()
1897 if (dev_read_bool(bus, "aspeed-spi-command-mode")) { in aspeed_spi_probe()
1899 priv->tmp_buf = memalign(4, 512); in aspeed_spi_probe()
1900 priv->spi_exec_op_cmd = aspeed_spi_exec_op_cmd_mode; in aspeed_spi_probe()
1902 priv->spi_exec_op_cmd = NULL; in aspeed_spi_probe()
1907 * SPI controllers in aspeed_spi_probe()
1909 priv->is_fmc = dev_get_driver_data(bus); in aspeed_spi_probe()
1916 bus->name, priv->regs, priv->ahb_base, priv->flash_count, bus->seq); in aspeed_spi_probe()
1934 { .compatible = "aspeed,ast2600-fmc", .data = 1 },
1935 { .compatible = "aspeed,ast2600-spi", .data = 0 },
1936 { .compatible = "aspeed,ast2500-fmc", .data = 1 },
1937 { .compatible = "aspeed,ast2500-spi", .data = 0 },
1938 { .compatible = "aspeed,ast2400-fmc", .data = 1 },