128103120SPo LiuOverview 228103120SPo Liu========= 328103120SPo LiuC29XPCIE board is a series of Freescale PCIe add-in cards to perform 428103120SPo Liuas public key crypto accelerator or secure key management module. 528103120SPo LiuIt includes C293PCIE board, C293PCIE board and C291PCIE board. 628103120SPo LiuThe Freescale C29x family is a high performance crypto co-processor. 728103120SPo LiuIt combines a single e500v2 core with necessary SEC engines. 828103120SPo Liu(maximum core frequency 1000/1200 MHz). 928103120SPo Liu 1028103120SPo LiuThe C29xPCIE board features are as follows: 1128103120SPo LiuMemory subsystem: 1228103120SPo Liu - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) 1328103120SPo Liu - 64 Mbyte NOR flash single-chip memory 1428103120SPo Liu - 4 Gbyte NAND flash memory 1528103120SPo Liu - 1 Mbit AT24C1024 I2C EEPROM 1628103120SPo Liu - 16 Mbyte SPI memory 1728103120SPo Liu 1828103120SPo LiuInterfaces: 1928103120SPo Liu - 10/100/1000 BaseT Ethernet ports: 2028103120SPo Liu - eTSEC1, RGMII: one 10/100/1000 port 2128103120SPo Liu - eTSEC2, RGMII: one 10/100/1000 port 2228103120SPo Liu - DUART interface: 2328103120SPo Liu - DUART interface: supports two UARTs up to 115200 bps for 2428103120SPo Liu console display 2528103120SPo Liu 2628103120SPo LiuBoard connectors: 2728103120SPo Liu - Mini-ITX power supply connector 2828103120SPo Liu - JTAG/COP for debugging 2928103120SPo Liu 3028103120SPo LiuPhysical Memory Map on C29xPCIE 3128103120SPo Liu=============================== 3228103120SPo LiuAddress Start Address End Memory type 3328103120SPo Liu0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR 3428103120SPo Liu0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory 3528103120SPo Liu0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash 3628103120SPo Liu0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM 3728103120SPo Liu0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO 3828103120SPo Liu0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD 3928103120SPo Liu0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR 4028103120SPo Liu 4128103120SPo LiuSerial Port Configuration on C29xPCIE 4228103120SPo Liu===================================== 4328103120SPo LiuConfigure the serial port of the attached computer with the following values: 4428103120SPo Liu -Data rate: 115200 bps 4528103120SPo Liu -Number of data bits: 8 4628103120SPo Liu -Parity: None 4728103120SPo Liu -Number of Stop bits: 1 4828103120SPo Liu -Flow Control: Hardware/None 4928103120SPo Liu 5028103120SPo LiuSettings of DIP-switch 5128103120SPo Liu====================== 5228103120SPo Liu SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash 5328103120SPo Liu SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash 5428103120SPo LiuNote: 1 stands for 'off', 0 stands for 'on' 5528103120SPo Liu 56*a187559eSBin MengBuild and program U-Boot to NOR flash 5728103120SPo Liu================================== 5828103120SPo Liu1. Build u-boot.bin image example: 5928103120SPo Liu export ARCH=powerpc 6028103120SPo Liu export CROSS_COMPILE=/your_path/powerpc-linux-gnu- 6128103120SPo Liu make C293PCIE 6228103120SPo Liu 6328103120SPo Liu2. Program u-boot.bin into NOR flash 6428103120SPo Liu => tftp $loadaddr $uboot 65e222b1f3SPrabhakar Kushwaha => protect off eff40000 +$filesize 66e222b1f3SPrabhakar Kushwaha => erase eff40000 +$filesize 67e222b1f3SPrabhakar Kushwaha => cp.b $loadaddr eff40000 $filesize 6828103120SPo Liu 6928103120SPo Liu3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. 7028103120SPo Liu 7128103120SPo LiuAlternate NOR bank 7228103120SPo Liu================== 7328103120SPo LiuThere are four banks in C29XPCIE board, example to change bank booting: 7428103120SPo Liu1. Program u-boot.bin into alternate NOR bank 7528103120SPo Liu => tftp $loadaddr $uboot 76e222b1f3SPrabhakar Kushwaha => protect off e9f40000 +$filesize 77e222b1f3SPrabhakar Kushwaha => erase e9f40000 +$filesize 78e222b1f3SPrabhakar Kushwaha => cp.b $loadaddr e9f40000 $filesize 7928103120SPo Liu 8028103120SPo Liu2. Switch to alternate NOR bank 8128103120SPo Liu => cpld_cmd reset altbank [bank] 8228103120SPo Liu - [bank] bank value select 1-4 8328103120SPo Liu - bank 1 on the flash 0x0000000~0x0ffffff 8428103120SPo Liu - bank 2 on the flash 0x1000000~0x1ffffff 8528103120SPo Liu - bank 3 on the flash 0x2000000~0x2ffffff 8628103120SPo Liu - bank 4 on the flash 0x3000000~0x3ffffff 8728103120SPo Liu or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. 8828103120SPo Liu 89*a187559eSBin MengBuild and program U-Boot to SPI flash 9028103120SPo Liu================================== 9128103120SPo Liu1. Build u-boot-spi.bin image 9228103120SPo Liu make C29xPCIE_SPIFLASH_config; make 9328103120SPo Liu Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin. 9428103120SPo Liu 9528103120SPo Liu2. Program u-boot-spi.bin into SPI flash 9628103120SPo Liu => tftp $loadaddr $uboot-spi 9728103120SPo Liu => sf erase 0 100000 9828103120SPo Liu => sf write $loadaddr 0 $filesize 9928103120SPo Liu 10028103120SPo Liu3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on. 101