1 /* 2 * Generated by info2header.py 3 * Do not edit it. 4 */ 5 6 #define OTP_INFO_VER "2.0.0" 7 #define OTP_REG_RESERVED -1 8 #define OTP_REG_VALUE -2 9 #define OTP_REG_VALID_BIT -3 10 11 struct otpstrap_info { 12 signed char bit_offset; 13 signed char length; 14 signed char value; 15 const char *information; 16 }; 17 18 struct otpconf_info { 19 signed char dw_offset; 20 signed char bit_offset; 21 signed char length; 22 signed char value; 23 const char *information; 24 }; 25 26 struct scu_info { 27 signed char bit_offset; 28 signed char length; 29 const char *information; 30 }; 31 32 static const struct otpstrap_info a0_strap_info[] = { 33 { 0, 1, 0, "Disable Secure Boot" }, 34 { 0, 1, 1, "Enable Secure Boot" }, 35 { 1, 1, 0, "Disable boot from eMMC" }, 36 { 1, 1, 1, "Enable boot from eMMC" }, 37 { 2, 1, 0, "Disable Boot from debug SPI" }, 38 { 2, 1, 1, "Enable Boot from debug SPI" }, 39 { 3, 1, 0, "Enable ARM CM3" }, 40 { 3, 1, 1, "Disable ARM CM3" }, 41 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 42 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 43 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 44 { 5, 1, 1, "MAC 1 : RGMII" }, 45 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 46 { 6, 1, 1, "MAC 2 : RGMII" }, 47 { 7, 2, 0, "CPU Frequency : 1GHz" }, 48 { 7, 2, 1, "CPU Frequency : 800MHz" }, 49 { 7, 2, 2, "CPU Frequency : 1.2GHz" }, 50 { 7, 2, 3, "CPU Frequency : 1.4GHz" }, 51 { 10, 2, 0, "HCLK ratio AXI:AHB = default" }, 52 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 53 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 54 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 55 { 12, 2, 0, "VGA memory size : 8MB" }, 56 { 12, 2, 1, "VGA memory size : 16MB" }, 57 { 12, 2, 2, "VGA memory size : 32MB" }, 58 { 12, 2, 3, "VGA memory size : 64MB" }, 59 { 15, 1, 0, "CPU/AXI clock ratio : 2:1" }, 60 { 15, 1, 1, "CPU/AXI clock ratio : 1:1" }, 61 { 16, 1, 0, "Enable ARM JTAG debug" }, 62 { 16, 1, 1, "Disable ARM JTAG debug" }, 63 { 17, 1, 0, "VGA class code : vga_device" }, 64 { 17, 1, 1, "VGA class code : video_device" }, 65 { 18, 1, 0, "Enable debug interfaces 0" }, 66 { 18, 1, 1, "Disable debug interfaces 0" }, 67 { 19, 1, 0, "Boot from eMMC speed mode : normal" }, 68 { 19, 1, 1, "Boot from eMMC speed mode : high" }, 69 { 20, 1, 0, "Disable Pcie EHCI device" }, 70 { 20, 1, 1, "Enable Pcie EHCI device" }, 71 { 21, 1, 0, "Enable ARM JTAG trust world debug" }, 72 { 21, 1, 1, "Disable ARM JTAG trust world debug" }, 73 { 22, 1, 0, "Normal BMC mode" }, 74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 75 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 76 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 77 { 24, 1, 0, "Enable watchdog to reset full chip" }, 78 { 24, 1, 1, "Disable watchdog to reset full chip" }, 79 { 25, 2, 0, "Internal bridge speed selection : 1x" }, 80 { 25, 2, 1, "Internal bridge speed selection : 1/2x" }, 81 { 25, 2, 2, "Internal bridge speed selection : 1/4x" }, 82 { 25, 2, 3, "Internal bridge speed selection : 1/8x" }, 83 { 29, 1, 0, "Enable RVAS function" }, 84 { 29, 1, 1, "Disable RVAS function" }, 85 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 86 { 32, 1, 1, "MAC 3 : RGMII" }, 87 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 88 { 33, 1, 1, "MAC 4 : RGMII" }, 89 { 34, 1, 0, "SuperIO configuration address : 0x2e" }, 90 { 34, 1, 1, "SuperIO configuration address : 0x4e" }, 91 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 92 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 93 { 36, 1, 0, "Enable debug interfaces 1" }, 94 { 36, 1, 1, "Disable debug interfaces 1" }, 95 { 37, 1, 0, "Disable ACPI function" }, 96 { 37, 1, 1, "Enable ACPI function" }, 97 { 38, 1, 0, "Select LPC/eSPI : eSPI" }, 98 { 38, 1, 1, "Select LPC/eSPI : LPC" }, 99 { 39, 1, 0, "Disable SAFS mode" }, 100 { 39, 1, 1, "Enable SAFS mode" }, 101 { 40, 1, 0, "Disable boot from uart5" }, 102 { 40, 1, 1, "Enable boot from uart5" }, 103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" }, 104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" }, 105 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 106 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 107 { 43, 1, 0, "Disable boot SPI or eMMC ABR" }, 108 { 43, 1, 1, "Enable boot SPI or eMMC ABR" }, 109 { 44, 1, 0, "Boot SPI ABR Mode : dual" }, 110 { 44, 1, 1, "Boot SPI ABR Mode : single" }, 111 { 45, 3, 0, "Boot SPI flash size : 0MB" }, 112 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 113 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 114 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 115 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 116 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 117 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 118 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 119 { 48, 1, 0, "Disable host SPI ABR" }, 120 { 48, 1, 1, "Enable host SPI ABR" }, 121 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 122 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 123 { 50, 1, 0, "Host SPI ABR mode : dual" }, 124 { 50, 1, 1, "Host SPI ABR mode : single" }, 125 { 51, 3, 0, "Host SPI flash size : 0MB" }, 126 { 51, 3, 1, "Host SPI flash size : 2MB" }, 127 { 51, 3, 2, "Host SPI flash size : 4MB" }, 128 { 51, 3, 3, "Host SPI flash size : 8MB" }, 129 { 51, 3, 4, "Host SPI flash size : 16MB" }, 130 { 51, 3, 5, "Host SPI flash size : 32MB" }, 131 { 51, 3, 6, "Host SPI flash size : 64MB" }, 132 { 51, 3, 7, "Host SPI flash size : 128MB" }, 133 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 134 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 135 { 55, 2, 0, "Boot SPI CRTM size : 0KB" }, 136 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 137 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 138 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" }, 139 { 57, 2, 0, "Host SPI CRTM size : 0KB" }, 140 { 57, 2, 1, "Host SPI CRTM size : 1024KB" }, 141 { 57, 2, 2, "Host SPI CRTM size : 2048KB" }, 142 { 57, 2, 3, "Host SPI CRTM size : 4096KB" }, 143 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 144 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 145 { 60, 1, 0, "Disable GPIO pass through" }, 146 { 60, 1, 1, "Enable GPIO pass through" }, 147 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 148 { 62, 1, 1, "Enable dedicate GPIO strap pins" } 149 }; 150 151 static const struct otpstrap_info a1_strap_info[] = { 152 { 0, 1, 0, "Disable Secure Boot" }, 153 { 0, 1, 1, "Enable Secure Boot" }, 154 { 1, 1, 0, "Disable boot from eMMC" }, 155 { 1, 1, 1, "Enable boot from eMMC" }, 156 { 2, 1, 0, "Disable Boot from debug SPI" }, 157 { 2, 1, 1, "Enable Boot from debug SPI" }, 158 { 3, 1, 0, "Enable ARM CM3" }, 159 { 3, 1, 1, "Disable ARM CM3" }, 160 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 161 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 162 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 163 { 5, 1, 1, "MAC 1 : RGMII" }, 164 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 165 { 6, 1, 1, "MAC 2 : RGMII" }, 166 { 7, 3, 0, "CPU Frequency : 1.2GHz" }, 167 { 7, 3, 1, "CPU Frequency : 1.6GHz" }, 168 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 169 { 7, 3, 3, "CPU Frequency : 1.6GHz" }, 170 { 7, 3, 4, "CPU Frequency : 800MHz" }, 171 { 7, 3, 5, "CPU Frequency : 800MHz" }, 172 { 7, 3, 6, "CPU Frequency : 800MHz" }, 173 { 7, 3, 7, "CPU Frequency : 800MHz" }, 174 { 10, 2, 0, "HCLK ratio AXI:AHB = default" }, 175 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 176 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 177 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 178 { 12, 2, 0, "VGA memory size : 8MB" }, 179 { 12, 2, 1, "VGA memory size : 16MB" }, 180 { 12, 2, 2, "VGA memory size : 32MB" }, 181 { 12, 2, 3, "VGA memory size : 64MB" }, 182 { 14, 1, OTP_REG_RESERVED, "Reserved" }, 183 { 15, 1, 0, "CPU/AXI clock ratio : 2:1" }, 184 { 15, 1, 1, "CPU/AXI clock ratio : 1:1" }, 185 { 16, 1, 0, "Enable ARM JTAG debug" }, 186 { 16, 1, 1, "Disable ARM JTAG debug" }, 187 { 17, 1, 0, "VGA class code : vga_device" }, 188 { 17, 1, 1, "VGA class code : video_device" }, 189 { 18, 1, 0, "Enable debug interfaces 0" }, 190 { 18, 1, 1, "Disable debug interfaces 0" }, 191 { 19, 1, 0, "Boot from eMMC speed mode : normal" }, 192 { 19, 1, 1, "Boot from eMMC speed mode : high" }, 193 { 20, 1, 0, "Disable Pcie EHCI device" }, 194 { 20, 1, 1, "Enable Pcie EHCI device" }, 195 { 21, 1, 0, "Enable ARM JTAG trust world debug" }, 196 { 21, 1, 1, "Disable ARM JTAG trust world debug" }, 197 { 22, 1, 0, "Normal BMC mode" }, 198 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 199 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 200 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 201 { 24, 1, 0, "Enable watchdog to reset full chip" }, 202 { 24, 1, 1, "Disable watchdog to reset full chip" }, 203 { 25, 2, 0, "Internal bridge speed selection : 1x" }, 204 { 25, 2, 1, "Internal bridge speed selection : 1/2x" }, 205 { 25, 2, 2, "Internal bridge speed selection : 1/4x" }, 206 { 25, 2, 3, "Internal bridge speed selection : 1/8x" }, 207 { 27, 2, 0, "Reset Source of eMMC part : GPIOY3" }, 208 { 27, 2, 1, "Reset Source of eMMC part : GPIO18A2" }, 209 { 27, 2, 2, "Reset Source of eMMC part : GPIO18B6" }, 210 { 27, 2, 3, "Reset Source of eMMC part : GPIO18A2" }, 211 { 29, 1, 0, "Enable RVAS function" }, 212 { 29, 1, 1, "Disable RVAS function" }, 213 { 30, 2, OTP_REG_RESERVED, "Reserved" }, 214 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 215 { 32, 1, 1, "MAC 3 : RGMII" }, 216 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 217 { 33, 1, 1, "MAC 4 : RGMII" }, 218 { 34, 1, 0, "SuperIO configuration address : 0x2e" }, 219 { 34, 1, 1, "SuperIO configuration address : 0x4e" }, 220 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 221 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 222 { 36, 1, 0, "Enable debug interfaces 1" }, 223 { 36, 1, 1, "Disable debug interfaces 1" }, 224 { 37, 1, 0, "Disable ACPI function" }, 225 { 37, 1, 1, "Enable ACPI function" }, 226 { 38, 1, 0, "Select LPC/eSPI : eSPI" }, 227 { 38, 1, 1, "Select LPC/eSPI : LPC" }, 228 { 39, 1, 0, "Disable SAFS mode" }, 229 { 39, 1, 1, "Enable SAFS mode" }, 230 { 40, 1, 0, "Disable boot from uart5" }, 231 { 40, 1, 1, "Enable boot from uart5" }, 232 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" }, 233 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" }, 234 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 235 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 236 { 43, 1, 0, "Disable boot SPI or eMMC ABR" }, 237 { 43, 1, 1, "Enable boot SPI or eMMC ABR" }, 238 { 44, 1, 0, "Boot SPI ABR Mode : dual" }, 239 { 44, 1, 1, "Boot SPI ABR Mode : single" }, 240 { 45, 3, 0, "Boot SPI flash size : 0MB" }, 241 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 242 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 243 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 244 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 245 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 246 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 247 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 248 { 48, 1, 0, "Disable host SPI ABR" }, 249 { 48, 1, 1, "Enable host SPI ABR" }, 250 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 251 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 252 { 50, 1, 0, "Host SPI ABR mode : dual" }, 253 { 50, 1, 1, "Host SPI ABR mode : single" }, 254 { 51, 3, 0, "Host SPI flash size : 0MB" }, 255 { 51, 3, 1, "Host SPI flash size : 2MB" }, 256 { 51, 3, 2, "Host SPI flash size : 4MB" }, 257 { 51, 3, 3, "Host SPI flash size : 8MB" }, 258 { 51, 3, 4, "Host SPI flash size : 16MB" }, 259 { 51, 3, 5, "Host SPI flash size : 32MB" }, 260 { 51, 3, 6, "Host SPI flash size : 64MB" }, 261 { 51, 3, 7, "Host SPI flash size : 128MB" }, 262 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 263 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 264 { 55, 2, 0, "Boot SPI CRTM size : 0KB" }, 265 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 266 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 267 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" }, 268 { 57, 2, 0, "Host SPI CRTM size : 0KB" }, 269 { 57, 2, 1, "Host SPI CRTM size : 1024KB" }, 270 { 57, 2, 2, "Host SPI CRTM size : 2048KB" }, 271 { 57, 2, 3, "Host SPI CRTM size : 4096KB" }, 272 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 273 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 274 { 60, 1, 0, "Disable GPIO pass through" }, 275 { 60, 1, 1, "Enable GPIO pass through" }, 276 { 61, 1, OTP_REG_RESERVED, "Reserved" }, 277 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 278 { 62, 1, 1, "Enable dedicate GPIO strap pins" }, 279 { 63, 1, OTP_REG_RESERVED, "Reserved" } 280 }; 281 282 static const struct otpconf_info a0_conf_info[] = { 283 { 0, 1, 1, 0, "Disable Secure Boot" }, 284 { 0, 1, 1, 1, "Enable Secure Boot" }, 285 { 0, 3, 1, 0, "User region ECC disable" }, 286 { 0, 3, 1, 1, "User region ECC enable" }, 287 { 0, 4, 1, 0, "Secure Region ECC disable" }, 288 { 0, 4, 1, 1, "Secure Region ECC enable" }, 289 { 0, 5, 1, 0, "Enable low security key" }, 290 { 0, 5, 1, 1, "Disable low security key" }, 291 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 292 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 293 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 294 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 295 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 296 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 297 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 298 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 299 { 0, 12, 2, 0, "SHA mode : SHA224" }, 300 { 0, 12, 2, 1, "SHA mode : SHA256" }, 301 { 0, 12, 2, 2, "SHA mode : SHA384" }, 302 { 0, 12, 2, 3, "SHA mode : SHA512" }, 303 { 0, 14, 1, 0, "Enable patch code" }, 304 { 0, 14, 1, 1, "Disable patch code" }, 305 { 0, 15, 1, 0, "Enable Boot from Uart" }, 306 { 0, 15, 1, 1, "Disable Boot from Uart" }, 307 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 308 { 0, 22, 1, 0, "Secure Region : Writable" }, 309 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 310 { 0, 23, 1, 0, "User Region : Writable" }, 311 { 0, 23, 1, 1, "User Region : Write Protect" }, 312 { 0, 24, 1, 0, "Configure Region : Writable" }, 313 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 314 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 315 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 316 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 317 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 318 { 0, 27, 1, 0, "Disable image encryption" }, 319 { 0, 27, 1, 1, "Enable image encryption" }, 320 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 321 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 322 { 0, 31, 1, 0, "OTP memory lock disable" }, 323 { 0, 31, 1, 1, "OTP memory lock enable" }, 324 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 325 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 326 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 327 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 328 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 329 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 330 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 331 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 332 }; 333 334 static const struct otpconf_info a1_conf_info[] = { 335 { 0, 1, 1, 0, "Disable Secure Boot" }, 336 { 0, 1, 1, 1, "Enable Secure Boot" }, 337 { 0, 3, 1, 0, "User region ECC disable" }, 338 { 0, 3, 1, 1, "User region ECC enable" }, 339 { 0, 4, 1, 0, "Secure Region ECC disable" }, 340 { 0, 4, 1, 1, "Secure Region ECC enable" }, 341 { 0, 5, 1, 0, "Enable low security key" }, 342 { 0, 5, 1, 1, "Disable low security key" }, 343 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 344 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 345 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 346 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 347 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 348 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 349 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 350 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 351 { 0, 12, 2, 0, "SHA mode : SHA224" }, 352 { 0, 12, 2, 1, "SHA mode : SHA256" }, 353 { 0, 12, 2, 2, "SHA mode : SHA384" }, 354 { 0, 12, 2, 3, "SHA mode : SHA512" }, 355 { 0, 14, 1, 0, "Disable patch code" }, 356 { 0, 14, 1, 1, "Enable patch code" }, 357 { 0, 15, 1, 0, "Enable Boot from Uart" }, 358 { 0, 15, 1, 1, "Disable Boot from Uart" }, 359 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 360 { 0, 22, 1, 0, "Secure Region : Writable" }, 361 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 362 { 0, 23, 1, 0, "User Region : Writable" }, 363 { 0, 23, 1, 1, "User Region : Write Protect" }, 364 { 0, 24, 1, 0, "Configure Region : Writable" }, 365 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 366 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 367 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 368 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 369 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 370 { 0, 27, 1, 0, "Disable image encryption" }, 371 { 0, 27, 1, 1, "Enable image encryption" }, 372 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 373 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 374 { 0, 31, 1, 0, "OTP memory lock disable" }, 375 { 0, 31, 1, 1, "OTP memory lock enable" }, 376 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 377 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 378 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 379 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 380 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 381 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 382 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" }, 383 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" }, 384 { 7, 31, 1, 0, "Disable chip security setting" }, 385 { 7, 31, 1, 1, "Enable chip security setting" }, 386 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 387 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 388 }; 389 390 static const struct otpconf_info a2_conf_info[] = { 391 { 0, 0, 1, 0, "Enable OTP Memory BIST Mode" }, 392 { 0, 0, 1, 1, "Disable OTP Memory BIST Mode" }, 393 { 0, 1, 1, 0, "Disable Secure Boot" }, 394 { 0, 1, 1, 1, "Enable Secure Boot" }, 395 { 0, 3, 1, 0, "User region ECC disable" }, 396 { 0, 3, 1, 1, "User region ECC enable" }, 397 { 0, 4, 1, 0, "Secure Region ECC disable" }, 398 { 0, 4, 1, 1, "Secure Region ECC enable" }, 399 { 0, 5, 1, 0, "Enable low security key" }, 400 { 0, 5, 1, 1, "Disable low security key" }, 401 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 402 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 403 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 404 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 405 { 0, 9, 1, 0, "ROM code will dump boot messages" }, 406 { 0, 9, 1, 1, "ROM code message is disabled" }, 407 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 408 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 409 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 410 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 411 { 0, 12, 2, 0, "SHA mode : SHA224" }, 412 { 0, 12, 2, 1, "SHA mode : SHA256" }, 413 { 0, 12, 2, 2, "SHA mode : SHA384" }, 414 { 0, 12, 2, 3, "SHA mode : SHA512" }, 415 { 0, 14, 1, 0, "Enable patch code" }, 416 { 0, 14, 1, 1, "Disable patch code" }, 417 { 0, 15, 1, 0, "Enable Boot from Uart" }, 418 { 0, 15, 1, 1, "Disable Boot from Uart" }, 419 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 420 { 0, 22, 1, 0, "Secure Region : Writable" }, 421 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 422 { 0, 23, 1, 0, "User Region : Writable" }, 423 { 0, 23, 1, 1, "User Region : Write Protect" }, 424 { 0, 24, 1, 0, "Configure Region : Writable" }, 425 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 426 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 427 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 428 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 429 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 430 { 0, 27, 1, 0, "Disable image encryption" }, 431 { 0, 27, 1, 1, "Enable image encryption" }, 432 { 0, 28, 1, 0, "Enable Flash Patch Code" }, 433 { 0, 28, 1, 1, "Disable Flash Patch Code" }, 434 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 435 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 436 { 0, 30, 1, 0, "Boot from UART/VUART when normal boot is fail" }, 437 { 0, 30, 1, 1, "Disable auto UART/VUART boot option" }, 438 { 0, 31, 1, 0, "OTP memory lock disable" }, 439 { 0, 31, 1, 1, "OTP memory lock enable" }, 440 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 441 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 442 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 443 { 3, 16, 1, 0, "Boot from UART using: UART5" }, 444 { 3, 16, 1, 1, "Boot from UART using: UART1" }, 445 { 3, 17, 1, 0, "Enable Auto Boot from UART" }, 446 { 3, 17, 1, 1, "Disable Auto Boot from UART" }, 447 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" }, 448 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" }, 449 { 3, 19, 1, 0, "Enable Auto Boot from VUART2 over LPC" }, 450 { 3, 19, 1, 1, "Disable Auto Boot from VUART2 over LPC" }, 451 { 3, 20, 1, 0, "Enable ROM code based programming control" }, 452 { 3, 20, 1, 1, "Disable ROM code based programming control" }, 453 { 3, 21, 3, OTP_REG_VALUE, "Rollback prevention shift bit : 0x%x" }, 454 { 3, 24, 6, OTP_REG_VALUE, "Extra Data Write Protection Region size (DW): 0x%x" }, 455 { 3, 30, 1, 0, "Do not erase signature data after secure boot check" }, 456 { 3, 30, 1, 1, "Erase signature data after secure boot check" }, 457 { 3, 31, 1, 0, "Do not erase RSA public key after secure boot check" }, 458 { 3, 31, 1, 1, "Erase RSA public key after secure boot check" }, 459 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 460 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 461 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 462 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" }, 463 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" }, 464 { 7, 31, 1, 0, "Disable chip security setting" }, 465 { 7, 31, 1, 1, "Enable chip security setting" }, 466 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 467 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 468 }; 469 470 static const struct otpconf_info a3_conf_info[] = { 471 { 0, 0, 1, 0, "Enable OTP Memory BIST Mode" }, 472 { 0, 0, 1, 1, "Disable OTP Memory BIST Mode" }, 473 { 0, 1, 1, 0, "Disable Secure Boot" }, 474 { 0, 1, 1, 1, "Enable Secure Boot" }, 475 { 0, 3, 1, 0, "User region ECC disable" }, 476 { 0, 3, 1, 1, "User region ECC enable" }, 477 { 0, 4, 1, 0, "Secure Region ECC disable" }, 478 { 0, 4, 1, 1, "Secure Region ECC enable" }, 479 { 0, 5, 1, 0, "Enable low security key" }, 480 { 0, 5, 1, 1, "Disable low security key" }, 481 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 482 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 483 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 484 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 485 { 0, 9, 1, 0, "ROM code will dump boot messages" }, 486 { 0, 9, 1, 1, "ROM code message is disabled" }, 487 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 488 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 489 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 490 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 491 { 0, 12, 2, 0, "SHA mode : SHA224" }, 492 { 0, 12, 2, 1, "SHA mode : SHA256" }, 493 { 0, 12, 2, 2, "SHA mode : SHA384" }, 494 { 0, 12, 2, 3, "SHA mode : SHA512" }, 495 { 0, 14, 1, 0, "Enable patch code" }, 496 { 0, 14, 1, 1, "Disable patch code" }, 497 { 0, 15, 1, 0, "Enable Boot from Uart" }, 498 { 0, 15, 1, 1, "Disable Boot from Uart" }, 499 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 500 { 0, 22, 1, 0, "Secure Region : Writable" }, 501 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 502 { 0, 23, 1, 0, "User Region : Writable" }, 503 { 0, 23, 1, 1, "User Region : Write Protect" }, 504 { 0, 24, 1, 0, "Configure Region : Writable" }, 505 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 506 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 507 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 508 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 509 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 510 { 0, 27, 1, 0, "Disable image encryption" }, 511 { 0, 27, 1, 1, "Enable image encryption" }, 512 { 0, 28, 1, 0, "Enable Flash Patch Code" }, 513 { 0, 28, 1, 1, "Disable Flash Patch Code" }, 514 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 515 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 516 { 0, 30, 1, 0, "Boot from UART/VUART when normal boot is fail" }, 517 { 0, 30, 1, 1, "Disable auto UART/VUART boot option" }, 518 { 0, 31, 1, 0, "OTP memory lock disable" }, 519 { 0, 31, 1, 1, "OTP memory lock enable" }, 520 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 521 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 522 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 523 { 3, 16, 1, 0, "Boot from UART using: UART5" }, 524 { 3, 16, 1, 1, "Boot from UART using: UART1" }, 525 { 3, 17, 1, 0, "Enable Auto Boot from UART" }, 526 { 3, 17, 1, 1, "Disable Auto Boot from UART" }, 527 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" }, 528 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" }, 529 { 3, 19, 1, 0, "Enable Auto Boot from VUART2 over LPC" }, 530 { 3, 19, 1, 1, "Disable Auto Boot from VUART2 over LPC" }, 531 { 3, 20, 1, 0, "Enable ROM code based programming control" }, 532 { 3, 20, 1, 1, "Disable ROM code based programming control" }, 533 { 3, 21, 3, OTP_REG_VALUE, "Rollback prevention shift bit : 0x%x" }, 534 { 3, 24, 6, OTP_REG_VALUE, "Extra Data Write Protection Region size (DW): 0x%x" }, 535 { 3, 30, 1, 0, "Do not erase signature data after secure boot check" }, 536 { 3, 30, 1, 1, "Erase signature data after secure boot check" }, 537 { 3, 31, 1, 0, "Do not erase RSA public key after secure boot check" }, 538 { 3, 31, 1, 1, "Erase RSA public key after secure boot check" }, 539 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 540 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 541 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 542 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" }, 543 { 7, 15, 1, 0, "Disable write protection for SCU0C8 and SCU0D8" }, 544 { 7, 15, 1, 1, "Enable write protection for SCU0C8 and SCU0D8" }, 545 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" }, 546 { 7, 31, 1, 0, "Disable chip security setting" }, 547 { 7, 31, 1, 1, "Enable chip security setting" }, 548 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 549 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 550 }; 551 552 static const struct scu_info a1_scu_info[] = { 553 { 0, 1, "Disable ARM CA7 CPU boot (TXD5)" }, 554 { 1, 1, "Reserved0" }, 555 { 2, 1, "Enable boot from eMMC" }, 556 { 3, 1, "Boot from debug SPI" }, 557 { 4, 1, "Disable ARM CM3" }, 558 { 5, 1, "Enable dedicated VGA BIOS ROM" }, 559 { 6, 1, "MAC 1 RMII mode" }, 560 { 7, 1, "MAC 2 RMII mode" }, 561 { 8, 3, "CPU frequency" }, 562 { 11, 2, "HCLK ratio" }, 563 { 13, 2, "VGA memory size" }, 564 { 15, 1, "OTPSTRAP[14] Reserved" }, 565 { 16, 1, "CPU/AXI clock ratio" }, 566 { 17, 1, "Disable ARM JTAG debug" }, 567 { 18, 1, "VGA class code" }, 568 { 19, 1, "Disable debug 0" }, 569 { 20, 1, "Boot from eMMC speed mode" }, 570 { 21, 1, "Enable PCIe EHCI" }, 571 { 22, 1, "Disable ARM JTAG trust world debug" }, 572 { 23, 1, "Disable dedicated BMC function" }, 573 { 24, 1, "Enable dedicate PCIe RC reset" }, 574 { 25, 1, "Disable watchdog to reset full chip" }, 575 { 26, 2, "Internal bridge speed selection" }, 576 { 28, 2, "Select Reset Source of eMMC part" }, 577 { 30, 1, "Disable RVAS function" }, 578 { 31, 1, "Enable boot SPI auxiliary control pins(mirror)" }, 579 { 32, 1, "MAC 3 RMII mode" }, 580 { 33, 1, "MAC 4 RMII mode" }, 581 { 34, 1, "SuperIO configuration address selection" }, 582 { 35, 1, "Disable LPC to decode SuperIO" }, 583 { 36, 1, "Disable debug 1" }, 584 { 37, 1, "Enable ACPI" }, 585 { 38, 1, "Select LPC/eSPI" }, 586 { 39, 1, "Enable SAFS" }, 587 { 40, 1, "Enable boot from uart5" }, 588 { 41, 1, "Enable boot SPI 3B address mode auto-clear" }, 589 { 42, 1, "Enable SPI 3B/4B address mode auto detection" }, 590 { 43, 1, "Enable boot SPI or eMMC ABR" }, 591 { 44, 1, "Boot SPI ABR Mode" }, 592 { 45, 3, "Boot SPI flash size" }, 593 { 48, 1, "Enable host SPI ABR" }, 594 { 49, 1, "Enable host SPI ABR mode select pin" }, 595 { 50, 1, "Host SPI ABR Mode" }, 596 { 51, 3, "Host SPI flash size" }, 597 { 54, 1, "Enable boot SPI auxiliary control pins" }, 598 { 55, 2, "Boot SPI CRTM size" }, 599 { 57, 2, "Host SPI CRTM size" }, 600 { 59, 1, "Enable host SPI auxiliary control pins" }, 601 { 60, 1, "Enable GPIO Pass Through" }, 602 { 61, 1, "OTPSTRAP[3D] Reserved" }, 603 { 62, 1, "Enable Dedicate GPIO Strap Pins" }, 604 { 63, 1, "OTPSTRAP[3F] Reserved" } 605 }; 606 607